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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-10-06 22:26:47 +0200 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-07 17:09:28 +0800 |
| commit | 8baf3d07567f886be683aa26e3fc92346b604a93 (patch) | |
| tree | 13aefc58587c50e5d144f8d06d6e68de7719b2eb | |
| parent | 9455c91957590ca6d4520cfe0955f9f9f1349f82 (diff) | |
| download | gdb-8baf3d07567f886be683aa26e3fc92346b604a93.zip gdb-8baf3d07567f886be683aa26e3fc92346b604a93.tar.gz gdb-8baf3d07567f886be683aa26e3fc92346b604a93.tar.bz2 | |
RISC-V: Support aliases for Zbs instructions
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.
2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/
* testsuite/gas/riscv/b-ext.d: Add tests.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
| -rw-r--r-- | gas/testsuite/gas/riscv/b-ext-64.d | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/b-ext-64.s | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/b-ext.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/b-ext.s | 5 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
5 files changed, 30 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d index 339fa20..9b6e6b7 100644 --- a/gas/testsuite/gas/riscv/b-ext-64.d +++ b/gas/testsuite/gas/riscv/b-ext-64.d @@ -62,3 +62,11 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s index 8ceb2b4..57e501e 100644 --- a/gas/testsuite/gas/riscv/b-ext-64.s +++ b/gas/testsuite/gas/riscv/b-ext-64.s @@ -53,3 +53,12 @@ target: bset a0, a1, a2 binv a0, a1, a2 bext a0, a1, a2 + #aliases + bclr a0, a1, 31 + bset a0, a1, 31 + binv a0, a1, 31 + bext a0, a1, 31 + bclr a0, a1, 63 + bset a0, a1, 63 + binv a0, a1, 63 + bext a0, a1, 63 diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d index 748c218..c1c5f91 100644 --- a/gas/testsuite/gas/riscv/b-ext.d +++ b/gas/testsuite/gas/riscv/b-ext.d @@ -45,3 +45,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2 [ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s index a13a797..9de3fc3 100644 --- a/gas/testsuite/gas/riscv/b-ext.s +++ b/gas/testsuite/gas/riscv/b-ext.s @@ -36,3 +36,8 @@ target: bset a0, a1, a2 binv a0, a1, a2 bext a0, a1, a2 + #aliases + bclr a0, a1, 31 + bset a0, a1, 31 + binv a0, a1, 31 + bext a0, a1, 31 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 1a4c9f0..b756bae 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -839,9 +839,13 @@ const struct riscv_opcode riscv_opcodes[] = {"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 }, {"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 }, {"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 }, +{"bclr", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS }, {"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 }, +{"bset", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS }, {"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 }, +{"binv", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS }, {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 }, +{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS }, /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} |