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authorRichard Henderson <rth@redhat.com>2000-02-24 00:43:29 +0000
committerRichard Henderson <rth@redhat.com>2000-02-24 00:43:29 +0000
commit7e0527420a4b51c074a523285d0fc88ca9eb539e (patch)
tree7436517834b19956f6d72c80bcde2c5cded3dcfd
parent99eeeb0ff7898f8987188e510b2612de1fcfa454 (diff)
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* config/tc-i386.c (md_assemble): When swapping operands for
intel_syntax, assume everything that's not Imm or Disp is a register.
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-i386.c30
2 files changed, 21 insertions, 15 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4a9b1a3..6d7868a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2000-02-23 Richard Henderson <rth@cygnus.com>
+
+ * config/tc-i386.c (md_assemble): When swapping operands for
+ intel_syntax, assume everything that's not Imm or Disp is a
+ register.
+
2000-02-23 Linas Vepstas <linas@linas.org>
* config/tc-i370.c, config/tc-i370.h: New files.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 43886d1..d762d5f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1298,21 +1298,16 @@ md_assemble (line)
if (i.operands > 1)
{
temp_type = i.types[xchg2];
- if (temp_type & (Reg | FloatReg))
- temp_reg = i.regs[xchg2];
- else if (temp_type & Imm)
+ if (temp_type & Imm)
temp_imm = i.imms[xchg2];
else if (temp_type & Disp)
temp_disp = i.disps[xchg2];
+ else
+ temp_reg = i.regs[xchg2];
i.types[xchg2] = i.types[xchg1];
- if (i.types[xchg1] & (Reg | FloatReg))
- {
- i.regs[xchg2] = i.regs[xchg1];
- i.regs[xchg1] = NULL;
- }
- else if (i.types[xchg2] & Imm)
+ if (i.types[xchg2] & Imm)
{
i.imms[xchg2] = i.imms[xchg1];
i.imms[xchg1] = NULL;
@@ -1322,14 +1317,13 @@ md_assemble (line)
i.disps[xchg2] = i.disps[xchg1];
i.disps[xchg1] = NULL;
}
-
- if (temp_type & (Reg | FloatReg))
+ else
{
- i.regs[xchg1] = temp_reg;
- if (! (i.types[xchg1] & (Reg | FloatReg)))
- i.regs[xchg2] = NULL;
+ i.regs[xchg2] = i.regs[xchg1];
+ i.regs[xchg1] = NULL;
}
- else if (temp_type & Imm)
+
+ if (temp_type & Imm)
{
i.imms[xchg1] = temp_imm;
if (! (i.types[xchg1] & Imm))
@@ -1341,6 +1335,12 @@ md_assemble (line)
if (! (i.types[xchg1] & Disp))
i.disps[xchg2] = NULL;
}
+ else
+ {
+ i.regs[xchg1] = temp_reg;
+ if (i.types[xchg1] & (Imm | Disp))
+ i.regs[xchg2] = NULL;
+ }
i.types[xchg1] = temp_type;
}