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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-09 11:38:59 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-09 11:38:59 +0100 |
| commit | 7697afb662b2ffd67d044209d6d807a8e21dfed9 (patch) | |
| tree | eaeaab01a9809997f43d6edca9dd7e4c3fc3cc21 | |
| parent | d835a58baae720abe909795cb68763040d1750a8 (diff) | |
| download | gdb-7697afb662b2ffd67d044209d6d807a8e21dfed9.zip gdb-7697afb662b2ffd67d044209d6d807a8e21dfed9.tar.gz gdb-7697afb662b2ffd67d044209d6d807a8e21dfed9.tar.bz2 | |
x86: consistently convert to byte registers for TEST w/ imm optimization
Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 21 |
2 files changed, 15 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 116617a..c3045c1 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2020-01-09 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (optimize_encoding): Generalize register + transformation for TEST optimization. + +2020-01-09 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/x86-64-sysenter-amd.s, testsuite/gas/i386/x86-64-sysenter-amd.d, testsuite/gas/i386/x86-64-sysenter-amd.l, diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index d0b8f26..efa4365 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4009,17 +4009,16 @@ optimize_encoding (void) i.types[1].bitfield.byte = 1; /* Ignore the suffix. */ i.suffix = 0; - if (base_regnum >= 4) - { - /* Handle SP, BP, SI, DI and R12-R15 registers. */ - if (i.types[1].bitfield.word) - j = 16; - else if (i.types[1].bitfield.dword) - j = 32; - else - j = 48; - i.op[1].regs -= j; - } + /* Convert to byte registers. */ + if (i.types[1].bitfield.word) + j = 16; + else if (i.types[1].bitfield.dword) + j = 32; + else + j = 48; + if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) + j += 8; + i.op[1].regs -= j; } } else if (flag_code == CODE_64BIT |