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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-28 19:07:52 +0900 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-28 14:17:34 +0000 |
| commit | 6b84c098e533f87d7973fd6fe8a39ee97255ebdb (patch) | |
| tree | ba56a5585518038f476d3a7e6a4b216e67f0be1e | |
| parent | 83029f7ff5d571dff0190e8d92c26e032c7acd76 (diff) | |
| download | gdb-6b84c098e533f87d7973fd6fe8a39ee97255ebdb.zip gdb-6b84c098e533f87d7973fd6fe8a39ee97255ebdb.tar.gz gdb-6b84c098e533f87d7973fd6fe8a39ee97255ebdb.tar.bz2 | |
RISC-V: Improve "bits undefined" diagnostics
This commit improves internal error message
"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"
to display actual unused bits (excluding non-instruction bits).
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Exclude non-
instruction bits from displaying internal diagnostics.
Change error message slightly.
| -rw-r--r-- | gas/config/tc-riscv.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 7055879..3237369 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1398,8 +1398,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) if (used_bits != required_bits) { as_bad (_("internal: bad RISC-V opcode " - "(bits 0x%lx undefined): %s %s"), - ~(unsigned long)(used_bits & required_bits), + "(bits %#llx undefined or invalid): %s %s"), + (unsigned long long)(used_bits ^ required_bits), opc->name, opc->args); return false; } |