diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
| commit | 6327658ee73502ffb55dfb6b28a20d1dde15a4dc (patch) | |
| tree | 13b1c36b6ded6afcde85d45b69971548bb22c37d | |
| parent | a5e9beead8580777ea4886b06c493a6f79570f93 (diff) | |
| download | gdb-6327658ee73502ffb55dfb6b28a20d1dde15a4dc.zip gdb-6327658ee73502ffb55dfb6b28a20d1dde15a4dc.tar.gz gdb-6327658ee73502ffb55dfb6b28a20d1dde15a4dc.tar.bz2 | |
aarch64: Add support for +mops
This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.
I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]
include/
* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
(AARCH64_OPND_MOPS_WB_Rn): Likewise.
opcodes/
* aarch64-asm.h (ins_x0_to_x30): New inserter.
* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
* aarch64-dis.h (ext_x0_to_x30): New extractor.
* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
* aarch64-tbl.h (aarch64_feature_mops): New feature set.
(aarch64_feature_mops_memtag): Likewise.
(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
(MOPS_SET_INSN): New macros.
(aarch64_opcode_table): Add MOPS instructions.
(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
* aarch64-opc.c (aarch64_print_operand): Handle
AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
AARCH64_OPND_MOPS_WB_Rn.
(verify_three_different_regs): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* doc/c-aarch64.texi: Document +mops.
* config/tc-aarch64.c (parse_x0_to_x30): New function.
(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
(aarch64_features): Add "mops".
* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
* testsuite/gas/aarch64/mops_invalid.s,
* testsuite/gas/aarch64/mops_invalid.d,
* testsuite/gas/aarch64/mops_invalid.l: Likewise.
| -rw-r--r-- | gas/config/tc-aarch64.c | 33 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/mops.d | 1016 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/mops.s | 66 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/mops_invalid.d | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/mops_invalid.l | 226 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/mops_invalid.s | 248 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 7 | ||||
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 13 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.h | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 1386 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 11 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.h | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 41 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 107 |
17 files changed, 3133 insertions, 33 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2181fa1..4aadf5b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3918,6 +3918,22 @@ parse_sve_address (char **str, aarch64_opnd_info *operand, SHIFTED_MUL_VL); } +/* Parse a register X0-X30. The register must be 64-bit and register 31 + is unallocated. */ +static bool +parse_x0_to_x30 (char **str, aarch64_opnd_info *operand) +{ + const reg_entry *reg = parse_reg (str); + if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R_64)) + { + set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64))); + return false; + } + operand->reg.regno = reg->number; + operand->qualifier = AARCH64_OPND_QLF_X; + return true; +} + /* Parse an operand for a MOVZ, MOVN or MOVK instruction. Return TRUE on success; otherwise return FALSE. */ static bool @@ -7491,6 +7507,21 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; } + case AARCH64_OPND_MOPS_ADDR_Rd: + case AARCH64_OPND_MOPS_ADDR_Rs: + po_char_or_fail ('['); + if (!parse_x0_to_x30 (&str, info)) + goto failure; + po_char_or_fail (']'); + po_char_or_fail ('!'); + break; + + case AARCH64_OPND_MOPS_WB_Rn: + if (!parse_x0_to_x30 (&str, info)) + goto failure; + po_char_or_fail ('!'); + break; + default: as_fatal (_("unhandled operand code %d"), operands[i]); } @@ -9929,6 +9960,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_ARCH_NONE}, {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC, 0), AARCH64_ARCH_NONE}, + {"mops", AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0), + AARCH64_ARCH_NONE}, {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 3051b6f..7edccce 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -193,6 +193,8 @@ automatically cause those extensions to be disabled. @tab Enable Large System extensions. @item @code{memtag} @tab ARMv8.5-A @tab No @tab Enable ARMv8.5-A Memory Tagging Extensions. +@item @code{mops} @tab @tab Armv8.8-A or later + @tab Enable Armv8.8-A memcpy and memset acceleration instructions @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later @tab Enable Privileged Access Never support. @item @code{pauth} @tab ARMv8-A @tab No diff --git a/gas/testsuite/gas/aarch64/mops.d b/gas/testsuite/gas/aarch64/mops.d new file mode 100644 index 0000000..a49ef1a --- /dev/null +++ b/gas/testsuite/gas/aarch64/mops.d @@ -0,0 +1,1016 @@ +# objdump: -dr + +.* + + +Disassembly of section \.text: + +0+0 <\.text>: +[^:]*: 190107c0 cpyfp \[x0\]!, \[x1\]!, x30! +[^:]*: 194107c0 cpyfm \[x0\]!, \[x1\]!, x30! +[^:]*: 198107c0 cpyfe \[x0\]!, \[x1\]!, x30! +[^:]*: 191e041d cpyfp \[x29\]!, \[x30\]!, x0! +[^:]*: 195e041d cpyfm \[x29\]!, \[x30\]!, x0! +[^:]*: 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\[x30\]!, x0! +[^:]*: 1d9ea41d cpyertrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00a43e cpyprtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40a43e cpymrtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80a43e cpyertrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0ba668 cpyprtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4ba668 cpymrtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8ba668 cpyertrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0167c0 cpyprtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4167c0 cpymrtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8167c0 cpyertwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e641d cpyprtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e641d cpymrtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e641d cpyertwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00643e cpyprtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40643e cpymrtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80643e cpyertwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b6668 cpyprtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b6668 cpymrtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b6668 cpyertwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d01e7c0 cpyprtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d41e7c0 cpymrtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d81e7c0 cpyertn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1ee41d cpyprtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5ee41d cpymrtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9ee41d cpyertn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00e43e cpyprtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40e43e cpymrtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80e43e cpyertn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0be668 cpyprtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4be668 cpymrtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8be668 cpyertn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0117c0 cpypwt \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4117c0 cpymwt \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8117c0 cpyewt \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e141d cpypwt \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e141d cpymwt \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e141d cpyewt \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00143e cpypwt \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40143e cpymwt \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80143e cpyewt \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b1668 cpypwt \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b1668 cpymwt \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b1668 cpyewt \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0197c0 cpypwtrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4197c0 cpymwtrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8197c0 cpyewtrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e941d cpypwtrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e941d cpymwtrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e941d cpyewtrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00943e cpypwtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40943e cpymwtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80943e cpyewtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b9668 cpypwtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b9668 cpymwtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b9668 cpyewtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0157c0 cpypwtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4157c0 cpymwtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8157c0 cpyewtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e541d cpypwtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e541d cpymwtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e541d cpyewtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00543e cpypwtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40543e cpymwtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80543e cpyewtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b5668 cpypwtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b5668 cpymwtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b5668 cpyewtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d01d7c0 cpypwtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d41d7c0 cpymwtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d81d7c0 cpyewtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1ed41d cpypwtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5ed41d cpymwtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9ed41d cpyewtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00d43e cpypwtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40d43e cpymwtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80d43e cpyewtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0bd668 cpypwtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4bd668 cpymwtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8bd668 cpyewtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0137c0 cpypt \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4137c0 cpymt \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8137c0 cpyet \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e341d cpypt \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e341d cpymt \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e341d cpyet \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00343e cpypt \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40343e cpymt \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80343e cpyet \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b3668 cpypt \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b3668 cpymt \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b3668 cpyet \[x8\]!, \[x11\]!, x19! +[^:]*: 1d01b7c0 cpyptrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d41b7c0 cpymtrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d81b7c0 cpyetrn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1eb41d cpyptrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5eb41d cpymtrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9eb41d cpyetrn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00b43e cpyptrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40b43e cpymtrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80b43e cpyetrn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0bb668 cpyptrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4bb668 cpymtrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8bb668 cpyetrn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d0177c0 cpyptwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d4177c0 cpymtwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d8177c0 cpyetwn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1e741d cpyptwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5e741d cpymtwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9e741d cpyetwn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00743e cpyptwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40743e cpymtwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80743e cpyetwn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0b7668 cpyptwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4b7668 cpymtwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8b7668 cpyetwn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d01f7c0 cpyptn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d41f7c0 cpymtn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d81f7c0 cpyetn \[x0\]!, \[x1\]!, x30! +[^:]*: 1d1ef41d cpyptn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d5ef41d cpymtn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d9ef41d cpyetn \[x29\]!, \[x30\]!, x0! +[^:]*: 1d00f43e cpyptn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d40f43e cpymtn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d80f43e cpyetn \[x30\]!, \[x0\]!, x1! +[^:]*: 1d0bf668 cpyptn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d4bf668 cpymtn \[x8\]!, \[x11\]!, x19! +[^:]*: 1d8bf668 cpyetn \[x8\]!, \[x11\]!, x19! +[^:]*: 19de0420 setp \[x0\]!, x1!, x30 +[^:]*: 19de4420 setm \[x0\]!, x1!, x30 +[^:]*: 19de8420 sete \[x0\]!, x1!, x30 +[^:]*: 19c007dd setp \[x29\]!, x30!, x0 +[^:]*: 19c047dd setm \[x29\]!, x30!, x0 +[^:]*: 19c087dd sete \[x29\]!, x30!, x0 +[^:]*: 19df041e setp \[x30\]!, x0!, xzr +[^:]*: 19df441e setm \[x30\]!, x0!, xzr +[^:]*: 19df841e sete \[x30\]!, x0!, xzr +[^:]*: 19d70668 setp \[x8\]!, x19!, x23 +[^:]*: 19d74668 setm \[x8\]!, x19!, x23 +[^:]*: 19d78668 sete \[x8\]!, x19!, x23 +[^:]*: 19df0668 setp \[x8\]!, x19!, xzr +[^:]*: 19df4668 setm \[x8\]!, x19!, xzr +[^:]*: 19df8668 sete \[x8\]!, x19!, xzr +[^:]*: 19de1420 setpt \[x0\]!, x1!, x30 +[^:]*: 19de5420 setmt \[x0\]!, x1!, x30 +[^:]*: 19de9420 setet \[x0\]!, x1!, x30 +[^:]*: 19c017dd setpt \[x29\]!, x30!, x0 +[^:]*: 19c057dd setmt \[x29\]!, x30!, x0 +[^:]*: 19c097dd setet \[x29\]!, x30!, x0 +[^:]*: 19df141e setpt \[x30\]!, x0!, xzr +[^:]*: 19df541e setmt \[x30\]!, x0!, xzr +[^:]*: 19df941e setet \[x30\]!, x0!, xzr +[^:]*: 19d71668 setpt \[x8\]!, x19!, x23 +[^:]*: 19d75668 setmt \[x8\]!, x19!, x23 +[^:]*: 19d79668 setet \[x8\]!, x19!, x23 +[^:]*: 19df1668 setpt \[x8\]!, x19!, xzr +[^:]*: 19df5668 setmt \[x8\]!, x19!, xzr +[^:]*: 19df9668 setet \[x8\]!, x19!, xzr +[^:]*: 19de2420 setpn \[x0\]!, x1!, x30 +[^:]*: 19de6420 setmn \[x0\]!, x1!, x30 +[^:]*: 19dea420 seten \[x0\]!, x1!, x30 +[^:]*: 19c027dd setpn \[x29\]!, x30!, x0 +[^:]*: 19c067dd setmn \[x29\]!, x30!, x0 +[^:]*: 19c0a7dd seten \[x29\]!, x30!, x0 +[^:]*: 19df241e setpn \[x30\]!, x0!, xzr +[^:]*: 19df641e setmn \[x30\]!, x0!, xzr +[^:]*: 19dfa41e seten \[x30\]!, x0!, xzr +[^:]*: 19d72668 setpn \[x8\]!, x19!, x23 +[^:]*: 19d76668 setmn \[x8\]!, x19!, x23 +[^:]*: 19d7a668 seten \[x8\]!, x19!, x23 +[^:]*: 19df2668 setpn \[x8\]!, x19!, xzr +[^:]*: 19df6668 setmn \[x8\]!, x19!, xzr +[^:]*: 19dfa668 seten \[x8\]!, x19!, xzr +[^:]*: 19de3420 setptn \[x0\]!, x1!, x30 +[^:]*: 19de7420 setmtn \[x0\]!, x1!, x30 +[^:]*: 19deb420 setetn \[x0\]!, x1!, x30 +[^:]*: 19c037dd setptn \[x29\]!, x30!, x0 +[^:]*: 19c077dd setmtn \[x29\]!, x30!, x0 +[^:]*: 19c0b7dd setetn \[x29\]!, x30!, x0 +[^:]*: 19df341e setptn \[x30\]!, x0!, xzr +[^:]*: 19df741e setmtn \[x30\]!, x0!, xzr +[^:]*: 19dfb41e setetn \[x30\]!, x0!, xzr +[^:]*: 19d73668 setptn \[x8\]!, x19!, x23 +[^:]*: 19d77668 setmtn \[x8\]!, x19!, x23 +[^:]*: 19d7b668 setetn \[x8\]!, x19!, x23 +[^:]*: 19df3668 setptn \[x8\]!, x19!, xzr +[^:]*: 19df7668 setmtn \[x8\]!, x19!, xzr +[^:]*: 19dfb668 setetn \[x8\]!, x19!, xzr +[^:]*: 1dde0420 setgp \[x0\]!, x1!, x30 +[^:]*: 1dde4420 setgm \[x0\]!, x1!, x30 +[^:]*: 1dde8420 setge \[x0\]!, x1!, x30 +[^:]*: 1dc007dd setgp \[x29\]!, x30!, x0 +[^:]*: 1dc047dd setgm \[x29\]!, x30!, x0 +[^:]*: 1dc087dd setge \[x29\]!, x30!, x0 +[^:]*: 1ddf041e setgp \[x30\]!, x0!, xzr +[^:]*: 1ddf441e setgm \[x30\]!, x0!, xzr +[^:]*: 1ddf841e setge \[x30\]!, x0!, xzr +[^:]*: 1dd70668 setgp \[x8\]!, x19!, x23 +[^:]*: 1dd74668 setgm \[x8\]!, x19!, x23 +[^:]*: 1dd78668 setge \[x8\]!, x19!, x23 +[^:]*: 1ddf0668 setgp \[x8\]!, x19!, xzr +[^:]*: 1ddf4668 setgm \[x8\]!, x19!, xzr +[^:]*: 1ddf8668 setge \[x8\]!, x19!, xzr +[^:]*: 1dde1420 setgpt \[x0\]!, x1!, x30 +[^:]*: 1dde5420 setgmt \[x0\]!, x1!, x30 +[^:]*: 1dde9420 setget \[x0\]!, x1!, x30 +[^:]*: 1dc017dd setgpt \[x29\]!, x30!, x0 +[^:]*: 1dc057dd setgmt \[x29\]!, x30!, x0 +[^:]*: 1dc097dd setget \[x29\]!, x30!, x0 +[^:]*: 1ddf141e setgpt \[x30\]!, x0!, xzr +[^:]*: 1ddf541e setgmt \[x30\]!, x0!, xzr +[^:]*: 1ddf941e setget \[x30\]!, x0!, xzr +[^:]*: 1dd71668 setgpt \[x8\]!, x19!, x23 +[^:]*: 1dd75668 setgmt \[x8\]!, x19!, x23 +[^:]*: 1dd79668 setget \[x8\]!, x19!, x23 +[^:]*: 1ddf1668 setgpt \[x8\]!, x19!, xzr +[^:]*: 1ddf5668 setgmt \[x8\]!, x19!, xzr +[^:]*: 1ddf9668 setget \[x8\]!, x19!, xzr +[^:]*: 1dde2420 setgpn \[x0\]!, x1!, x30 +[^:]*: 1dde6420 setgmn \[x0\]!, x1!, x30 +[^:]*: 1ddea420 setgen \[x0\]!, x1!, x30 +[^:]*: 1dc027dd setgpn \[x29\]!, x30!, x0 +[^:]*: 1dc067dd setgmn \[x29\]!, x30!, x0 +[^:]*: 1dc0a7dd setgen \[x29\]!, x30!, x0 +[^:]*: 1ddf241e setgpn \[x30\]!, x0!, xzr +[^:]*: 1ddf641e setgmn \[x30\]!, x0!, xzr +[^:]*: 1ddfa41e setgen \[x30\]!, x0!, xzr +[^:]*: 1dd72668 setgpn \[x8\]!, x19!, x23 +[^:]*: 1dd76668 setgmn \[x8\]!, x19!, x23 +[^:]*: 1dd7a668 setgen \[x8\]!, x19!, x23 +[^:]*: 1ddf2668 setgpn \[x8\]!, x19!, xzr +[^:]*: 1ddf6668 setgmn \[x8\]!, x19!, xzr +[^:]*: 1ddfa668 setgen \[x8\]!, x19!, xzr +[^:]*: 1dde3420 setgptn \[x0\]!, x1!, x30 +[^:]*: 1dde7420 setgmtn \[x0\]!, x1!, x30 +[^:]*: 1ddeb420 setgetn \[x0\]!, x1!, x30 +[^:]*: 1dc037dd setgptn \[x29\]!, x30!, x0 +[^:]*: 1dc077dd setgmtn \[x29\]!, x30!, x0 +[^:]*: 1dc0b7dd setgetn \[x29\]!, x30!, x0 +[^:]*: 1ddf341e setgptn \[x30\]!, x0!, xzr +[^:]*: 1ddf741e setgmtn \[x30\]!, x0!, xzr +[^:]*: 1ddfb41e setgetn \[x30\]!, x0!, xzr +[^:]*: 1dd73668 setgptn \[x8\]!, x19!, x23 +[^:]*: 1dd77668 setgmtn \[x8\]!, x19!, x23 +[^:]*: 1dd7b668 setgetn \[x8\]!, x19!, x23 +[^:]*: 1ddf3668 setgptn \[x8\]!, x19!, xzr +[^:]*: 1ddf7668 setgmtn \[x8\]!, x19!, xzr +[^:]*: 1ddfb668 setgetn \[x8\]!, x19!, xzr diff --git a/gas/testsuite/gas/aarch64/mops.s b/gas/testsuite/gas/aarch64/mops.s new file mode 100644 index 0000000..5cd9e3a --- /dev/null +++ b/gas/testsuite/gas/aarch64/mops.s @@ -0,0 +1,66 @@ + .arch armv8.8-a+memtag + +dest .req x8 +src .req x11 +len .req x19 +data .req x23 +zero .req xzr + + .macro pme_seq, op, suffix, r1, r2, r3 + \op\()p\()\suffix \r1, \r2, \r3 + \op\()m\()\suffix \r1, \r2, \r3 + \op\()e\()\suffix \r1, \r2, \r3 + .endm + + .macro cpy_op1_op2, op, suffix + pme_seq \op, \suffix, [x0]!, [x1]!, x30! + pme_seq \op, \suffix, [x29]!, [x30]!, x0! + pme_seq \op, \suffix, [x30]!, [x0]!, x1! + pme_seq \op, \suffix, [dest]!, [src]!, len! + .endm + + .macro cpy_op1, op, suffix + cpy_op1_op2 \op, \suffix + cpy_op1_op2 \op, \suffix\()rn + cpy_op1_op2 \op, \suffix\()wn + cpy_op1_op2 \op, \suffix\()n + .endm + + .macro cpy_all, op + cpy_op1 \op + cpy_op1 \op, rt + cpy_op1 \op, wt + cpy_op1 \op, t + .endm + + .macro set_op1_op2, op, suffix + pme_seq \op, \suffix, [x0]!, x1!, x30 + pme_seq \op, \suffix, [x29]!, x30!, x0 + pme_seq \op, \suffix, [x30]!, x0!, xzr + pme_seq \op, \suffix, [dest]!, len!, data + pme_seq \op, \suffix, [dest]!, len!, zero + .endm + + .macro set_all, op + set_op1_op2 \op + set_op1_op2 \op, t + set_op1_op2 \op, n + set_op1_op2 \op, tn + .endm + + cpy_all cpyf + cpy_all cpy + + set_all set + set_all setg + + .arch armv8.7-a+mops + + cpy_all cpyf + cpy_all cpy + + set_all set + + .arch armv8.7-a+mops+memtag + + set_all setg diff --git a/gas/testsuite/gas/aarch64/mops_invalid.d b/gas/testsuite/gas/aarch64/mops_invalid.d new file mode 100644 index 0000000..af66fff --- /dev/null +++ b/gas/testsuite/gas/aarch64/mops_invalid.d @@ -0,0 +1 @@ +#error_output: mops_invalid.l diff --git a/gas/testsuite/gas/aarch64/mops_invalid.l b/gas/testsuite/gas/aarch64/mops_invalid.l new file mode 100644 index 0000000..8f5e588 --- /dev/null +++ b/gas/testsuite/gas/aarch64/mops_invalid.l @@ -0,0 +1,226 @@ +[^:]+: Assembler messages: +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `cpyfp x0,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `cpyfp x0!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `cpyfp \[x0\],\[x1\]!,x2!' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `cpyfp \[x0,#0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `cpyfp \[x0,xzr\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,x0,x2!' +[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,x0!,x2!' +[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0\],x2!' +[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,#0\]!,x2!' +[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,xzr\]!,x2!' +[^:]+:[0-9]+: Error: operand 3 must be an integer register with writeback -- `cpyfp \[x0\]!,\[x1\]!,x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!' +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x0\]!,\[x0\]!,x1!' +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x10\]!,\[x1\]!,x10!' +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x1\]!,\[x30\]!,x30!' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp x0,x1!,x2' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp x0!,x1!,x2' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0\],x1!,x2' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,#0\]!,x1!,x2' +[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,xzr\]!,x1!,x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[x31\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[sp\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[zr\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w30\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w0\]!,x1!,x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wsp\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wzr\]!,x0!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[foo\]!,x1!,x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,x31!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,sp!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,zr!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,w30!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,w0!,x2' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wsp!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wzr!,x1' +[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,foo!,x2' +[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,sp' +[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,wsp' +[^:]+:[0-9]+: Error: operand mismatch -- `setp \[x30\]!,x0!,wzr' +[^:]+:[0-9]+: Info: did you mean this\? +[^:]+:[0-9]+: Info: setp \[x30\]!, x0!, xzr +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `setp \[x0\]!,x0!,x1' +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `setp \[x10\]!,x1!,x10' +[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `setp \[x1\]!,x30!,x30' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfp \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfm \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfe \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfprn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfern \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfewn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfen \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfprt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmrt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfert \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfprtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmrtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfertrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfprtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmrtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfertwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfprtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmrtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfertn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpwt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmwt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfewt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpwtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmwtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfewtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpwtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmwtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfewtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpwtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmwtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfewtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfpt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfet \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfptrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfetrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfptwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfetwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfptn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfmtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyfetn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyp \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpym \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpye \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyprn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyern \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyewn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyen \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyprt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymrt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyert \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyprtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymrtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyertrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyprtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymrtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyertwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyprtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymrtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyertn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypwt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymwt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyewt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypwtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymwtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyewtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypwtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymwtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyewtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypwtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymwtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyewtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpypt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymt \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyet \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyptrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymtrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyetrn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyptwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymtwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyetwn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyptn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpymtn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `cpyetn \[x0\]!,\[x1\]!,x2!' +[^:]+:[0-9]+: Error: selected processor does not support `setp \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setm \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `sete \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setpt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setmt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setet \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setpn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setmn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `seten \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setptn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setmtn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setetn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgp \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgm \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setge \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setget \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgen \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgptn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmtn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgetn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgp \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgm \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setge \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setget \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgen \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgptn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmtn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgetn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgp \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgm \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setge \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmt \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setget \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgpn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgen \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgptn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgmtn \[x0\]!,x1!,x2' +[^:]+:[0-9]+: Error: selected processor does not support `setgetn \[x0\]!,x1!,x2' diff --git a/gas/testsuite/gas/aarch64/mops_invalid.s b/gas/testsuite/gas/aarch64/mops_invalid.s new file mode 100644 index 0000000..5281d37 --- /dev/null +++ b/gas/testsuite/gas/aarch64/mops_invalid.s @@ -0,0 +1,248 @@ + .arch armv8.8-a + + cpyfp x0, [x1]!, x2! + cpyfp x0!, [x1]!, x2! + cpyfp [x0], [x1]!, x2! + cpyfp [x0, #0]!, [x1]!, x2! + cpyfp [x0, xzr]!, [x1]!, x2! + + cpyfp [x1]!, x0, x2! + cpyfp [x1]!, x0!, x2! + cpyfp [x1]!, [x0], x2! + cpyfp [x1]!, [x0, #0]!, x2! + cpyfp [x1]!, [x0, xzr]!, x2! + + cpyfp [x0]!, [x1]!, x2 + cpyfp [x0]!, [x1]!, !x2 + cpyfp [x0]!, [x1]!, [x2] + cpyfp [x0]!, [x1]!, [x2]! + + cpyfp [x31]!, [x0]!, x1! + cpyfp [sp]!, [x0]!, x1! + cpyfp [zr]!, [x0]!, x1! + cpyfp [w30]!, [x0]!, x1! + cpyfp [w0]!, [x1]!, x2! + cpyfp [wsp]!, [x0]!, x1! + cpyfp [wzr]!, [x0]!, x1! + cpyfp [b0]!, [x1]!, x2! + cpyfp [h0]!, [x1]!, x2! + cpyfp [s0]!, [x1]!, x2! + cpyfp [d0]!, [x1]!, x2! + cpyfp [q0]!, [x1]!, x2! + cpyfp [v0]!, [x1]!, x2! + cpyfp [v0.2d]!, [x1]!, x2! + cpyfp [z0]!, [x1]!, x2! + cpyfp [z0.d]!, [x1]!, x2! + cpyfp [p0]!, [x1]!, x2! + cpyfp [p0.d]!, [x1]!, x2! + cpyfp [foo]!, [x1]!, x2! + + cpyfp [x0]!, [x31]!, x1! + cpyfp [x0]!, [sp]!, x1! + cpyfp [x0]!, [zr]!, x1! + cpyfp [x0]!, [w30]!, x1! + cpyfp [x1]!, [w0]!, x2! + cpyfp [x0]!, [wsp]!, x1! + cpyfp [x0]!, [wzr]!, x1! + cpyfp [x1]!, [foo]!, x2! + + cpyfp [x0]!, [x1]!, x31! + cpyfp [x0]!, [x1]!, sp! + cpyfp [x0]!, [x1]!, zr! + cpyfp [x0]!, [x1]!, w30! + cpyfp [x1]!, [x2]!, w0! + cpyfp [x0]!, [x1]!, wsp! + cpyfp [x0]!, [x1]!, wzr! + cpyfp [x1]!, [x2]!, foo! + + cpyfp [x0]!, [x0]!, x1! + cpyfp [x10]!, [x1]!, x10! + cpyfp [x1]!, [x30]!, x30! + + setp x0, x1!, x2 + setp x0!, x1!, x2 + setp [x0], x1!, x2 + setp [x0, #0]!, x1!, x2 + setp [x0, xzr]!, x1!, x2 + + setp [x31]!, x0!, x1 + setp [sp]!, x0!, x1 + setp [zr]!, x0!, x1 + setp [w30]!, x0!, x1 + setp [w0]!, x1!, x2 + setp [wsp]!, x0!, x1 + setp [wzr]!, x0!, x1 + setp [foo]!, x1!, x2 + + setp [x0]!, x31!, x1 + setp [x0]!, sp!, x1 + setp [x0]!, zr!, x1 + setp [x0]!, w30!, x1 + setp [x1]!, w0!, x2 + setp [x0]!, wsp!, x1 + setp [x0]!, wzr!, x1 + setp [x1]!, foo!, x2 + + setp [x30]!, x0!, sp + setp [x30]!, x0!, wsp + setp [x30]!, x0!, wzr + + setp [x0]!, x0!, x1 + setp [x10]!, x1!, x10 + setp [x1]!, x30!, x30 + + .arch armv8.7-a + + cpyfp [x0]!, [x1]!, x2! + cpyfm [x0]!, [x1]!, x2! + cpyfe [x0]!, [x1]!, x2! + cpyfprn [x0]!, [x1]!, x2! + cpyfmrn [x0]!, [x1]!, x2! + cpyfern [x0]!, [x1]!, x2! + cpyfpwn [x0]!, [x1]!, x2! + cpyfmwn [x0]!, [x1]!, x2! + cpyfewn [x0]!, [x1]!, x2! + cpyfpn [x0]!, [x1]!, x2! + cpyfmn [x0]!, [x1]!, x2! + cpyfen [x0]!, [x1]!, x2! + cpyfprt [x0]!, [x1]!, x2! + cpyfmrt [x0]!, [x1]!, x2! + cpyfert [x0]!, [x1]!, x2! + cpyfprtrn [x0]!, [x1]!, x2! + cpyfmrtrn [x0]!, [x1]!, x2! + cpyfertrn [x0]!, [x1]!, x2! + cpyfprtwn [x0]!, [x1]!, x2! + cpyfmrtwn [x0]!, [x1]!, x2! + cpyfertwn [x0]!, [x1]!, x2! + cpyfprtn [x0]!, [x1]!, x2! + cpyfmrtn [x0]!, [x1]!, x2! + cpyfertn [x0]!, [x1]!, x2! + cpyfpwt [x0]!, [x1]!, x2! + cpyfmwt [x0]!, [x1]!, x2! + cpyfewt [x0]!, [x1]!, x2! + cpyfpwtrn [x0]!, [x1]!, x2! + cpyfmwtrn [x0]!, [x1]!, x2! + cpyfewtrn [x0]!, [x1]!, x2! + cpyfpwtwn [x0]!, [x1]!, x2! + cpyfmwtwn [x0]!, [x1]!, x2! + cpyfewtwn [x0]!, [x1]!, x2! + cpyfpwtn [x0]!, [x1]!, x2! + cpyfmwtn [x0]!, [x1]!, x2! + cpyfewtn [x0]!, [x1]!, x2! + cpyfpt [x0]!, [x1]!, x2! + cpyfmt [x0]!, [x1]!, x2! + cpyfet [x0]!, [x1]!, x2! + cpyfptrn [x0]!, [x1]!, x2! + cpyfmtrn [x0]!, [x1]!, x2! + cpyfetrn [x0]!, [x1]!, x2! + cpyfptwn [x0]!, [x1]!, x2! + cpyfmtwn [x0]!, [x1]!, x2! + cpyfetwn [x0]!, [x1]!, x2! + cpyfptn [x0]!, [x1]!, x2! + cpyfmtn [x0]!, [x1]!, x2! + cpyfetn [x0]!, [x1]!, x2! + + cpyp [x0]!, [x1]!, x2! + cpym [x0]!, [x1]!, x2! + cpye [x0]!, [x1]!, x2! + cpyprn [x0]!, [x1]!, x2! + cpymrn [x0]!, [x1]!, x2! + cpyern [x0]!, [x1]!, x2! + cpypwn [x0]!, [x1]!, x2! + cpymwn [x0]!, [x1]!, x2! + cpyewn [x0]!, [x1]!, x2! + cpypn [x0]!, [x1]!, x2! + cpymn [x0]!, [x1]!, x2! + cpyen [x0]!, [x1]!, x2! + cpyprt [x0]!, [x1]!, x2! + cpymrt [x0]!, [x1]!, x2! + cpyert [x0]!, [x1]!, x2! + cpyprtrn [x0]!, [x1]!, x2! + cpymrtrn [x0]!, [x1]!, x2! + cpyertrn [x0]!, [x1]!, x2! + cpyprtwn [x0]!, [x1]!, x2! + cpymrtwn [x0]!, [x1]!, x2! + cpyertwn [x0]!, [x1]!, x2! + cpyprtn [x0]!, [x1]!, x2! + cpymrtn [x0]!, [x1]!, x2! + cpyertn [x0]!, [x1]!, x2! + cpypwt [x0]!, [x1]!, x2! + cpymwt [x0]!, [x1]!, x2! + cpyewt [x0]!, [x1]!, x2! + cpypwtrn [x0]!, [x1]!, x2! + cpymwtrn [x0]!, [x1]!, x2! + cpyewtrn [x0]!, [x1]!, x2! + cpypwtwn [x0]!, [x1]!, x2! + cpymwtwn [x0]!, [x1]!, x2! + cpyewtwn [x0]!, [x1]!, x2! + cpypwtn [x0]!, [x1]!, x2! + cpymwtn [x0]!, [x1]!, x2! + cpyewtn [x0]!, [x1]!, x2! + cpypt [x0]!, [x1]!, x2! + cpymt [x0]!, [x1]!, x2! + cpyet [x0]!, [x1]!, x2! + cpyptrn [x0]!, [x1]!, x2! + cpymtrn [x0]!, [x1]!, x2! + cpyetrn [x0]!, [x1]!, x2! + cpyptwn [x0]!, [x1]!, x2! + cpymtwn [x0]!, [x1]!, x2! + cpyetwn [x0]!, [x1]!, x2! + cpyptn [x0]!, [x1]!, x2! + cpymtn [x0]!, [x1]!, x2! + cpyetn [x0]!, [x1]!, x2! + + setp [x0]!, x1!, x2 + setm [x0]!, x1!, x2 + sete [x0]!, x1!, x2 + setpt [x0]!, x1!, x2 + setmt [x0]!, x1!, x2 + setet [x0]!, x1!, x2 + setpn [x0]!, x1!, x2 + setmn [x0]!, x1!, x2 + seten [x0]!, x1!, x2 + setptn [x0]!, x1!, x2 + setmtn [x0]!, x1!, x2 + setetn [x0]!, x1!, x2 + + setgp [x0]!, x1!, x2 + setgm [x0]!, x1!, x2 + setge [x0]!, x1!, x2 + setgpt [x0]!, x1!, x2 + setgmt [x0]!, x1!, x2 + setget [x0]!, x1!, x2 + setgpn [x0]!, x1!, x2 + setgmn [x0]!, x1!, x2 + setgen [x0]!, x1!, x2 + setgptn [x0]!, x1!, x2 + setgmtn [x0]!, x1!, x2 + setgetn [x0]!, x1!, x2 + + .arch armv8.7-a+mops + + setgp [x0]!, x1!, x2 + setgm [x0]!, x1!, x2 + setge [x0]!, x1!, x2 + setgpt [x0]!, x1!, x2 + setgmt [x0]!, x1!, x2 + setget [x0]!, x1!, x2 + setgpn [x0]!, x1!, x2 + setgmn [x0]!, x1!, x2 + setgen [x0]!, x1!, x2 + setgptn [x0]!, x1!, x2 + setgmtn [x0]!, x1!, x2 + setgetn [x0]!, x1!, x2 + + .arch armv8.7-a+memtag + + setgp [x0]!, x1!, x2 + setgm [x0]!, x1!, x2 + setge [x0]!, x1!, x2 + setgpt [x0]!, x1!, x2 + setgmt [x0]!, x1!, x2 + setget [x0]!, x1!, x2 + setgpn [x0]!, x1!, x2 + setgmn [x0]!, x1!, x2 + setgen [x0]!, x1!, x2 + setgptn [x0]!, x1!, x2 + setgmtn [x0]!, x1!, x2 + setgetn [x0]!, x1!, x2 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 493b797..183d281 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -87,6 +87,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */ #define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */ #define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */ +#define AARCH64_FEATURE_MOPS (1ULL << 50) /* Standardization of memory operations. */ #define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */ #define AARCH64_FEATURE_F32MM (1ULL << 53) #define AARCH64_FEATURE_F64MM (1ULL << 54) @@ -143,7 +144,8 @@ typedef uint32_t aarch64_insn; AARCH64_FEATURE_V8_7 \ | AARCH64_FEATURE_LS64) #define AARCH64_ARCH_V8_8 AARCH64_FEATURE (AARCH64_ARCH_V8_7, \ - AARCH64_FEATURE_V8_8) + AARCH64_FEATURE_V8_8 \ + | AARCH64_FEATURE_MOPS) #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ AARCH64_FEATURE_V8_R) \ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) @@ -461,6 +463,9 @@ enum aarch64_opnd AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ + AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ + AARCH64_OPND_MOPS_WB_Rn /* Rn!, in bits [5, 9]. */ }; /* Qualifier constrains an operand. It either specifies a variant of an diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index bbe4b68..57c9e30 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -893,6 +893,10 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 220: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 223: + case 224: + case 225: + return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 9b66fd3..f8328eb 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1519,6 +1519,19 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, return true; } +/* Insert X0-X30. Register 31 is unallocated. */ +bool +aarch64_ins_x0_to_x30 (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + assert (info->reg.regno <= 30); + insert_field (self->fields[0], code, info->reg.regno, 0); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index 47f775d..ac97b9e 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -106,6 +106,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_sm_za); AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); +AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30); #undef AARCH64_DECL_OPD_INSERTER diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index f9999ad..70cbf90 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -2947,11 +2947,187 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100100xxxxxxxxxxx1xxxxxxxxxx - stg. */ - return 885; + if (((word >> 21) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0000x1xxxxxxxxxx + cpyfp. */ + return 2511; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1000x1xxxxxxxxxx + cpyfprn. */ + return 2517; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0100x1xxxxxxxxxx + cpyfpwn. */ + return 2514; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1100x1xxxxxxxxxx + cpyfpn. */ + return 2520; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0010x1xxxxxxxxxx + cpyfprt. */ + return 2535; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1010x1xxxxxxxxxx + cpyfprtrn. */ + return 2541; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0110x1xxxxxxxxxx + cpyfprtwn. */ + return 2538; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1110x1xxxxxxxxxx + cpyfprtn. */ + return 2544; + } + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0001x1xxxxxxxxxx + cpyfpwt. */ + return 2523; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1001x1xxxxxxxxxx + cpyfpwtrn. */ + return 2529; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0101x1xxxxxxxxxx + cpyfpwtwn. */ + return 2526; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1101x1xxxxxxxxxx + cpyfpwtn. */ + return 2532; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0011x1xxxxxxxxxx + cpyfpt. */ + return 2547; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1011x1xxxxxxxxxx + cpyfptrn. */ + return 2553; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx0111x1xxxxxxxxxx + cpyfptwn. */ + return 2550; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001000xxxxx1111x1xxxxxxxxxx + cpyfptn. */ + return 2556; + } + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001001xxxxxxxxxx1xxxxxxxxxx + stg. */ + return 885; + } } } else @@ -3054,11 +3230,187 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100101xxxxxxxxxxx1xxxxxxxxxx - stzg. */ - return 886; + if (((word >> 21) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0000x1xxxxxxxxxx + cpyfm. */ + return 2512; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1000x1xxxxxxxxxx + cpyfmrn. */ + return 2518; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0100x1xxxxxxxxxx + cpyfmwn. */ + return 2515; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1100x1xxxxxxxxxx + cpyfmn. */ + return 2521; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0010x1xxxxxxxxxx + cpyfmrt. */ + return 2536; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1010x1xxxxxxxxxx + cpyfmrtrn. */ + return 2542; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0110x1xxxxxxxxxx + cpyfmrtwn. */ + return 2539; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1110x1xxxxxxxxxx + cpyfmrtn. */ + return 2545; + } + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0001x1xxxxxxxxxx + cpyfmwt. */ + return 2524; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1001x1xxxxxxxxxx + cpyfmwtrn. */ + return 2530; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0101x1xxxxxxxxxx + cpyfmwtwn. */ + return 2527; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1101x1xxxxxxxxxx + cpyfmwtn. */ + return 2533; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0011x1xxxxxxxxxx + cpyfmt. */ + return 2548; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1011x1xxxxxxxxxx + cpyfmtrn. */ + return 2554; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx0111x1xxxxxxxxxx + cpyfmtwn. */ + return 2551; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001010xxxxx1111x1xxxxxxxxxx + cpyfmtn. */ + return 2557; + } + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001011xxxxxxxxxx1xxxxxxxxxx + stzg. */ + return 886; + } } } else @@ -3195,21 +3547,329 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 21) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100110xxxxxxxxxxx1xxxxxxxxxx - st2g. */ - return 887; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0000x1xxxxxxxxxx + cpyfe. */ + return 2513; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0000x1xxxxxxxxxx + setp. */ + return 2607; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx1000x1xxxxxxxxxx + cpyfern. */ + return 2519; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx1000x1xxxxxxxxxx + sete. */ + return 2609; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0100x1xxxxxxxxxx + cpyfewn. */ + return 2516; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0100x1xxxxxxxxxx + setm. */ + return 2608; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0110011x0xxxxx1100x1xxxxxxxxxx + cpyfen. */ + return 2522; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0010x1xxxxxxxxxx + cpyfert. */ + return 2537; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0010x1xxxxxxxxxx + setpn. */ + return 2613; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx1010x1xxxxxxxxxx + cpyfertrn. */ + return 2543; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx1010x1xxxxxxxxxx + seten. */ + return 2615; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0110x1xxxxxxxxxx + cpyfertwn. */ + return 2540; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0110x1xxxxxxxxxx + setmn. */ + return 2614; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0110011x0xxxxx1110x1xxxxxxxxxx + cpyfertn. */ + return 2546; + } + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0001x1xxxxxxxxxx + cpyfewt. */ + return 2525; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0001x1xxxxxxxxxx + setpt. */ + return 2610; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx1001x1xxxxxxxxxx + cpyfewtrn. */ + return 2531; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx1001x1xxxxxxxxxx + setet. */ + return 2612; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0101x1xxxxxxxxxx + cpyfewtwn. */ + return 2528; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0101x1xxxxxxxxxx + setmt. */ + return 2611; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0110011x0xxxxx1101x1xxxxxxxxxx + cpyfewtn. */ + return 2534; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0011x1xxxxxxxxxx + cpyfet. */ + return 2549; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0011x1xxxxxxxxxx + setptn. */ + return 2616; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx1011x1xxxxxxxxxx + cpyfetrn. */ + return 2555; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx1011x1xxxxxxxxxx + setetn. */ + return 2618; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001100xxxxx0111x1xxxxxxxxxx + cpyfetwn. */ + return 2552; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001110xxxxx0111x1xxxxxxxxxx + setmtn. */ + return 2617; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx0110011x0xxxxx1111x1xxxxxxxxxx + cpyfetn. */ + return 2558; + } + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100111xxxxxxxxxxx1xxxxxxxxxx - stz2g. */ - return 888; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001101xxxxxxxxxx1xxxxxxxxxx + st2g. */ + return 887; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001111xxxxxxxxxx1xxxxxxxxxx + stz2g. */ + return 888; + } } } } @@ -16812,19 +17472,679 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx11101x0xxxxxxxxxxxxxxxxxxxxxx - str. */ - return 892; + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0000xxxxxxxxxxxx + cpyp. */ + return 2559; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0000xxxxxxxxxxxx + cpye. */ + return 2561; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1000xxxxxxxxxxxx + cpyprn. */ + return 2565; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1000xxxxxxxxxxxx + cpyern. */ + return 2567; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0100xxxxxxxxxxxx + cpypwn. */ + return 2562; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0100xxxxxxxxxxxx + cpyewn. */ + return 2564; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1100xxxxxxxxxxxx + cpypn. */ + return 2568; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1100xxxxxxxxxxxx + cpyen. */ + return 2570; + } + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0010xxxxxxxxxxxx + cpyprt. */ + return 2583; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0010xxxxxxxxxxxx + cpyert. */ + return 2585; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1010xxxxxxxxxxxx + cpyprtrn. */ + return 2589; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1010xxxxxxxxxxxx + cpyertrn. */ + return 2591; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0110xxxxxxxxxxxx + cpyprtwn. */ + return 2586; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0110xxxxxxxxxxxx + cpyertwn. */ + return 2588; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1110xxxxxxxxxxxx + cpyprtn. */ + return 2592; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1110xxxxxxxxxxxx + cpyertn. */ + return 2594; + } + } + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0001xxxxxxxxxxxx + cpypwt. */ + return 2571; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0001xxxxxxxxxxxx + cpyewt. */ + return 2573; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1001xxxxxxxxxxxx + cpypwtrn. */ + return 2577; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1001xxxxxxxxxxxx + cpyewtrn. */ + return 2579; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0101xxxxxxxxxxxx + cpypwtwn. */ + return 2574; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0101xxxxxxxxxxxx + cpyewtwn. */ + return 2576; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1101xxxxxxxxxxxx + cpypwtn. */ + return 2580; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1101xxxxxxxxxxxx + cpyewtn. */ + return 2582; + } + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0011xxxxxxxxxxxx + cpypt. */ + return 2595; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0011xxxxxxxxxxxx + cpyet. */ + return 2597; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1011xxxxxxxxxxxx + cpyptrn. */ + return 2601; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1011xxxxxxxxxxxx + cpyetrn. */ + return 2603; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx0111xxxxxxxxxxxx + cpyptwn. */ + return 2598; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx0111xxxxxxxxxxxx + cpyetwn. */ + return 2600; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110100xxxxxx1111xxxxxxxxxxxx + cpyptn. */ + return 2604; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110110xxxxxx1111xxxxxxxxxxxx + cpyetn. */ + return 2606; + } + } + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx111101x0xxxxxxxxxxxxxxxxxxxxxx + str. */ + return 892; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx11101x1xxxxxxxxxxxxxxxxxxxxxx - ldr. */ - return 893; + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0000xxxxxxxxxxxx + cpym. */ + return 2560; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0000xxxxxxxxxxxx + setgp. */ + return 2619; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx1000xxxxxxxxxxxx + cpymrn. */ + return 2566; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx1000xxxxxxxxxxxx + setge. */ + return 2621; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0100xxxxxxxxxxxx + cpymwn. */ + return 2563; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0100xxxxxxxxxxxx + setgm. */ + return 2620; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011101x1xxxxxx1100xxxxxxxxxxxx + cpymn. */ + return 2569; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0010xxxxxxxxxxxx + cpymrt. */ + return 2584; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0010xxxxxxxxxxxx + setgpn. */ + return 2625; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx1010xxxxxxxxxxxx + cpymrtrn. */ + return 2590; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx1010xxxxxxxxxxxx + setgen. */ + return 2627; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0110xxxxxxxxxxxx + cpymrtwn. */ + return 2587; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0110xxxxxxxxxxxx + setgmn. */ + return 2626; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011101x1xxxxxx1110xxxxxxxxxxxx + cpymrtn. */ + return 2593; + } + } + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0001xxxxxxxxxxxx + cpymwt. */ + return 2572; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0001xxxxxxxxxxxx + setgpt. */ + return 2622; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx1001xxxxxxxxxxxx + cpymwtrn. */ + return 2578; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx1001xxxxxxxxxxxx + setget. */ + return 2624; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0101xxxxxxxxxxxx + cpymwtwn. */ + return 2575; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0101xxxxxxxxxxxx + setgmt. */ + return 2623; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011101x1xxxxxx1101xxxxxxxxxxxx + cpymwtn. */ + return 2581; + } + } + } + else + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0011xxxxxxxxxxxx + cpymt. */ + return 2596; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0011xxxxxxxxxxxx + setgptn. */ + return 2628; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx1011xxxxxxxxxxxx + cpymtrn. */ + return 2602; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx1011xxxxxxxxxxxx + setgetn. */ + return 2630; + } + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110101xxxxxx0111xxxxxxxxxxxx + cpymtwn. */ + return 2599; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx01110111xxxxxx0111xxxxxxxxxxxx + setgmtn. */ + return 2629; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011101x1xxxxxx1111xxxxxxxxxxxx + cpymtn. */ + return 2605; + } + } + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx111101x1xxxxxxxxxxxxxxxxxxxxxx + ldr. */ + return 893; + } } } } @@ -24638,6 +25958,10 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 220: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 223: + case 224: + case 225: + return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 46d602d..8e6123d 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2053,6 +2053,17 @@ aarch64_ext_sve_shrimm (const aarch64_operand *self, info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value; return true; } + +/* Decode X0-X30. Register 31 is unallocated. */ +bool +aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + info->reg.regno = extract_field (self->fields[0], code, 0); + return info->reg.regno <= 30; +} /* Bitfields that are commonly used to encode certain operands' information may be partially used as part of the base opcode in some instructions. diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index df59d22..9174dd9 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -130,6 +130,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); +AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); #undef AARCH64_DECL_OPD_EXTRACTOR diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index c583bd0..e0aec42 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -247,6 +247,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a77070e..cfd4781 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3921,6 +3921,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", opnd->hint_option->name); break; + case AARCH64_OPND_MOPS_ADDR_Rd: + case AARCH64_OPND_MOPS_ADDR_Rs: + snprintf (buf, size, "[%s]!", + get_int_reg_name (opnd->reg.regno, AARCH64_OPND_QLF_X, 0)); + break; + + case AARCH64_OPND_MOPS_WB_Rn: + snprintf (buf, size, "%s!", + get_int_reg_name (opnd->reg.regno, AARCH64_OPND_QLF_X, 0)); + break; + default: snprintf (buf, size, "<invalid>"); break; @@ -5409,6 +5420,36 @@ verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn, return ERR_OK; } +/* Check an instruction that takes three register operands and that + requires the register numbers to be distinct from one another. */ + +static enum err_type +verify_three_different_regs (const struct aarch64_inst *inst, + const aarch64_insn insn ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + bool encoding ATTRIBUTE_UNUSED, + aarch64_operand_error *mismatch_detail + ATTRIBUTE_UNUSED, + aarch64_instr_sequence *insn_sequence + ATTRIBUTE_UNUSED) +{ + int rd, rs, rn; + + rd = inst->operands[0].reg.regno; + rs = inst->operands[1].reg.regno; + rn = inst->operands[2].reg.regno; + if (rd == rs || rd == rn || rs == rn) + { + mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR; + mismatch_detail->error + = _("the three register operands must be distinct from one another"); + mismatch_detail->index = -1; + return ERR_UND; + } + + return ERR_OK; +} + /* Add INST to the end of INSN_SEQUENCE. */ static void diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3c0e990..48d2fa8 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2493,6 +2493,10 @@ static const aarch64_feature_set aarch64_feature_ls64 = AARCH64_FEATURE (AARCH64_FEATURE_V8_6 | AARCH64_FEATURE_LS64, 0); static const aarch64_feature_set aarch64_feature_flagm = AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0); +static const aarch64_feature_set aarch64_feature_mops = + AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0); +static const aarch64_feature_set aarch64_feature_mops_memtag = + AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2544,6 +2548,8 @@ static const aarch64_feature_set aarch64_feature_flagm = #define ARMV8_7 &aarch64_feature_v8_7 #define LS64 &aarch64_feature_ls64 #define FLAGM &aarch64_feature_flagm +#define MOPS &aarch64_feature_mops +#define MOPS_MEMTAG &aarch64_feature_mops_memtag #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2669,6 +2675,52 @@ static const aarch64_feature_set aarch64_feature_flagm = { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL } +#define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ + { NAME, OPCODE, MASK, CLASS, 0, MOPS, OPS, QUALS, FLAGS, CONSTRAINTS, \ + 0, VERIFIER } +#define MOPS_MEMTAG_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \ + { NAME, OPCODE, MASK, CLASS, 0, MOPS_MEMTAG, OPS, QUALS, FLAGS, \ + CONSTRAINTS, 0, VERIFIER } + +#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ + MOPS_INSN (NAME, OPCODE, MASK, 0, \ + OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \ + FLAGS, CONSTRAINTS, VERIFIER (three_different_regs)) + +#define MOPS_CPY_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK) \ + MOPS_CPY_OP1_OP2_PME_INSN (NAME "p" SUFFIX, OPCODE, MASK, F_SCAN, 0), \ + MOPS_CPY_OP1_OP2_PME_INSN (NAME "m" SUFFIX, OPCODE | 0x400000, MASK, 0, 0), \ + MOPS_CPY_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x800000, MASK, 0, 0) + +#define MOPS_CPY_OP1_INSN(NAME, SUFFIX, OPCODE, MASK) \ + MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX, OPCODE, MASK), \ + MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "wn", OPCODE | 0x4000, MASK), \ + MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "rn", OPCODE | 0x8000, MASK), \ + MOPS_CPY_OP1_OP2_INSN (NAME, SUFFIX "n", OPCODE | 0xc000, MASK) + +#define MOPS_CPY_INSN(NAME, OPCODE, MASK) \ + MOPS_CPY_OP1_INSN (NAME, "", OPCODE, MASK), \ + MOPS_CPY_OP1_INSN (NAME, "wt", OPCODE | 0x1000, MASK), \ + MOPS_CPY_OP1_INSN (NAME, "rt", OPCODE | 0x2000, MASK), \ + MOPS_CPY_OP1_INSN (NAME, "t", OPCODE | 0x3000, MASK) + +#define MOPS_SET_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS, ISA) \ + ISA (NAME, OPCODE, MASK, 0, \ + OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \ + CONSTRAINTS, VERIFIER (three_different_regs)) + +#define MOPS_SET_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK, ISA) \ + MOPS_SET_OP1_OP2_PME_INSN (NAME "p" SUFFIX, OPCODE, MASK, 0, 0, ISA), \ + MOPS_SET_OP1_OP2_PME_INSN (NAME "m" SUFFIX, OPCODE | 0x4000, MASK, \ + 0, 0, ISA), \ + MOPS_SET_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x8000, MASK, \ + 0, 0, ISA) + +#define MOPS_SET_INSN(NAME, OPCODE, MASK, ISA) \ + MOPS_SET_OP1_OP2_INSN (NAME, "", OPCODE, MASK, ISA), \ + MOPS_SET_OP1_OP2_INSN (NAME, "t", OPCODE | 0x1000, MASK, ISA), \ + MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \ + MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA) const struct aarch64_opcode aarch64_opcode_table[] = { @@ -5312,6 +5364,51 @@ const struct aarch64_opcode aarch64_opcode_table[] = BFLOAT16_INSN ("bfmlalb", 0x2ec0fc00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, 0), BFLOAT16_INSN ("bfmlalt", 0x4fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0), BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0), + + /* cpyfp cpyfprn cpyfpwn cpyfpn + cpyfm cpyfmrn cpyfmwn cpyfmn + cpyfe cpyfern cpyfewn cpyfen + + cpyfprt cpyfprtrn cpyfprtwn cpyfprtn + cpyfmrt cpyfmrtrn cpyfmrtwn cpyfmrtn + cpyfert cpyfertrn cpyfertwn cpyfertn + + cpyfpwt cpyfpwtrn cpyfpwtwn cpyfpwtn + cpyfmwt cpyfmwtrn cpyfmwtwn cpyfmwtn + cpyfewt cpyfewtrn cpyfewtwn cpyfewtn + + cpyfpt cpyfptrn cpyfptwn cpyfptn + cpyfmt cpyfmtrn cpyfmtwn cpyfmtn + cpyfet cpyfetrn cpyfetwn cpyfetn. */ + MOPS_CPY_INSN ("cpyf", 0x19000400, 0xffe0fc00), + + /* cpyp cpyprn cpypwn cpypn + cpym cpymrn cpymwn cpymn + cpye cpyern cpyewn cpyen + + cpyprt cpyprtrn cpyprtwn cpyprtn + cpymrt cpymrtrn cpymrtwn cpymrtn + cpyert cpyertrn cpyertwn cpyertn + + cpypwt cpypwtrn cpypwtwn cpypwtn + cpymwt cpymwtrn cpymwtwn cpymwtn + cpyewt cpyewtrn cpyewtwn cpyewtn + + cpypt cpyptrn cpyptwn cpyptn + cpymt cpymtrn cpymtwn cpymtn + cpyet cpyetrn cpyetwn cpyetn. */ + MOPS_CPY_INSN ("cpy", 0x1d000400, 0xffe0fc00), + + /* setp setpt setpn setptn + setm setmt setmn setmtn + sete setet seten setetn */ + MOPS_SET_INSN ("set", 0x19c00400, 0xffe0fc00, MOPS_INSN), + + /* setgp setgpt setgpn setgptn + setgm setgmt setgmn setgmtn + setge setget setgen setgetn */ + MOPS_SET_INSN ("setg", 0x1dc00400, 0xffe0fc00, MOPS_MEMTAG_INSN), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -5795,4 +5892,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ - "an indexed SM3 vector immediate") + "an indexed SM3 vector immediate") \ + /* These next two are really register fields; the [...] notation \ + is just syntactic sugar. */ \ + Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd), \ + "a register destination address with writeback") \ + Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \ + "a register source address with writeback") \ + Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn), \ + "an integer register with writeback") |