bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}

This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.

Tested in bpf-unknown-none.

include/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
	(BPF_IMM32_BSWAP32): Likewise.
	(BPF_IMM32_BSWAP64): Likewise.
	(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.

opcodes/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
	instructions.

gas/ChangeLog:

2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
	* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
	* testsuite/gas/bpf/alu.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.

12 files changed, 74 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5538cd2..ef87eea 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
+	* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
+	* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
+	* testsuite/gas/bpf/alu.d: Likewise.
+	* testsuite/gas/bpf/alu-be.d: Likewise.
+	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
+	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
+	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
+
+2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
 	* doc/c-bpf.texi (BPF Instructions): The pseudoc syntax for MOVS*
 	doesn't use `s=' but `='.
 
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
index be29d8d..4cb1561 100644
--- a/gas/doc/c-bpf.texi
+++ b/gas/doc/c-bpf.texi
@@ -404,6 +404,26 @@ Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
 and store it back in @code{rd}.
 @end table
 
+@subsection Byte swap instructions
+
+@table @code
+@item bswap rd, 16
+@itemx rd = bswap16 rd
+Swap the least-significant 16-bit word in @code{rd} with the
+most-significant 16-bit word.
+
+@item bswap rd, 32
+@itemx rd = bswap32 rd
+Swap the least-significant 32-bit word in @code{rd} with the
+most-significant 32-bit word.
+
+@item bswap rd, 64
+@itemx rd = bswap64 rd
+Swap the least-significant 64-bit word in @code{rd} with the
+most-significant 64-bit word.
+@end table
+
+
 @subsection 64-bit load and pseudo maps
 
 @table @code
diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
index 5eb7f39..1d83eac 100644
--- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
@@ -66,3 +66,6 @@ Disassembly of section .text:
  1b8:	bf 12 00 08 00 00 00 00 	r1 = \(s8\) r2
  1c0:	bf 12 00 10 00 00 00 00 	r1 = \(s16\) r2
  1c8:	bf 12 00 20 00 00 00 00 	r1 = \(s32\) r2
+ 1d0:	d7 10 00 00 00 00 00 10 	r1 = bswap16 r1
+ 1d8:	d7 20 00 00 00 00 00 20 	r2 = bswap32 r2
+ 1e0:	d7 30 00 00 00 00 00 40 	r3 = bswap64 r3
diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d
index a082c46..2911d8b 100644
--- a/gas/testsuite/gas/bpf/alu-be.d
+++ b/gas/testsuite/gas/bpf/alu-be.d
@@ -66,3 +66,6 @@ Disassembly of section .text:
  1b8:	bf 12 00 08 00 00 00 00 	movs %r1,%r2,8
  1c0:	bf 12 00 10 00 00 00 00 	movs %r1,%r2,16
  1c8:	bf 12 00 20 00 00 00 00 	movs %r1,%r2,32
+ 1d0:	d7 10 00 00 00 00 00 10 	bswap %r1,16
+ 1d8:	d7 20 00 00 00 00 00 20 	bswap %r2,32
+ 1e0:	d7 30 00 00 00 00 00 40 	bswap %r3,64
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d
index 586fc09..bfc2493 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.d
@@ -66,3 +66,6 @@ Disassembly of section .text:
  1b8:	bf 21 08 00 00 00 00 00 	r1 = \(s8\) r2
  1c0:	bf 21 10 00 00 00 00 00 	r1 = \(s16\) r2
  1c8:	bf 21 20 00 00 00 00 00 	r1 = \(s32\) r2
+ 1d0:	d7 01 00 00 10 00 00 00 	r1 = bswap16 r1
+ 1d8:	d7 02 00 00 20 00 00 00 	r2 = bswap32 r2
+ 1e0:	d7 03 00 00 40 00 00 00 	r3 = bswap64 r3
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s
index 4a47ba6..172a93c 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.s
@@ -58,3 +58,6 @@
         r1 = (s8) r2
         r1 = (s16) r2
         r1 = (s32) r2
+        r1 = bswap16 r1
+        r2 = bswap32 r2
+        r3 = bswap64 r3
diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d
index 409018d..65f3280 100644
--- a/gas/testsuite/gas/bpf/alu.d
+++ b/gas/testsuite/gas/bpf/alu.d
@@ -66,3 +66,6 @@ Disassembly of section .text:
  1b8:	bf 21 08 00 00 00 00 00 	movs %r1,%r2,8
  1c0:	bf 21 10 00 00 00 00 00 	movs %r1,%r2,16
  1c8:	bf 21 20 00 00 00 00 00 	movs %r1,%r2,32
+ 1d0:	d7 01 00 00 10 00 00 00 	bswap %r1,16
+ 1d8:	d7 02 00 00 20 00 00 00 	bswap %r2,32
+ 1e0:	d7 03 00 00 40 00 00 00 	bswap %r3,64
diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s
index 6f8c30f..3e8a3cf 100644
--- a/gas/testsuite/gas/bpf/alu.s
+++ b/gas/testsuite/gas/bpf/alu.s
@@ -58,3 +58,6 @@
         movs    %r1,%r2,8
         movs    %r1,%r2,16
         movs    %r1,%r2,32
+        bswap   %r1, 16
+        bswap   %r2, 32
+        bswap   %r3, 64
diff --git a/include/ChangeLog b/include/ChangeLog
index 8cad8e2..11c1c09 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,12 @@
 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
+	* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
+	(BPF_IMM32_BSWAP32): Likewise.
+	(BPF_IMM32_BSWAP64): Likewise.
+	(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
+
+2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
 	* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
 	(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
 
diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
index dc1b6e7..ed34442 100644
--- a/include/opcode/bpf.h
+++ b/include/opcode/bpf.h
@@ -140,6 +140,10 @@ typedef uint64_t bpf_insn_word;
 #define BPF_IMM32_END32 ((uint64_t)0x00000020)
 #define BPF_IMM32_END64 ((uint64_t)0x00000040)
 
+#define BPF_IMM32_BSWAP16 ((uint64_t)0x00000010)
+#define BPF_IMM32_BSWAP32 ((uint64_t)0x00000020)
+#define BPF_IMM32_BSWAP64 ((uint64_t)0x00000040)
+
 #define BPF_IMM32_AADD ((uint64_t)0x00000000)
 #define BPF_IMM32_AOR  ((uint64_t)0x00000040)
 #define BPF_IMM32_AAND ((uint64_t)0x00000050)
@@ -178,6 +182,8 @@ enum bpf_insn_id
   BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
   BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R,
   BPF_INSN_MOV32R, BPF_INSN_MOV32I,
+  /* Byte swap instructions.  */
+  BPF_INSN_BSWAP16, BPF_INSN_BSWAP32, BPF_INSN_BSWAP64,
   /* Endianness conversion instructions.  */
   BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,
   BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e384815..973b17e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
+	* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
+	instructions.
+
+2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
 	* bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
 	instructions.
 
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index e2691ea..00a21c6 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -182,6 +182,14 @@ const struct bpf_opcode bpf_opcodes[] =
   {BPF_INSN_ENDBE64, "endbe%W%dr , 64", "%dr = be64%w%dr",
    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},
 
+  /* Byte-swap instructions.  */
+  {BPF_INSN_BSWAP16, "bswap%W%dr , 16", "%dr%w=%wbswap16%w%dr",
+   BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP16},
+  {BPF_INSN_BSWAP32, "bswap%W%dr , 32", "%dr%w=%wbswap32%w%dr",
+   BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP32},
+  {BPF_INSN_BSWAP64, "bswap%W%dr , 64", "%dr%w=%wbswap64%w%dr",
+   BPF_V4, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU64|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_BSWAP64},
+
   /* 64-bit load instruction.  */
   {BPF_INSN_LDDW, "lddw%W%dr , %i64", "%dr = %i64%wll",
    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},