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authorAlan Modra <amodra@gmail.com>2019-12-29 12:57:42 +1030
committerAlan Modra <amodra@gmail.com>2019-12-29 22:13:27 +1030
commit4383e1fc3b3269413423c271cb362431b2b70398 (patch)
treeccd3793ab24c6404d8a097a44560c2d283c8ec7b
parent8c5e259235a4e4546910245b170de1e29a711034 (diff)
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ubsan: sparc: left shift cannot be represented in type 'int'
* sparc-dis.c (SEX): Don't use left and right shift to sign extend. (compare_opcodes): Avoid signed shift left overflow. (print_insn_sparc): Likewise.
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/sparc-dis.c15
2 files changed, 12 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5187fb2..bde9b92 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2019-12-29 Alan Modra <amodra@gmail.com>
+ * sparc-dis.c (SEX): Don't use left and right shift to sign extend.
+ (compare_opcodes): Avoid signed shift left overflow.
+ (print_insn_sparc): Likewise.
+
+2019-12-29 Alan Modra <amodra@gmail.com>
+
PR 25319
* tic4x-dis.c (tic4x_print_cond): Init all of condtable.
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index bdf018d..57bde0e 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -63,8 +63,8 @@ static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
/* Sign-extend a value which is N bits long. */
#define SEX(value, bits) \
- ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
- >> ((8 * sizeof (int)) - bits) )
+ ((int) (((value & ((1u << (bits - 1) << 1) - 1)) \
+ ^ (1u << (bits - 1))) - (1u << (bits - 1))))
static char *reg_names[] =
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
@@ -325,7 +325,7 @@ compare_opcodes (const void * a, const void * b)
another, it is important to order the opcodes in the right order. */
for (i = 0; i < 32; ++i)
{
- unsigned long int x = 1 << i;
+ unsigned long int x = 1ul << i;
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
@@ -335,7 +335,7 @@ compare_opcodes (const void * a, const void * b)
for (i = 0; i < 32; ++i)
{
- unsigned long int x = 1 << i;
+ unsigned long int x = 1ul << i;
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
@@ -712,8 +712,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
- ((unsigned) 0xFFFFFFFF
- & ((int) X_IMM22 (insn) << 10)));
+ (unsigned) X_IMM22 (insn) << 10);
break;
case 'i': /* 13 bit immediate. */
@@ -1062,9 +1061,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
- info->target =
- ((unsigned) 0xFFFFFFFF
- & ((int) X_IMM22 (prev_insn) << 10));
+ info->target = (unsigned) X_IMM22 (prev_insn) << 10;
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else