sim: cr16: migrate to standard uintXX_t types

This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.

Also migrate off the sim-specific unsignedXX types.

3 files changed, 621 insertions, 630 deletions

diff --git a/sim/cr16/cr16_sim.h b/sim/cr16/cr16_sim.h
index 54df026..86ee50a 100644
--- a/sim/cr16/cr16_sim.h
+++ b/sim/cr16/cr16_sim.h
@@ -44,25 +44,16 @@ extern int cr16_debug;
 #include "sim-config.h"
 #include "sim-types.h"
 
-typedef unsigned8 uint8;
-typedef signed8 int8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
 /* FIXME: CR16 defines */
-typedef uint16 reg_t;
-typedef uint32 creg_t;
+typedef uint16_t reg_t;
+typedef uint32_t creg_t;
 
 struct simops 
 {
   char mnemonic[12];
-  uint32 size;
-  uint32 mask;
-  uint32 opcode;
+  uint32_t size;
+  uint32_t mask;
+  uint32_t opcode;
   int format;
   char fname[12];
   void (*func)(SIM_DESC, SIM_CPU *);
@@ -205,7 +196,7 @@ struct _state
 
 #define GPR32(N) \
      (N < 12) ? \
-     ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \
+     ((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \
      : GPR (N) 
 
 #define SET_GPR32(N,VAL) do { \
@@ -232,7 +223,7 @@ struct _state
 
   /* trace data */
   struct {
-    uint16 psw;
+    uint16_t psw;
   } trace;
 
   int	pc_changed;
@@ -247,8 +238,8 @@ struct _state
 extern struct _state State;
 
 
-extern uint32 OP[4];
-extern uint32 sign_flag;
+extern uint32_t OP[4];
+extern uint32_t sign_flag;
 extern struct simops Simops[];
 
 enum
@@ -394,7 +385,7 @@ enum
 
 /* Yes, this is as whacked as it looks.  The sim currently reads little endian
    for 16 bits, but then merge them like big endian to get 32 bits.  */
-static inline uint32 get_longword (SIM_CPU *cpu, address_word addr)
+static inline uint32_t get_longword (SIM_CPU *cpu, address_word addr)
 {
   return (RW (addr) << 16) | RW (addr + 2);
 }
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index 5ba752f..47fb647 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -42,19 +42,19 @@ struct _state State;
 
 int cr16_debug;
 
-uint32 OP[4];
-uint32 sign_flag;
+uint32_t OP[4];
+uint32_t sign_flag;
 
-static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size);
-static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
+static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64_t ins, int size);
+static void get_operands (operand_desc *s, uint64_t mcode, int isize, int nops);
 
 #define MAX_HASH  16
 
 struct hash_entry
 {
   struct hash_entry *next;
-  uint32 opcode;
-  uint32 mask;
+  uint32_t opcode;
+  uint32_t mask;
   int format;
   int size;
   struct simops *ops;
@@ -77,9 +77,9 @@ hash(unsigned long long insn, int format)
 
 
 INLINE static struct hash_entry *
-lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
+lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64_t ins, int size)
 {
-  uint32 mask;
+  uint32_t mask;
   struct hash_entry *h;
 
   h = &hash_table[hash(ins,1)];
@@ -108,10 +108,10 @@ lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
 }
 
 INLINE static void
-get_operands (operand_desc *s, uint64 ins, int isize, int nops)
+get_operands (operand_desc *s, uint64_t ins, int isize, int nops)
 {
-  uint32 i, opn = 0, start_bit = 0, op_type = 0; 
-  int32 op_size = 0, mask = 0;
+  uint32_t i, opn = 0, start_bit = 0, op_type = 0; 
+  int32_t op_size = 0, mask = 0;
 
   if (isize == 1) /* Trunkcate the extra 16 bits of INS.  */
     ins = ins >> 16;
@@ -328,7 +328,7 @@ get_operands (operand_desc *s, uint64 ins, int isize, int nops)
 }
 
 static int
-do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
+do_run (SIM_DESC sd, SIM_CPU *cpu, uint64_t mcode)
 {
   struct hash_entry *h;
 
@@ -579,8 +579,8 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
 static void
 step_once (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 curr_ins_size = 0;
-  uint64 mcode = RLW (PC);
+  uint32_t curr_ins_size = 0;
+  uint64_t mcode = RLW (PC);
 
   State.pc_changed = 0;
 
@@ -689,10 +689,10 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
   return SIM_RC_OK;
 }
 
-static uint32
+static uint32_t
 cr16_extract_unsigned_integer (unsigned char *addr, int len)
 {
-  uint32 retval;
+  uint32_t retval;
   unsigned char * p;
   unsigned char * startaddr = (unsigned char *)addr;
   unsigned char * endaddr = startaddr + len;
@@ -706,7 +706,7 @@ cr16_extract_unsigned_integer (unsigned char *addr, int len)
 }
 
 static void
-cr16_store_unsigned_integer (unsigned char *addr, int len, uint32 val)
+cr16_store_unsigned_integer (unsigned char *addr, int len, uint32_t val)
 {
   unsigned char *p;
   unsigned char *startaddr = addr;
diff --git a/sim/cr16/simops.c b/sim/cr16/simops.c
index f668aca..d58c0c9 100644
--- a/sim/cr16/simops.c
+++ b/sim/cr16/simops.c
@@ -362,7 +362,7 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
 	  break;
 
 	case OP_MEMREF2:
-	  sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
+	  sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
 	  p += strlen (p);
 	  comma = ",";
 	  break;
@@ -398,39 +398,39 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
 
 	    case OP_REG:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16) GPR (OP[i]));
+						 (uint16_t) GPR (OP[i]));
 	      break;
 
 	    case OP_REGP:
-	      tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
+	      tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
 	      sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
 	      break;
 
 	    case OP_PROC_REG:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16) CREG (OP[i]));
+						 (uint16_t) CREG (OP[i]));
 	      break;
 
 	    case OP_CONSTANT16:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)OP[i]);
+						 (uint16_t)OP[i]);
 	      break;
 
 	    case OP_CONSTANT4:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)SEXT4(OP[i]));
+						 (uint16_t)SEXT4(OP[i]));
 	      break;
 
 	    case OP_CONSTANT3:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)SEXT3(OP[i]));
+						 (uint16_t)SEXT3(OP[i]));
 	      break;
 
 	    case OP_MEMREF2:
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)OP[i]);
+						 (uint16_t)OP[i]);
 	      sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)GPR (OP[i + 1]));
+						 (uint16_t)GPR (OP[i + 1]));
 	      i++;
 	      break;
 	    }
@@ -459,7 +459,7 @@ do_trace_output_finish (SIM_DESC sd)
 
 #if 0
 static void
-trace_output_40 (SIM_DESC sd, uint64 val)
+trace_output_40 (SIM_DESC sd, uint64_t val)
 {
   if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
     {
@@ -475,7 +475,7 @@ trace_output_40 (SIM_DESC sd, uint64 val)
 #endif
 
 static void
-trace_output_32 (SIM_DESC sd, uint32 val)
+trace_output_32 (SIM_DESC sd, uint32_t val)
 {
   if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
     {
@@ -489,7 +489,7 @@ trace_output_32 (SIM_DESC sd, uint32 val)
 }
 
 static void
-trace_output_16 (SIM_DESC sd, uint16 val)
+trace_output_16 (SIM_DESC sd, uint16_t val)
 {
   if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
     {
@@ -537,9 +537,9 @@ trace_output_flag (SIM_DESC sd)
 void
 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp;
-  uint8 a = OP[0] & 0xff;
-  uint16 b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint16_t b = (GPR (OP[1])) & 0xff;
   trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
   tmp = (a + b) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -550,8 +550,8 @@ OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp;
-  uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
+  uint16_t tmp;
+  uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
   trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = (a + b) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -562,9 +562,9 @@ OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (GPR (OP[0])) & 0xff;
-  uint8 b = (GPR (OP[1])) & 0xff;
-  uint16 tmp = (a + b) & 0xff;
+  uint8_t a = (GPR (OP[0])) & 0xff;
+  uint8_t b = (GPR (OP[1])) & 0xff;
+  uint16_t tmp = (a + b) & 0xff;
   trace_input ("addub", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   trace_output_16 (sd, tmp);
@@ -574,9 +574,9 @@ OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b);
+  uint16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b);
   trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   trace_output_16 (sd, tmp);
@@ -586,9 +586,9 @@ OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b);
+  uint16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b);
   trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   trace_output_16 (sd, tmp);
@@ -598,9 +598,9 @@ OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b);
+  uint16_t a = GPR (OP[0]);
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b);
   trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   trace_output_16 (sd, tmp);
@@ -610,9 +610,9 @@ OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0];
-  uint8 b = (GPR (OP[1]) & 0xff);
-  uint16 tmp = (a + b) & 0xff;
+  uint8_t a = OP[0];
+  uint8_t b = (GPR (OP[1]) & 0xff);
+  uint16_t tmp = (a + b) & 0xff;
   trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   SET_PSR_C (tmp > 0xFF);
@@ -624,9 +624,9 @@ OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint8 b = (GPR (OP[1]) & 0xff);
-  uint16 tmp = (a + b) & 0xff;
+  uint8_t a = (OP[0]) & 0xff;
+  uint8_t b = (GPR (OP[1]) & 0xff);
+  uint16_t tmp = (a + b) & 0xff;
   trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   SET_PSR_C (tmp > 0xFF);
@@ -638,9 +638,9 @@ OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (GPR (OP[0]) & 0xff);
-  uint8 b = (GPR (OP[1]) & 0xff);
-  uint16 tmp = (a + b) & 0xff;
+  uint8_t a = (GPR (OP[0]) & 0xff);
+  uint8_t b = (GPR (OP[1]) & 0xff);
+  uint16_t tmp = (a + b) & 0xff;
   trace_input ("addb", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   SET_PSR_C (tmp > 0xFF);
@@ -652,8 +652,8 @@ OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = OP[0];
-  uint16 tmp, b = GPR (OP[1]);
+  int16_t a = OP[0];
+  uint16_t tmp, b = GPR (OP[1]);
   tmp = (a + b);
   trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
@@ -666,8 +666,8 @@ OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = OP[0];
-  uint16 tmp, b = GPR (OP[1]);
+  int16_t a = OP[0];
+  uint16_t tmp, b = GPR (OP[1]);
   tmp = (a + b);
   trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
@@ -680,7 +680,7 @@ OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+  uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("addw", OP_REG, OP_REG, OP_VOID);
   tmp = (a + b);
   SET_GPR (OP[1], tmp);
@@ -693,7 +693,7 @@ OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
   tmp = (a + b + PSR_C) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -706,9 +706,9 @@ OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int8 a = OP[0] & 0xff;
-  uint8 b = (GPR (OP[1])) & 0xff;
-  uint8 tmp = (a + b + PSR_C) & 0xff;
+  int8_t a = OP[0] & 0xff;
+  uint8_t b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp = (a + b + PSR_C) & 0xff;
   trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   SET_PSR_C (tmp > 0xFF);
@@ -720,9 +720,9 @@ OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (GPR (OP[0])) & 0xff;
-  uint8 b = (GPR (OP[1])) & 0xff;
-  uint8 tmp = (a + b + PSR_C) & 0xff;
+  uint8_t a = (GPR (OP[0])) & 0xff;
+  uint8_t b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp = (a + b + PSR_C) & 0xff;
   trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
   SET_PSR_C (tmp > 0xFF);
@@ -734,9 +734,9 @@ OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b + PSR_C);
+  uint16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b + PSR_C);
   trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   SET_PSR_C (tmp > 0xFFFF);
@@ -748,9 +748,9 @@ OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b + PSR_C);
+  int16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b + PSR_C);
   trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   SET_PSR_C (tmp > 0xFFFF);
@@ -762,9 +762,9 @@ OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[1]);
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (a + b + PSR_C);
+  uint16_t a = GPR (OP[1]);
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (a + b + PSR_C);
   trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], tmp);
   SET_PSR_C (tmp > 0xFFFF);
@@ -776,9 +776,9 @@ OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = (OP[0]);
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp = (a + b);
+  int16_t a = (OP[0]);
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp = (a + b);
   trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   SET_PSR_C (tmp > 0xFFFFFFFF);
@@ -790,9 +790,9 @@ OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 a = (SEXT16(OP[0]));
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp = (a + b);
+  int32_t a = (SEXT16(OP[0]));
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp = (a + b);
   trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   SET_PSR_C (tmp > 0xFFFFFFFF);
@@ -804,9 +804,9 @@ OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]);
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp = (a + b);
+  uint32_t a = GPR32 (OP[0]);
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp = (a + b);
   trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -818,9 +818,9 @@ OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = OP[0];
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp;
+  uint32_t a = OP[0];
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp;
   trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
   tmp = (a + b);
   SET_GPR32 (OP[1], tmp);
@@ -833,9 +833,9 @@ OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 a = OP[0];
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp;
+  int32_t a = OP[0];
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp;
   trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
   tmp = (a + b);
   SET_GPR32 (OP[1], tmp);
@@ -848,7 +848,7 @@ OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -859,7 +859,7 @@ OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -870,7 +870,7 @@ OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("andb", OP_REG, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -881,7 +881,7 @@ OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = OP[0], b = GPR (OP[1]);
+  uint16_t tmp, a = OP[0], b = GPR (OP[1]);
   trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], tmp);
@@ -892,7 +892,7 @@ OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = OP[0], b = GPR (OP[1]);
+  uint16_t tmp, a = OP[0], b = GPR (OP[1]);
   trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], tmp);
@@ -903,7 +903,7 @@ OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
+  uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
   trace_input ("andw", OP_REG, OP_REG, OP_VOID);
   tmp = a & b;
   SET_GPR (OP[1], tmp);
@@ -914,7 +914,7 @@ OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = OP[0],  b = GPR32 (OP[1]);
+  uint32_t tmp, a = OP[0],  b = GPR32 (OP[1]);
   trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
   tmp = a & b;
   SET_GPR32 (OP[1], tmp);
@@ -925,7 +925,7 @@ OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
+  uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
   trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
   tmp = a & b;
   SET_GPR32 (OP[1], tmp);
@@ -936,7 +936,7 @@ OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+  uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
   trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR32 (OP[1], tmp);
@@ -947,7 +947,7 @@ OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+  uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
   trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
   tmp = a | b;
   SET_GPR32 (OP[1], tmp);
@@ -958,7 +958,7 @@ OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+  uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
   trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR32 (OP[1], tmp);
@@ -969,7 +969,7 @@ OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+  uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
   trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
   tmp = a ^ b;
   SET_GPR32 (OP[1], tmp);
@@ -981,7 +981,7 @@ OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0, cc = cond_stat (OP[0]);
+  uint32_t tmp = 0, cc = cond_stat (OP[0]);
   trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
   if  (cc)
     {
@@ -1008,7 +1008,7 @@ OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0, cc = cond_stat (OP[0]);
+  uint32_t tmp = 0, cc = cond_stat (OP[0]);
   trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
   if (cc)
     {
@@ -1035,7 +1035,7 @@ OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0, cc = cond_stat (OP[0]);
+  uint32_t tmp = 0, cc = cond_stat (OP[0]);
   trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
   if (cc)
     {
@@ -1062,7 +1062,7 @@ OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
   tmp =  ((PC + 4) >> 1); /* Store PC in RA register. */
   SET_GPR32 (14, tmp);
@@ -1090,7 +1090,7 @@ OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
   tmp = (((PC) + 4) >> 1); /* Store PC in reg pair.  */
   SET_GPR32 (OP[0], tmp);
@@ -1116,7 +1116,7 @@ OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
   SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
   tmp = GPR32 (OP[1]);
@@ -1140,7 +1140,7 @@ OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
   SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
   tmp = GPR32 (OP[0]);
@@ -1164,8 +1164,8 @@ OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint8 a = (GPR (OP[0]) & 0xFF);
+  uint32_t addr;
+  uint8_t a = (GPR (OP[0]) & 0xFF);
   trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
   addr = OP[1];
   if (a == 0) 
@@ -1185,8 +1185,8 @@ OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint8 a = (GPR (OP[0]) & 0xFF);
+  uint32_t addr;
+  uint8_t a = (GPR (OP[0]) & 0xFF);
   trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
   addr = OP[1];
   if (a != 0) 
@@ -1206,8 +1206,8 @@ OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = GPR (OP[0]);
+  uint32_t addr;
+  uint16_t a = GPR (OP[0]);
   trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
   addr = OP[1];
   if (a == 0) 
@@ -1227,8 +1227,8 @@ OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = GPR (OP[0]);
+  uint32_t addr;
+  uint16_t a = GPR (OP[0]);
   trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
   addr = OP[1];
   if (a != 0) 
@@ -1249,7 +1249,7 @@ OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_Z) == 1)
   {
@@ -1263,7 +1263,7 @@ OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_Z) == 0)
   {
@@ -1277,7 +1277,7 @@ OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_C) == 1)
   {
@@ -1291,7 +1291,7 @@ OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_C) == 0)
   {
@@ -1305,7 +1305,7 @@ OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_L) == 1)
   {
@@ -1319,7 +1319,7 @@ OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_L) == 0)
   {
@@ -1333,7 +1333,7 @@ OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_N) == 1)
   {
@@ -1347,7 +1347,7 @@ OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_N) == 0)
   {
@@ -1362,7 +1362,7 @@ OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_F) == 1)
   {
@@ -1376,7 +1376,7 @@ OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
   if ((PSR_F) == 0)
   {
@@ -1390,7 +1390,7 @@ OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
   if (((PSR_Z) == 0) & ((PSR_L) == 0))
   {
@@ -1404,7 +1404,7 @@ OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
   if (((PSR_Z) == 1) | ((PSR_L) == 1))
   {
@@ -1418,7 +1418,7 @@ OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
   if (((PSR_Z) == 0) & ((PSR_N) == 0))
   {
@@ -1432,7 +1432,7 @@ OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = 0;
+  uint32_t tmp = 0;
   trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
   if (((PSR_Z) == 1) | ((PSR_N) == 1))
   {
@@ -1446,7 +1446,7 @@ OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
   tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
   JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
@@ -1457,7 +1457,7 @@ OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
   tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
   JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
@@ -1637,8 +1637,8 @@ OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1651,8 +1651,8 @@ OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1665,8 +1665,8 @@ OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1679,8 +1679,8 @@ OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1693,8 +1693,8 @@ OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1707,8 +1707,8 @@ OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1721,8 +1721,8 @@ OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1736,8 +1736,8 @@ OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1750,8 +1750,8 @@ OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1765,8 +1765,8 @@ OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1779,8 +1779,8 @@ OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1793,8 +1793,8 @@ OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = (OP[0]), tmp;
+  uint32_t addr;
+  uint16_t a = (OP[0]), tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -1814,8 +1814,8 @@ OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1828,8 +1828,8 @@ OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1843,8 +1843,8 @@ OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1857,8 +1857,8 @@ OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1872,8 +1872,8 @@ OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1886,8 +1886,8 @@ OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1900,8 +1900,8 @@ OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1914,8 +1914,8 @@ OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1928,8 +1928,8 @@ OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1942,8 +1942,8 @@ OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1956,8 +1956,8 @@ OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1971,8 +1971,8 @@ OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -1985,8 +1985,8 @@ OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2000,8 +2000,8 @@ OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2015,8 +2015,8 @@ OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2030,8 +2030,8 @@ OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2044,8 +2044,8 @@ OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2058,8 +2058,8 @@ OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = (OP[0]), tmp;
+  uint32_t addr;
+  uint16_t a = (OP[0]), tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -2078,8 +2078,8 @@ OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2092,8 +2092,8 @@ OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2106,8 +2106,8 @@ OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2120,8 +2120,8 @@ OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2134,8 +2134,8 @@ OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2148,8 +2148,8 @@ OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2163,8 +2163,8 @@ OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2175,8 +2175,8 @@ OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xff;
-  uint32 addr = OP[1], tmp;
+  uint8_t a = OP[0] & 0xff;
+  uint32_t addr = OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2187,8 +2187,8 @@ OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2199,8 +2199,8 @@ OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2211,8 +2211,8 @@ OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2223,8 +2223,8 @@ OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2235,8 +2235,8 @@ OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2247,8 +2247,8 @@ OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2259,8 +2259,8 @@ OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RB (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2272,8 +2272,8 @@ OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2284,8 +2284,8 @@ OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1], tmp;
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2297,8 +2297,8 @@ OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = (OP[0]), tmp;
+  uint32_t addr;
+  uint16_t a = (OP[0]), tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -2315,8 +2315,8 @@ OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2327,8 +2327,8 @@ OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2339,8 +2339,8 @@ OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2351,8 +2351,8 @@ OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2363,8 +2363,8 @@ OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2376,8 +2376,8 @@ OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+  uint16_t a = (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
   trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   tmp = RW (addr);
   SET_PSR_F (tmp & (1 << a));
@@ -2389,8 +2389,8 @@ OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = (GPR (OP[1]));
+  uint16_t a = OP[0];
+  uint16_t b = (GPR (OP[1]));
   trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
   SET_PSR_F (b & (1 << a));
   trace_output_16 (sd, b);
@@ -2400,8 +2400,8 @@ OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint16 b = (GPR (OP[1]));
+  uint16_t a = GPR (OP[0]);
+  uint16_t b = (GPR (OP[1]));
   trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
   SET_PSR_F (b & (1 << a));
   trace_output_16 (sd, b);
@@ -2412,11 +2412,11 @@ OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xFF; 
-  uint8 b = (GPR (OP[1])) & 0xFF;
+  uint8_t a = (OP[0]) & 0xFF; 
+  uint8_t b = (GPR (OP[1])) & 0xFF;
   trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int8)a > (int8)b);
+  SET_PSR_N ((int8_t)a > (int8_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2425,11 +2425,11 @@ OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xFF; 
-  uint8 b = (GPR (OP[1])) & 0xFF;
+  uint8_t a = (OP[0]) & 0xFF; 
+  uint8_t b = (GPR (OP[1])) & 0xFF;
   trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int8)a > (int8)b);
+  SET_PSR_N ((int8_t)a > (int8_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2438,11 +2438,11 @@ OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (GPR (OP[0])) & 0xFF; 
-  uint8 b = (GPR (OP[1])) & 0xFF;
+  uint8_t a = (GPR (OP[0])) & 0xFF; 
+  uint8_t b = (GPR (OP[1])) & 0xFF;
   trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int8)a > (int8)b);
+  SET_PSR_N ((int8_t)a > (int8_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2451,11 +2451,11 @@ OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]); 
-  uint16 b = GPR (OP[1]);
+  uint16_t a = (OP[0]); 
+  uint16_t b = GPR (OP[1]);
   trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int16)a > (int16)b);
+  SET_PSR_N ((int16_t)a > (int16_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2464,11 +2464,11 @@ OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (OP[0]); 
-  uint16 b = GPR (OP[1]);
+  uint16_t a = (OP[0]); 
+  uint16_t b = GPR (OP[1]);
   trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int16)a > (int16)b);
+  SET_PSR_N ((int16_t)a > (int16_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2477,11 +2477,11 @@ OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]) ; 
-  uint16 b = GPR (OP[1]) ;
+  uint16_t a = GPR (OP[0]) ; 
+  uint16_t b = GPR (OP[1]) ;
   trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int16)a > (int16)b);
+  SET_PSR_N ((int16_t)a > (int16_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2490,11 +2490,11 @@ OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = (OP[0]); 
-  uint32 b = GPR32 (OP[1]);
+  uint32_t a = (OP[0]); 
+  uint32_t b = GPR32 (OP[1]);
   trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int32)a > (int32)b);
+  SET_PSR_N ((int32_t)a > (int32_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2503,11 +2503,11 @@ OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = (SEXT16(OP[0])); 
-  uint32 b = GPR32 (OP[1]);
+  uint32_t a = (SEXT16(OP[0])); 
+  uint32_t b = GPR32 (OP[1]);
   trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int32)a > (int32)b);
+  SET_PSR_N ((int32_t)a > (int32_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2516,11 +2516,11 @@ OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]) ; 
-  uint32 b = GPR32 (OP[1]) ;
+  uint32_t a = GPR32 (OP[0]) ; 
+  uint32_t b = GPR32 (OP[1]) ;
   trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int32)a > (int32)b);
+  SET_PSR_N ((int32_t)a > (int32_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2529,11 +2529,11 @@ OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = (OP[0]); 
-  uint32 b = GPR32 (OP[1]);
+  uint32_t a = (OP[0]); 
+  uint32_t b = GPR32 (OP[1]);
   trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
   SET_PSR_Z (a == b);
-  SET_PSR_N ((int32)a > (int32)b);
+  SET_PSR_N ((int32_t)a > (int32_t)b);
   SET_PSR_L (a > b);
   trace_output_flag (sd);
 }
@@ -2543,8 +2543,8 @@ OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp = OP[0] & 0xFF;
-  uint16 a = (GPR (OP[1])) & 0xFF00;
+  uint8_t tmp = OP[0] & 0xFF;
+  uint16_t a = (GPR (OP[1])) & 0xFF00;
   trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
   SET_GPR (OP[1], (a | tmp));
   trace_output_16 (sd, tmp);
@@ -2554,8 +2554,8 @@ OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp = OP[0] & 0xFF;
-  uint16 a = (GPR (OP[1])) & 0xFF00;
+  uint8_t tmp = OP[0] & 0xFF;
+  uint16_t a = (GPR (OP[1])) & 0xFF00;
   trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], (a | tmp));
   trace_output_16 (sd, tmp);
@@ -2565,8 +2565,8 @@ OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp = (GPR (OP[0])) & 0xFF;
-  uint16 a = (GPR (OP[1])) & 0xFF00;
+  uint8_t tmp = (GPR (OP[0])) & 0xFF;
+  uint16_t a = (GPR (OP[1])) & 0xFF00;
   trace_input ("movb", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], (a | tmp));
   trace_output_16 (sd, tmp);
@@ -2576,7 +2576,7 @@ OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp = OP[0];
+  uint16_t tmp = OP[0];
   trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp & 0xffff));
   trace_output_16 (sd, tmp);
@@ -2586,7 +2586,7 @@ OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp = OP[0];
+  int16_t tmp = OP[0];
   trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
   SET_GPR (OP[1], (tmp & 0xffff));
   trace_output_16 (sd, tmp);
@@ -2596,8 +2596,8 @@ OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp = GPR (OP[0]);
-  uint32 a = GPR32 (OP[1]);
+  uint16_t tmp = GPR (OP[0]);
+  uint32_t a = GPR32 (OP[1]);
   trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
   a = (a & 0xffff0000) | tmp;
   SET_GPR32 (OP[1], a);
@@ -2608,7 +2608,7 @@ OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp = (GPR (OP[0])) & 0xFF;
+  uint8_t tmp = (GPR (OP[0])) & 0xFF;
   trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
   trace_output_16 (sd, tmp);
@@ -2618,7 +2618,7 @@ OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp = (GPR (OP[0])) & 0xFF;
+  uint8_t tmp = (GPR (OP[0])) & 0xFF;
   trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1],  tmp);
   trace_output_16 (sd, tmp);
@@ -2628,7 +2628,7 @@ OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp = GPR (OP[0]);
+  uint16_t tmp = GPR (OP[0]);
   trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], SEXT16(tmp));
   trace_output_16 (sd, tmp);
@@ -2638,7 +2638,7 @@ OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp = GPR (OP[0]);
+  uint16_t tmp = GPR (OP[0]);
   trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
   trace_output_16 (sd, tmp);
@@ -2648,7 +2648,7 @@ OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp = OP[0];
+  int32_t tmp = OP[0];
   trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -2658,7 +2658,7 @@ OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp = SEXT16(OP[0]);
+  int32_t tmp = SEXT16(OP[0]);
   trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -2668,7 +2668,7 @@ OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = GPR32 (OP[0]);
+  uint32_t tmp = GPR32 (OP[0]);
   trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -2678,7 +2678,7 @@ OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp = OP[0];
+  uint32_t tmp = OP[0];
   trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -2688,7 +2688,7 @@ OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp = OP[0];
+  int32_t tmp = OP[0];
   trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], tmp);
   trace_output_32 (sd, tmp);
@@ -2698,8 +2698,8 @@ OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr = GPR (0);
-  uint16 count = OP[0], reg = 2, tmp;
+  uint32_t addr = GPR (0);
+  uint16_t count = OP[0], reg = 2, tmp;
   trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
   if ((addr & 1))
     {
@@ -2726,8 +2726,8 @@ OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr = GPR32 (0);
-  uint16 count = OP[0], reg = 2, tmp;
+  uint32_t addr = GPR32 (0);
+  uint16_t count = OP[0], reg = 2, tmp;
   trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
   if ((addr & 1))
     {
@@ -2762,8 +2762,8 @@ OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
    * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 
    * by the core to 16M-64k to 16M. */
 
-  uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
-  uint32 addr = OP[0];
+  uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+  uint32_t addr = OP[0];
   trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
   if (addr > 0xEFFFF) addr |= 0xF00000;
   tmp = (RB (addr));
@@ -2779,8 +2779,8 @@ OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = abs24
    * REGR = [ADDR].   */
 
-  uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
-  uint32 addr = OP[0];
+  uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+  uint32_t addr = OP[0];
   trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[1], (a | tmp));
@@ -2795,8 +2795,8 @@ OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rindex + zext24(disp20)
    * REGR = [ADDR].   */
 
-  uint32 addr;
-  uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr;
+  uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
   trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
 
   if (OP[0] == 0)
@@ -2817,8 +2817,8 @@ OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadb DIPS4(REGP)   REG 
    * ADDR = RPBASE + zext24(DISP4)
    * REG = [ADDR].  */
-  uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr = (GPR32 (OP[1])) + OP[0];
+  uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr = (GPR32 (OP[1])) + OP[0];
   trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2833,8 +2833,8 @@ OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+  uint32_t addr;
+  uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
   trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
 
   addr =  (GPR32 (OP[2])) + OP[1];
@@ -2857,8 +2857,8 @@ OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex + zext24(disp14)
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+  uint32_t addr;
+  uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
 
   addr =  (GPR32 (OP[2])) + OP[1];
 
@@ -2882,8 +2882,8 @@ OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
    * zext24(Rbase) + zext24(dispe20)
    * REG = [ADDR]   */
 
-  uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr = OP[0] + (GPR (OP[1]));
+  uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr = OP[0] + (GPR (OP[1]));
   trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2898,8 +2898,8 @@ OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = zext24(Rbase) + zext24(disp20)
    * REG = [ADDR]                          */
 
-  uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr = OP[0] + (GPR (OP[1]));
+  uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr = OP[0] + (GPR (OP[1]));
   trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2914,8 +2914,8 @@ OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(disp16)
    * REGR = [ADDR]   */
 
-  uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr = (GPR32 (OP[1])) + OP[0];
+  uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr = (GPR32 (OP[1])) + OP[0];
   trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2929,8 +2929,8 @@ OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadb disp20(REGP)   REG
    * ADDR = RPbase + zext24(disp20)
    * REGR = [ADDR]   */
-  uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr =  (GPR32 (OP[1])) + OP[0];
+  uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr =  (GPR32 (OP[1])) + OP[0];
   trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2945,8 +2945,8 @@ OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadb -disp20(REGP)   REG
    * ADDR = RPbase + zext24(-disp20)
    * REGR = [ADDR]   */
-  uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
-  uint32 addr =  (GPR32 (OP[1])) + OP[1];
+  uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+  uint32_t addr =  (GPR32 (OP[1])) + OP[1];
   trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
   tmp = (RB (addr));
   SET_GPR (OP[2], (a | tmp));
@@ -2961,8 +2961,8 @@ OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbasex + Rindex + zext24(disp20)
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+  uint32_t addr;
+  uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
   trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
 
   addr = (GPR32 (OP[2])) + OP[1];
@@ -2990,8 +2990,8 @@ OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
    * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 
    * by the core to 16M-64k to 16M. */
 
-  uint16 tmp; 
-  uint32 addr = OP[0];
+  uint16_t tmp; 
+  uint32_t addr = OP[0];
   trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
   if (addr > 0xEFFFF) addr |= 0xF00000;
   tmp = (RW (addr));
@@ -3007,8 +3007,8 @@ OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadw ABS24, REG 
    * ADDR = abs24
    * REGR = [ADDR]  */
-  uint16 tmp; 
-  uint32 addr = OP[0];
+  uint16_t tmp; 
+  uint32_t addr = OP[0];
   trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
   tmp = (RW (addr));
   SET_GPR (OP[1], tmp);
@@ -3023,8 +3023,8 @@ OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rindex + zext24(disp20)
    * REGR = [ADDR]  */
 
-  uint32 addr;
-  uint16 tmp; 
+  uint32_t addr;
+  uint16_t tmp; 
   trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
 
   if (OP[0] == 0)
@@ -3045,8 +3045,8 @@ OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadw DIPS4(REGP)   REGP
    * ADDR = RPBASE + zext24(DISP4)
    * REGP = [ADDR].  */
-  uint16 tmp;
-  uint32 addr, a;
+  uint16_t tmp;
+  uint32_t addr, a;
   trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
   addr = (GPR32 (OP[1])) + OP[0];
   tmp =  (RW (addr));
@@ -3070,8 +3070,8 @@ OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp;
+  uint32_t addr;
+  uint16_t tmp;
   trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
 
   addr = (GPR32 (OP[2])) + OP[1];
@@ -3095,8 +3095,8 @@ OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex + zext24(disp14)
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp;
+  uint32_t addr;
+  uint16_t tmp;
   trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
   addr =  (GPR32 (OP[2])) + OP[1];
 
@@ -3117,8 +3117,8 @@ OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadw dispe20(REG)   REGP
    * REGP = [DISPE20+[REG]]   */
 
-  uint16 tmp;
-  uint32 addr, a; 
+  uint16_t tmp;
+  uint32_t addr, a; 
   trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
   addr = OP[0] + (GPR (OP[1]));
   tmp = (RW (addr));
@@ -3142,8 +3142,8 @@ OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = zext24(Rbase) + zext24(disp20)
    * REGP = [ADDR]                          */
 
-  uint16 tmp;
-  uint32 addr, a;
+  uint16_t tmp;
+  uint32_t addr, a;
   trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
   addr = OP[0] + (GPR (OP[1]));
   tmp = (RW (addr));
@@ -3165,8 +3165,8 @@ OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadw disp16(REGP)   REGP
    * ADDR = RPbase + zext24(disp16)
    * REGP = [ADDR]   */
-  uint16 tmp;
-  uint32 addr, a;
+  uint16_t tmp;
+  uint32_t addr, a;
   trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
   addr = (GPR32 (OP[1])) + OP[0];
   tmp = (RW (addr));
@@ -3188,8 +3188,8 @@ OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadw disp20(REGP)   REGP
    * ADDR = RPbase + zext24(disp20)
    * REGP = [ADDR]   */
-  uint16 tmp;
-  uint32 addr, a;
+  uint16_t tmp;
+  uint32_t addr, a;
   trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
   addr = (GPR32 (OP[1])) + OP[0];
   tmp = (RW (addr));
@@ -3212,8 +3212,8 @@ OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(-disp20)
    * REGR = [ADDR]   */
 
-  uint16 tmp;
-  uint32 addr, a;
+  uint16_t tmp;
+  uint32_t addr, a;
   trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
   addr = (GPR32 (OP[1])) + OP[0];
   tmp = (RB (addr));
@@ -3237,8 +3237,8 @@ OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbasex + Rindex + zext24(disp20)
    * REGR = [ADDR]   */
 
-  uint32 addr;
-  uint16 tmp;
+  uint32_t addr;
+  uint16_t tmp;
   trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
 
   if (OP[0] == 0)
@@ -3264,7 +3264,7 @@ OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
    * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 
    * by the core to 16M-64k to 16M. */
 
-  uint32 addr, tmp;
+  uint32_t addr, tmp;
   addr = OP[0];
   trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
   if (addr > 0xEFFFF) addr |= 0xF00000;
@@ -3282,8 +3282,8 @@ OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = abs24
    * REGP = [ADDR]  */
 
-  uint32 addr = OP[0];
-  uint32 tmp;
+  uint32_t addr = OP[0];
+  uint32_t tmp;
   trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3300,7 +3300,7 @@ OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rindex + zext24(disp20)
    * REGP = [ADDR]  */
 
-  uint32 addr, tmp;
+  uint32_t addr, tmp;
   trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
 
   if (OP[0] == 0)
@@ -3323,7 +3323,7 @@ OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbase + zext24(disp4)
    * REGP = [ADDR] */
 
-  uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
+  uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
   trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3340,7 +3340,7 @@ OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex
    * REGP = [ADDR]   */
 
-  uint32 addr, tmp;
+  uint32_t addr, tmp;
   trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
 
   if (OP[0] == 0)
@@ -3363,7 +3363,7 @@ OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex + zext24(disp14)
    * REGR = [ADDR]   */
 
-  uint32 addr, tmp;
+  uint32_t addr, tmp;
   trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
 
   if (OP[0] == 0)
@@ -3386,7 +3386,7 @@ OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
    * zext24(Rbase) + zext24(dispe20)
    * REG = [ADDR]   */
 
-  uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+  uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
   trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3403,7 +3403,7 @@ OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = zext24(Rbase) + zext24(disp20)
    * REG = [ADDR]                          */
 
-  uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+  uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
   trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3418,7 +3418,7 @@ OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadd disp16(REGP)   REGP
    * ADDR = RPbase + zext24(disp16)
    * REGR = [ADDR]   */
-  uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+  uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
   trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3434,7 +3434,7 @@ OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
   /* loadd disp20(REGP)   REGP
    * ADDR = RPbase + zext24(disp20)
    * REGP = [ADDR]   */
-  uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+  uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
   trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3450,7 +3450,7 @@ OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(-disp20)
    * REGP = [ADDR]   */
 
-  uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+  uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
   trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
   tmp = RLW (addr);
   tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3466,7 +3466,7 @@ OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbasex + Rindex + zext24(disp20)
    * REGP = [ADDR]   */
 
-  uint32 addr, tmp;
+  uint32_t addr, tmp;
   trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
 
   if (OP[0] == 0)
@@ -3493,8 +3493,8 @@ OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
    * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
    * by the core to 16M-64k to 16M. */
 
-  uint8 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr =  OP[1];
+  uint8_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr =  OP[1];
   trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3508,8 +3508,8 @@ OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = abs24
    * [ADDR] = REGR.  */
 
-  uint8 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr =  OP[1];
+  uint8_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr =  OP[1];
   trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3523,8 +3523,8 @@ OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rindex + zext24(disp20)
    * [ADDR] = REGR  */
 
-  uint32 addr;
-  uint8 a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr;
+  uint8_t a = ((GPR (OP[0])) & 0xff);
   trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -3544,8 +3544,8 @@ OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPBASE + zext24(DISP4)
    * [ADDR]  = REG.  */
 
-  uint16 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3559,8 +3559,8 @@ OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex
    * [ADDR] = REGR   */
 
-  uint32 addr;
-  uint8 a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr;
+  uint8_t a = ((GPR (OP[0])) & 0xff);
   trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
 
   if (OP[1] == 0)
@@ -3580,8 +3580,8 @@ OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = Rpbasex + Rindex + zext24(disp14)
    * [ADDR] = REGR  */
 
-  uint8 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3595,8 +3595,8 @@ OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
    * zext24(Rbase) + zext24(dispe20)
    * [ADDR] = REG  */
 
-  uint8 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr = OP[1] + (GPR (OP[2]));
+  uint8_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr = OP[1] + (GPR (OP[2]));
   trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3610,8 +3610,8 @@ OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = zext24(Rbase) + zext24(disp20)
    * [ADDR] = REG                          */
 
-  uint8 a = (GPR (OP[0]) & 0xff);
-  uint32 addr = OP[1] + (GPR (OP[2]));
+  uint8_t a = (GPR (OP[0]) & 0xff);
+  uint32_t addr = OP[1] + (GPR (OP[2]));
   trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3625,8 +3625,8 @@ OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(disp16)
    * [ADDR] = REGP   */
 
-  uint8 a = ((GPR (OP[0])) & 0xff);
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = ((GPR (OP[0])) & 0xff);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3640,8 +3640,8 @@ OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(disp20)
    * [ADDR] = REGP   */
 
-  uint8 a = ((GPR (OP[0])) & 0xff); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = ((GPR (OP[0])) & 0xff); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3655,8 +3655,8 @@ OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbase + zext24(-disp20)
    * [ADDR] = REGP  */
 
-  uint8 a = (GPR (OP[0]) & 0xff); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (GPR (OP[0]) & 0xff); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3670,8 +3670,8 @@ OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
    * ADDR = RPbasex + Rindex + zext24(disp20)
    * [ADDR] = REGP   */
 
-  uint8 a = (GPR (OP[0])) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (GPR (OP[0])) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3682,8 +3682,8 @@ OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3693,8 +3693,8 @@ OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3704,8 +3704,8 @@ OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint8 a = (OP[0]) & 0xff;
+  uint32_t addr;
+  uint8_t a = (OP[0]) & 0xff;
   trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -3721,8 +3721,8 @@ OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3732,8 +3732,8 @@ OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3743,8 +3743,8 @@ OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3754,8 +3754,8 @@ OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3765,8 +3765,8 @@ OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3776,8 +3776,8 @@ OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (OP[0]) & 0xff;
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint8_t a = (OP[0]) & 0xff;
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   SB (addr, a);
   trace_output_32 (sd, addr);
@@ -3788,8 +3788,8 @@ OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint32 addr =  OP[1];
+  uint16_t a = GPR (OP[0]);
+  uint32_t addr =  OP[1];
   trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3799,8 +3799,8 @@ OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint32 addr =  OP[1];
+  uint16_t a = GPR (OP[0]);
+  uint32_t addr =  OP[1];
   trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3810,8 +3810,8 @@ OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = GPR (OP[0]);
+  uint32_t addr;
+  uint16_t a = GPR (OP[0]);
   trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -3828,8 +3828,8 @@ OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3839,8 +3839,8 @@ OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = GPR (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3850,8 +3850,8 @@ OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = GPR (OP[0]);
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3861,8 +3861,8 @@ OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3872,8 +3872,8 @@ OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3883,8 +3883,8 @@ OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3894,8 +3894,8 @@ OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3905,8 +3905,8 @@ OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3916,8 +3916,8 @@ OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0]));
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = (GPR (OP[0]));
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3928,8 +3928,8 @@ OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3939,8 +3939,8 @@ OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3950,8 +3950,8 @@ OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr;
-  uint16 a = OP[0];
+  uint32_t addr;
+  uint16_t a = OP[0];
   trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -3967,8 +3967,8 @@ OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3978,8 +3978,8 @@ OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -3989,8 +3989,8 @@ OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -4000,8 +4000,8 @@ OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -4012,8 +4012,8 @@ OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -4023,8 +4023,8 @@ OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint16_t a = OP[0];
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
   SW (addr, a);
   trace_output_32 (sd, addr);
@@ -4035,8 +4035,8 @@ OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = OP[1];
   trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4046,8 +4046,8 @@ OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = OP[1];
   trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4057,7 +4057,7 @@ OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr, a = GPR32 (OP[0]); 
+  uint32_t addr, a = GPR32 (OP[0]); 
   trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
 
   if (OP[1] == 0)
@@ -4073,8 +4073,8 @@ OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4084,8 +4084,8 @@ OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4095,8 +4095,8 @@ OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4106,8 +4106,8 @@ OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4117,8 +4117,8 @@ OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4128,8 +4128,8 @@ OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4139,8 +4139,8 @@ OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4150,8 +4150,8 @@ OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4161,8 +4161,8 @@ OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]); 
-  uint32 addr = (GPR32 (OP[2])) + OP[1];
+  uint32_t a = GPR32 (OP[0]); 
+  uint32_t addr = (GPR32 (OP[2])) + OP[1];
   trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
   SLW (addr, a);
   trace_output_32 (sd, addr);
@@ -4172,8 +4172,8 @@ OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int16 src1, src2;
+  int32_t tmp;
+  int16_t src1, src2;
   trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
   src1 = GPR (OP[0]);
   src2 = GPR (OP[1]);
@@ -4187,8 +4187,8 @@ OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
-  uint16 src1, src2;
+  uint32_t tmp;
+  uint16_t src1, src2;
   trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
   src1 = GPR (OP[0]);
   src2 = GPR (OP[1]);
@@ -4202,8 +4202,8 @@ OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int16 src1, src2;
+  int32_t tmp;
+  int16_t src1, src2;
   trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
   src1 = GPR (OP[0]);
   src2 = GPR (OP[1]);
@@ -4218,9 +4218,9 @@ OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp;
-  int8 a = (OP[0]) & 0xff;
-  int8 b = (GPR (OP[1])) & 0xff;
+  int16_t tmp;
+  int8_t a = (OP[0]) & 0xff;
+  int8_t b = (GPR (OP[1])) & 0xff;
   trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
   tmp = (a * b) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4231,8 +4231,8 @@ OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp;
-  int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  int16_t tmp;
+  int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = (a * b) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4244,8 +4244,8 @@ OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp;
-  int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+  int16_t tmp;
+  int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
   tmp = (a * b) & 0xff;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4257,9 +4257,9 @@ OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  uint16 a = OP[0];
-  int16 b = (GPR (OP[1]));
+  int32_t tmp;
+  uint16_t a = OP[0];
+  int16_t b = (GPR (OP[1]));
   trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
   tmp = (a * b) & 0xffff;
   SET_GPR (OP[1], tmp);
@@ -4270,8 +4270,8 @@ OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int16 a = OP[0], b = (GPR (OP[1]));
+  int32_t tmp;
+  int16_t a = OP[0], b = (GPR (OP[1]));
   trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = (a * b) & 0xffff;
   SET_GPR (OP[1], tmp);
@@ -4283,8 +4283,8 @@ OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+  int32_t tmp;
+  int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
   tmp = (a * b) & 0xffff;
   SET_GPR (OP[1], tmp);
@@ -4296,8 +4296,8 @@ OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp;
-  int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+  int16_t tmp;
+  int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
   tmp = a * b;
   SET_GPR (OP[1], tmp);
@@ -4308,8 +4308,8 @@ OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp; 
-  int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+  int32_t tmp; 
+  int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
   tmp = a * b;
   SET_GPR32 (OP[1], tmp);
@@ -4320,8 +4320,8 @@ OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
-  uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+  uint32_t tmp;
+  uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
   tmp = a * b;
   SET_GPR32 (OP[1], tmp);
@@ -4354,7 +4354,7 @@ OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4365,7 +4365,7 @@ OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4376,7 +4376,7 @@ OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("orb", OP_REG, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4387,7 +4387,7 @@ OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+  uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
   trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], tmp);
@@ -4399,7 +4399,7 @@ OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+  uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
   trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], tmp);
@@ -4410,7 +4410,7 @@ OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+  uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("orw", OP_REG, OP_REG, OP_VOID);
   tmp = a | b;
   SET_GPR (OP[1], tmp);
@@ -4422,8 +4422,8 @@ OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+  uint16_t a = OP[0];
+  uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
   trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4442,8 +4442,8 @@ OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0])) & 0xff;
-  uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+  uint16_t a = (GPR (OP[0])) & 0xff;
+  uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
   trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
   if (a & ((long)1 << 3))
     {
@@ -4468,8 +4468,8 @@ OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, b = GPR (OP[1]);
-  int16 a = GPR (OP[0]);
+  uint16_t tmp, b = GPR (OP[1]);
+  int16_t a = GPR (OP[0]);
   trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
   if (a & ((long)1 << 4))
     {
@@ -4494,8 +4494,8 @@ OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, b = GPR (OP[1]);
-  uint16 a = OP[0];
+  uint16_t tmp, b = GPR (OP[1]);
+  uint16_t a = OP[0];
   trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4513,8 +4513,8 @@ OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, b = GPR32 (OP[1]);
-  uint16 a = OP[0];
+  uint32_t tmp, b = GPR32 (OP[1]);
+  uint16_t a = OP[0];
   trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4533,8 +4533,8 @@ OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp, b = GPR32 (OP[1]);
-  uint16 a = GPR (OP[0]);
+  uint32_t tmp, b = GPR32 (OP[1]);
+  uint16_t a = GPR (OP[0]);
   trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
   if (a & ((long)1 << 5))
     {
@@ -4559,8 +4559,8 @@ OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0]; 
-  int8 tmp, b = (GPR (OP[1])) & 0xFF;
+  uint16_t a = OP[0]; 
+  int8_t tmp, b = (GPR (OP[1])) & 0xFF;
   trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4579,8 +4579,8 @@ OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0]; 
-  int8 tmp, b = (GPR (OP[1])) & 0xFF;
+  uint16_t a = OP[0]; 
+  int8_t tmp, b = (GPR (OP[1])) & 0xFF;
   trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4600,8 +4600,8 @@ OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = (GPR (OP[0]));
-  int8 tmp, b = (GPR (OP[1])) & 0xFF;
+  int16_t a = (GPR (OP[0]));
+  int8_t tmp, b = (GPR (OP[1])) & 0xFF;
   trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
 
   if (a & ((long)1 << 3))
@@ -4629,8 +4629,8 @@ OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp, b = GPR (OP[1]);
-  uint16 a = OP[0];
+  int16_t tmp, b = GPR (OP[1]);
+  uint16_t a = OP[0];
   trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4649,8 +4649,8 @@ OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp, b = GPR (OP[1]);
-  uint16 a = OP[0];
+  int16_t tmp, b = GPR (OP[1]);
+  uint16_t a = OP[0];
   trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4668,8 +4668,8 @@ OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 tmp;
-  int16 a = GPR (OP[0]), b = GPR (OP[1]);
+  int16_t tmp;
+  int16_t a = GPR (OP[0]), b = GPR (OP[1]);
   trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
 
   if (a & ((long)1 << 4))
@@ -4695,8 +4695,8 @@ OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp,b = GPR32 (OP[1]);
-  uint32 a = OP[0];
+  int32_t tmp,b = GPR32 (OP[1]);
+  uint32_t a = OP[0];
   trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4714,8 +4714,8 @@ OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int32 a = OP[0], b = GPR32 (OP[1]);
+  int32_t tmp;
+  int32_t a = OP[0], b = GPR32 (OP[1]);
   trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
   /* A positive count specifies a shift to the left;
    * A negative count specifies a shift to the right. */
@@ -4733,8 +4733,8 @@ OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 tmp;
-  int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+  int32_t tmp;
+  int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
   trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
 
   if (a & ((long)1 << 5))
@@ -4760,8 +4760,8 @@ OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr = GPR (1);
-  uint16 count = OP[0], reg = 2;
+  uint32_t addr = GPR (1);
+  uint16_t count = OP[0], reg = 2;
   trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
   if ((addr & 1))
     {
@@ -4788,8 +4788,8 @@ OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 addr = GPR32 (6);
-  uint16 count = OP[0], reg = 2;
+  uint32_t addr = GPR32 (6);
+  uint16_t count = OP[0], reg = 2;
   trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
   if ((addr & 1))
     {
@@ -4814,9 +4814,9 @@ OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0];
-  uint8 b = (GPR (OP[1])) & 0xff;
-  uint16 tmp = (~a + 1 + b) & 0xff;
+  uint8_t a = OP[0];
+  uint8_t b = (GPR (OP[1])) & 0xff;
+  uint16_t tmp = (~a + 1 + b) & 0xff;
   trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4830,9 +4830,9 @@ OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0] & 0xFF;
-  uint8 b = (GPR (OP[1])) & 0xFF;
-  uint16 tmp = (~a + 1 + b) & 0xFF;
+  uint8_t a = OP[0] & 0xFF;
+  uint8_t b = (GPR (OP[1])) & 0xFF;
+  uint16_t tmp = (~a + 1 + b) & 0xFF;
   trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4846,9 +4846,9 @@ OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = (GPR (OP[0])) & 0xFF;
-  uint8 b = (GPR (OP[1])) & 0xFF;
-  uint16 tmp = (~a + 1 + b) & 0xff;
+  uint8_t a = (GPR (OP[0])) & 0xFF;
+  uint8_t b = (GPR (OP[1])) & 0xFF;
+  uint16_t tmp = (~a + 1 + b) & 0xff;
   trace_input ("subb", OP_REG, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4862,9 +4862,9 @@ OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp = (~a + 1 + b);
+  uint16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp = (~a + 1 + b);
   trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4878,9 +4878,9 @@ OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint32 tmp = (~a + 1 + b);
+  uint16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint32_t tmp = (~a + 1 + b);
   trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4894,9 +4894,9 @@ OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
-  uint16 b = GPR (OP[1]);
-  uint32 tmp = (~a + 1 + b);
+  uint16_t a = GPR (OP[0]);
+  uint16_t b = GPR (OP[1]);
+  uint32_t tmp = (~a + 1 + b);
   trace_input ("subw", OP_REG, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4910,11 +4910,11 @@ OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 a = OP[0];
-  uint8 b = (GPR (OP[1])) & 0xff;
-  //uint16 tmp1 = a + 1;
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1 + b);
+  uint8_t a = OP[0];
+  uint8_t b = (GPR (OP[1])) & 0xff;
+  //uint16_t tmp1 = a + 1;
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1 + b);
   trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4928,11 +4928,11 @@ OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0];
-  uint16 b = (GPR (OP[1])) & 0xff;
-  //uint16 tmp1 = a + 1;
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1 + b);
+  uint16_t a = OP[0];
+  uint16_t b = (GPR (OP[1])) & 0xff;
+  //uint16_t tmp1 = a + 1;
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1 + b);
   trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4946,10 +4946,10 @@ OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0])) & 0xff;
-  uint16 b = (GPR (OP[1])) & 0xff;
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1 + b);
+  uint16_t a = (GPR (OP[0])) & 0xff;
+  uint16_t b = (GPR (OP[1])) & 0xff;
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1 + b);
   trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4963,9 +4963,9 @@ OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0], b = (GPR (OP[1]));
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1  + b);
+  uint16_t a = OP[0], b = (GPR (OP[1]));
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1  + b);
   trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4979,10 +4979,10 @@ OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int16 a = OP[0];
-  uint16 b = GPR (OP[1]);
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1  + b);
+  int16_t a = OP[0];
+  uint16_t b = GPR (OP[1]);
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1  + b);
   trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -4996,9 +4996,9 @@ OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
-  uint16 tmp1 = a + (PSR_C);
-  uint16 tmp = (~tmp1 + 1  + b);
+  uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
+  uint16_t tmp1 = a + (PSR_C);
+  uint16_t tmp = (~tmp1 + 1  + b);
   trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -5012,9 +5012,9 @@ OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  int32 a = OP[0];
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp = (~a + 1 + b);
+  int32_t a = OP[0];
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp = (~a + 1 + b);
   trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -5029,9 +5029,9 @@ OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]);
-  uint32 b = GPR32 (OP[1]);
-  uint32 tmp = (~a + 1 + b);
+  uint32_t a = GPR32 (OP[0]);
+  uint32_t b = GPR32 (OP[1]);
+  uint32_t tmp = (~a + 1 + b);
   trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
   /* see ../common/sim-alu.h for a more extensive discussion on how to
      compute the carry/overflow bits. */
@@ -5047,8 +5047,8 @@ void
 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
 {
   host_callback *cb = STATE_CALLBACK (sd);
-  uint32 tmp;
-  uint16 a;
+  uint32_t tmp;
+  uint16_t a;
   trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
   switch (OP[0])
     {
@@ -5056,7 +5056,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
 #if (DEBUG & DEBUG_TRAP) == 0
       {
 #if 0
-	uint16 vec = OP[0] + TRAP_VECTOR_START;
+	uint16_t vec = OP[0] + TRAP_VECTOR_START;
 	SET_BPC (PC + 1);
 	SET_BPSR (PSR);
 	SET_PSR (PSR & PSR_SM_BIT);
@@ -5097,7 +5097,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
     case 8:			/* new system call trap */
       /* Trap 8 is used for simulating low-level I/O */
       {
-	unsigned32 result = 0;
+	uint32_t result = 0;
 	errno = 0;
 
 /* Registers passed to trap 0.  */
@@ -5284,7 +5284,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
 	      buf = PARM1;
 	      RETVAL (pipe (host_fd));
 	      SW (buf, host_fd[0]);
-	      buf += sizeof(uint16);
+	      buf += sizeof(uint16_t);
 	      SW (buf, host_fd[1]);
 	      trace_output_16 (sd, result);
 	    }
@@ -5449,7 +5449,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
 		break;
 	    }
 	  }
-	if ((uint16) result == (uint16) -1)
+	if ((uint16_t) result == (uint16_t) -1)
 	  RETERR (cb->get_errno (cb));
 	else
 	  RETERR (0);
@@ -5463,8 +5463,8 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
-  uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
+  uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+  uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
   trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
 
   for (; i < a; ++i)
@@ -5512,8 +5512,8 @@ OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 sp_addr, tmp, is_regp = 0;
-  uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+  uint32_t sp_addr, tmp, is_regp = 0;
+  uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
   trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
 
   if (c == 1)
@@ -5570,7 +5570,7 @@ OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 sp_addr = (GPR32 (15)), tmp;
+  uint32_t sp_addr = (GPR32 (15)), tmp;
   trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
   tmp = (GPR32 (14)); 
   SLW(sp_addr-4,tmp);                /* Store RA address.   */
@@ -5583,8 +5583,8 @@ OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
-  uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
+  uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+  uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
   trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
 
   for (; i < a; ++i)
@@ -5636,8 +5636,8 @@ OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
-  uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
+  uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+  uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
   trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
 
   for (; i < a; ++i)
@@ -5690,8 +5690,8 @@ OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 sp_addr = GPR32 (15);
-  uint32 tmp;
+  uint32_t sp_addr = GPR32 (15);
+  uint32_t tmp;
   trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
 
   tmp =  RLW(sp_addr); 
@@ -5705,7 +5705,7 @@ OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0], b = OP[1];
+  uint16_t a = OP[0], b = OP[1];
   trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
   OP_5_9 (sd, cpu);
   JMP(((GPR32(14)) << 1) & 0xffffff);
@@ -5717,7 +5717,7 @@ OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = OP[0], b = OP[1];
+  uint16_t a = OP[0], b = OP[1];
   trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
   OP_2_8 (sd, cpu);
   JMP(((GPR32(14)) << 1) & 0xffffff);
@@ -5729,7 +5729,7 @@ OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 tmp;
+  uint32_t tmp;
   trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
   OP_21E_10 (sd, cpu);
   tmp = (((GPR32(14)) << 1) & 0xffffff);
@@ -5851,7 +5851,7 @@ OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5862,7 +5862,7 @@ OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5873,7 +5873,7 @@ OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+  uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
   trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5884,7 +5884,7 @@ OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+  uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
   trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], tmp);
@@ -5895,7 +5895,7 @@ OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+  uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
   trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], tmp);
@@ -5906,7 +5906,7 @@ OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+  uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
   trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
   tmp = a ^ b;
   SET_GPR (OP[1], tmp);
@@ -5919,7 +5919,7 @@ OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = GPR (OP[0]);
+  uint16_t a = GPR (OP[0]);
   trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
   SET_CREG (OP[1], a);
   trace_output_16 (sd, a);
@@ -5929,7 +5929,7 @@ OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = GPR32 (OP[0]);
+  uint32_t a = GPR32 (OP[0]);
   trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
   SET_CREG (OP[1], a);
   trace_output_flag (sd);
@@ -5939,7 +5939,7 @@ OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint16 a = CREG (OP[0]);
+  uint16_t a = CREG (OP[0]);
   trace_input ("spr", OP_REG, OP_REG, OP_VOID);
   SET_GPR (OP[1], a);
   trace_output_16 (sd, a);
@@ -5949,7 +5949,7 @@ OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
 void
 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
 {
-  uint32 a = CREG (OP[0]);
+  uint32_t a = CREG (OP[0]);
   trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
   SET_GPR32 (OP[1], a);
   trace_output_32 (sd, a);