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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-27 13:33:51 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-14 05:21:41 +0000 |
| commit | 3009ffe06c8ede5fbb7c9d37dfc731ce2c8fdf45 (patch) | |
| tree | 11d3fe8d2fe223c8b7dedc4d17c1b9d5126693ea | |
| parent | 354c1c098abe2b5cbc9da9751d29c5e5a0072376 (diff) | |
| download | gdb-3009ffe06c8ede5fbb7c9d37dfc731ce2c8fdf45.zip gdb-3009ffe06c8ede5fbb7c9d37dfc731ce2c8fdf45.tar.gz gdb-3009ffe06c8ede5fbb7c9d37dfc731ce2c8fdf45.tar.bz2 | |
opcodes/riscv-dis.c: Make XLEN variable static
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
Since xlen variable is not (and should not) used outside riscv-dis.c,
this commit makes this variable static.
opcodes/ChangeLog:
* riscv-dis.c (xlen): Make this variable static.
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 608670b..27e1978 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -33,7 +33,7 @@ #include <ctype.h> /* Current XLEN for the disassembler. */ -unsigned xlen = 0; +static unsigned xlen = 0; /* Default ISA specification version (constant as of now). */ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; |