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author | Jan Beulich <jbeulich@suse.com> | 2021-06-15 08:00:45 +0200 |
---|---|---|
committer | Jan Beulich <jbeulich@suse.com> | 2021-06-15 08:00:45 +0200 |
commit | 2f2be86bbb8d26f780183e45b169748ef625f03d (patch) | |
tree | 43118b9e088c86ed84e75c447dbbd1a1a85fcc8f | |
parent | 649658972ca923250019ca15e4ddd98bf28bf123 (diff) | |
download | gdb-2f2be86bbb8d26f780183e45b169748ef625f03d.zip gdb-2f2be86bbb8d26f780183e45b169748ef625f03d.tar.gz gdb-2f2be86bbb8d26f780183e45b169748ef625f03d.tar.bz2 |
x86: simplify .dispNN setting
First of all eliminate the disp{16,32,32s} static variables, which are
used solely for setting a temporary variable in build_modrm_byte(). The
effect there can be had without use of such a temporary and without
operand_type_or(), by just setting the single bit each that needs
setting.
Then use operand_type_and_not(..., anydisp) when all dispNN bits want
clearing together.
-rw-r--r-- | gas/ChangeLog | 7 | ||||
-rw-r--r-- | gas/config/tc-i386.c | 68 |
2 files changed, 24 insertions, 51 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7699447..d01ba23 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2021-06-15 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (disp16, disp32, disp32s): Delete. + (optimize_disp, i386_finalize_displacement): Use + operand_type_and_not. + (build_modrm_byte): Likewise. Eliminate local variable newdisp. + +2021-06-15 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (offset_in_range): Bail early when mask would cover all bits anyway. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 945a1a69..18187d7 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2089,9 +2089,6 @@ operand_type_xor (i386_operand_type x, i386_operand_type y) return x; } -static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; -static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; -static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; @@ -5884,12 +5881,8 @@ optimize_disp (void) if (!op_disp && i.types[op].bitfield.baseindex) { - i.types[op].bitfield.disp8 = 0; - i.types[op].bitfield.disp16 = 0; - i.types[op].bitfield.disp32 = 0; - i.types[op].bitfield.disp32s = 0; - i.types[op].bitfield.disp64 = 0; - i.op[op].disps = 0; + i.types[op] = operand_type_and_not (i.types[op], anydisp); + i.op[op].disps = NULL; i.disp_operands--; continue; } @@ -5938,11 +5931,7 @@ optimize_disp (void) { fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, i.op[op].disps, 0, i.reloc[op]); - i.types[op].bitfield.disp8 = 0; - i.types[op].bitfield.disp16 = 0; - i.types[op].bitfield.disp32 = 0; - i.types[op].bitfield.disp32s = 0; - i.types[op].bitfield.disp64 = 0; + i.types[op] = operand_type_and_not (i.types[op], anydisp); } else /* We only support 64bit displacement on constants. */ @@ -8261,20 +8250,11 @@ build_modrm_byte (void) { i.sib.base = NO_BASE_REGISTER; i.sib.scale = i.log2_scale_factor; - i.types[op].bitfield.disp8 = 0; - i.types[op].bitfield.disp16 = 0; - i.types[op].bitfield.disp64 = 0; + i.types[op] = operand_type_and_not (i.types[op], anydisp); if (want_disp32 (&i.tm)) - { - /* Must be 32 bit */ - i.types[op].bitfield.disp32 = 1; - i.types[op].bitfield.disp32s = 0; - } + i.types[op].bitfield.disp32 = 1; else - { - i.types[op].bitfield.disp32 = 0; - i.types[op].bitfield.disp32s = 1; - } + i.types[op].bitfield.disp32s = 1; } /* Since the mandatory SIB always has index register, so @@ -8300,12 +8280,11 @@ build_modrm_byte (void) fake_zero_displacement = 1; if (i.index_reg == 0) { - i386_operand_type newdisp; - /* Both check for VSIB and mandatory non-vector SIB. */ gas_assert (!i.tm.opcode_modifier.sib || i.tm.opcode_modifier.sib == SIBMEM); /* Operand is just <disp> */ + i.types[op] = operand_type_and_not (i.types[op], anydisp); if (flag_code == CODE_64BIT) { /* 64bit mode overwrites the 32bit absolute @@ -8315,21 +8294,22 @@ build_modrm_byte (void) i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; i.sib.base = NO_BASE_REGISTER; i.sib.index = NO_INDEX_REGISTER; - newdisp = (want_disp32(&i.tm) ? disp32 : disp32s); + if (want_disp32 (&i.tm)) + i.types[op].bitfield.disp32 = 1; + else + i.types[op].bitfield.disp32s = 1; } else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) { i.rm.regmem = NO_BASE_REGISTER_16; - newdisp = disp16; + i.types[op].bitfield.disp16 = 1; } else { i.rm.regmem = NO_BASE_REGISTER; - newdisp = disp32; + i.types[op].bitfield.disp32 = 1; } - i.types[op] = operand_type_and_not (i.types[op], anydisp); - i.types[op] = operand_type_or (i.types[op], newdisp); } else if (!i.tm.opcode_modifier.sib) { @@ -8341,20 +8321,11 @@ build_modrm_byte (void) i.sib.base = NO_BASE_REGISTER; i.sib.scale = i.log2_scale_factor; i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; - i.types[op].bitfield.disp8 = 0; - i.types[op].bitfield.disp16 = 0; - i.types[op].bitfield.disp64 = 0; + i.types[op] = operand_type_and_not (i.types[op], anydisp); if (want_disp32 (&i.tm)) - { - /* Must be 32 bit */ - i.types[op].bitfield.disp32 = 1; - i.types[op].bitfield.disp32s = 0; - } + i.types[op].bitfield.disp32 = 1; else - { - i.types[op].bitfield.disp32 = 0; - i.types[op].bitfield.disp32s = 1; - } + i.types[op].bitfield.disp32s = 1; if ((i.index_reg->reg_flags & RegRex) != 0) i.rex |= REX_X; } @@ -11045,12 +11016,7 @@ i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, i.types[this_operand].bitfield.disp8 = 1; /* Check if this is a displacement only operand. */ - bigdisp = i.types[this_operand]; - bigdisp.bitfield.disp8 = 0; - bigdisp.bitfield.disp16 = 0; - bigdisp.bitfield.disp32 = 0; - bigdisp.bitfield.disp32s = 0; - bigdisp.bitfield.disp64 = 0; + bigdisp = operand_type_and_not (i.types[this_operand], anydisp); if (operand_type_all_zero (&bigdisp)) i.types[this_operand] = operand_type_and (i.types[this_operand], types); |