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authorVictor Do Nascimento <victor.donascimento@arm.com>2023-11-15 13:48:59 +0000
committerVictor Do Nascimento <victor.donascimento@arm.com>2024-01-09 10:16:40 +0000
commit2ec6065a4f3fe95d287602cb9158a7ce1fbed2e9 (patch)
tree6eafa4f4b744872bf4180b6a7109ccf57d9d9e85
parent7b08cc32165912395838e7bb995d880f623fe636 (diff)
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aarch64: Expand maximum number of operands from 5 to 6
Given the introduction of the new Armv9.4-a `sysp' insn using the following syntax: sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} and by extension the need to encode 6 assembly operands, extend Binutils to handle instructions taking 6 operands, up from a previous maximum of 5.
-rw-r--r--include/opcode/aarch64.h2
-rw-r--r--opcodes/aarch64-tbl.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7b7b15a..554e4e1 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1075,7 +1075,7 @@ enum err_type
};
/* Maximum number of operands an instruction can have. */
-#define AARCH64_MAX_OPND_NUM 6
+#define AARCH64_MAX_OPND_NUM 7
/* Maximum number of qualifier sequences an instruction can have. */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 27550fd..47c25d5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -34,6 +34,7 @@
#define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
#define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
#define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
+#define OP6(a,b,c,d,e,f) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e), OPND(f)}
#define QLF(x) AARCH64_OPND_QLF_##x
#define QLF1(a) {QLF(a)}
@@ -41,6 +42,7 @@
#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
+#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)}
/* Qualifiers list. */