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| author | Jeff Law <law@redhat.com> | 1997-05-16 22:37:02 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1997-05-16 22:37:02 +0000 |
| commit | 234a9a49cf20a2eecf9b990e4a18a5fe9e6c681d (patch) | |
| tree | 59a2991e57a6a405c3227f4e78c11eeb8763eb80 | |
| parent | efc02f6657b1dc6a8d9eb92975fffbfcaf2cea02 (diff) | |
| download | gdb-234a9a49cf20a2eecf9b990e4a18a5fe9e6c681d.zip gdb-234a9a49cf20a2eecf9b990e4a18a5fe9e6c681d.tar.gz gdb-234a9a49cf20a2eecf9b990e4a18a5fe9e6c681d.tar.bz2 | |
* interp.c (load_mem): If we get a load from an out of range
address, abort.
(store_mem): Likewise for stores.
(max_mem): New variable.
| -rw-r--r-- | sim/mn10300/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/mn10300/interp.c | 11 |
2 files changed, 18 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 51efa7b..50db974 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,10 @@ +Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (load_mem): If we get a load from an out of range + address, abort. + (store_mem): Likewise for stores. + (max_mem): New variable. + Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com) * mn10300_sim.h: Fix ordering of bits in the PSW. diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index 711356f..1a14039 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -33,6 +33,7 @@ struct hash_entry #endif }; +static int max_mem = 0; struct hash_entry hash_table[MAX_HASH+1]; @@ -241,6 +242,9 @@ load_mem_big (addr, len) { uint8 *p = addr + State.mem; + if (addr > max_mem) + abort (); + switch (len) { case 1: @@ -263,6 +267,9 @@ load_mem (addr, len) { uint8 *p = addr + State.mem; + if (addr > max_mem) + abort (); + switch (len) { case 1: @@ -286,6 +293,9 @@ store_mem (addr, len, data) { uint8 *p = addr + State.mem; + if (addr > max_mem) + abort (); + switch (len) { case 1: @@ -314,6 +324,7 @@ sim_size (power) if (State.mem) free (State.mem); + max_mem = 1 << power; State.mem = (uint8 *) calloc (1, 1 << power); if (!State.mem) { |