Modify the ARNM assembler to accept the omission of the immediate argument for the writeback form of the LDRAA and LDRAB mnemonics

This is a shorthand for the immediate argument being 0, as described here:
  https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication

This is because the instructions still have a use with an immediate
argument of 0, unlike loads without the PAC functionality. Currently,
the mnemonics are

  LDRAA Xt, [Xn, #<simm10>]!
  LDRAB Xt, [Xn, #<simm10>]!

After this patch they become

  LDRAA Xt, [Xn {, #<simm10>}]!
  LDRAB Xt, [Xn {, #<simm10>}]!

gas	* config/tc-aarch64.c (parse_address_main): Accept the omission of
	the immediate argument for ldraa and ldrab as a shorthand for the
	immediate being 0.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
	* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
	writeback form with no offset.
	* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
	error.

opcodes	* aarch64-opc.c (print_immediate_offset_address): Don't print the
	immediate for the writeback form of ldraa/ldrab if it is 0.
	* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
	* aarch64-opc-2.c: Regenerated.

10 files changed, 101 insertions, 47 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bd080bf..84a3a9a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2019-10-30  Delia Burduv  <Delia.Burduv@arm.com>
+
+	* config/tc-aarch64.c (parse_address_main): Accept the omission of
+	the immediate argument for ldraa and ldrab as a shorthand for the
+	immediate being 0.
+	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
+	* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
+	* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
+	writeback form with no offset.
+	* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
+	error.
+
 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 
 	* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.s,
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 522efeb..b4ee062 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3402,6 +3402,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
      [base,Xm,SXTX {#imm}]
      [base,Wm,(S|U)XTW {#imm}]
    Pre-indexed
+     [base]!                    // in ldraa/ldrab exclusive
      [base,#imm]!
    Post-indexed
      [base],#imm
@@ -3716,29 +3717,42 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
     }
 
   /* If at this point neither .preind nor .postind is set, we have a
-     bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].
+     bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
+     ldrab, accept [Rn] as a shorthand for [Rn,#0].
      For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
      [Zn.<T>, xzr].  */
   if (operand->addr.preind == 0 && operand->addr.postind == 0)
     {
       if (operand->addr.writeback)
 	{
-	  /* Reject [Rn]!   */
-	  set_syntax_error (_("missing offset in the pre-indexed address"));
-	  return FALSE;
+	  if (operand->type == AARCH64_OPND_ADDR_SIMM10)
+            {
+              /* Accept [Rn]! as a shorthand for [Rn,#0]!   */
+              operand->addr.offset.is_reg = 0;
+              operand->addr.offset.imm = 0;
+              operand->addr.preind = 1;
+            }
+          else
+           {
+	     /* Reject [Rn]!   */
+	     set_syntax_error (_("missing offset in the pre-indexed address"));
+	     return FALSE;
+	   }
 	}
-
-      operand->addr.preind = 1;
-      if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
-	{
-	  operand->addr.offset.is_reg = 1;
-	  operand->addr.offset.regno = REG_ZR;
-	  *offset_qualifier = AARCH64_OPND_QLF_X;
-	}
-      else
+       else
 	{
-	  inst.reloc.exp.X_op = O_constant;
-	  inst.reloc.exp.X_add_number = 0;
+          operand->addr.preind = 1;
+          if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
+	   {
+	     operand->addr.offset.is_reg = 1;
+	     operand->addr.offset.regno = REG_ZR;
+	     *offset_qualifier = AARCH64_OPND_QLF_X;
+ 	   }
+          else
+	   {
+	     inst.reloc.exp.X_op = O_constant;
+	     inst.reloc.exp.X_add_number = 0;
+	   }
 	}
     }
 
diff --git a/gas/testsuite/gas/aarch64/illegal-ldraa.l b/gas/testsuite/gas/aarch64/illegal-ldraa.l
index e3f81c5..33fae2f 100644
--- a/gas/testsuite/gas/aarch64/illegal-ldraa.l
+++ b/gas/testsuite/gas/aarch64/illegal-ldraa.l
@@ -6,30 +6,28 @@
 [^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]'
 [^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]'
 [^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
-[^:]+:16: Error: missing offset in the pre-indexed address at operand 2 -- `ldraa x0,\[x1\]!'
-[^:]+:17: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
-[^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
-[^:]+:19: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
-[^:]+:20: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#-10\]!'
-[^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!'
-[^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!'
-[^:]+:23: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!'
-[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
-[^:]+:25: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8'
-[^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]'
-[^:]+:29: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]'
-[^:]+:30: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]'
-[^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]'
-[^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
-[^:]+:33: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
-[^:]+:34: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
-[^:]+:35: Error: missing offset in the pre-indexed address at operand 2 -- `ldrab x0,\[x1\]!'
-[^:]+:36: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
-[^:]+:37: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
-[^:]+:38: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
-[^:]+:39: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]!'
-[^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!'
-[^:]+:41: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!'
-[^:]+:42: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!'
-[^:]+:43: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
-[^:]+:44: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8'
+[^:]+:16: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
+[^:]+:17: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
+[^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
+[^:]+:19: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#-10\]!'
+[^:]+:20: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!'
+[^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!'
+[^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!'
+[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
+[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8'
+[^:]+:27: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]'
+[^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]'
+[^:]+:29: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]'
+[^:]+:30: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]'
+[^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
+[^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
+[^:]+:33: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
+[^:]+:34: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
+[^:]+:35: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
+[^:]+:36: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
+[^:]+:37: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]!'
+[^:]+:38: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!'
+[^:]+:39: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!'
+[^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!'
+[^:]+:41: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
+[^:]+:42: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8'
diff --git a/gas/testsuite/gas/aarch64/illegal-ldraa.s b/gas/testsuite/gas/aarch64/illegal-ldraa.s
index 93a8cf5..3e6ebf5 100644
--- a/gas/testsuite/gas/aarch64/illegal-ldraa.s
+++ b/gas/testsuite/gas/aarch64/illegal-ldraa.s
@@ -13,7 +13,6 @@
 	ldraa x0, [x1,#5555]
 	ldraa x0, [x1,#-4104]
 	ldraa x0, [xz]
-	ldraa x0, [x1]!
 	ldraa x0, [sp],
 	ldraa x0, [x1,#1]!
 	ldraa x0, [x1,#4]!
@@ -32,7 +31,6 @@
 	ldrab x0, [x1,#5555]
 	ldrab x0, [x1,#-4104]
 	ldrab x0, [xz]
-	ldrab x0, [x1]!
 	ldrab x0, [sp],
 	ldrab x0, [x1,#1]!
 	ldrab x0, [x1,#4]!
diff --git a/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.d b/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.d
new file mode 100644
index 0000000..4146f76
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.d
@@ -0,0 +1,13 @@
+#as: -march=armv8.3-a
+#objdump: -dr
+
+.*: .*
+
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	f8200c01 	ldraa	x1, \[x0]!
+.*:	f8a00c02 	ldrab	x2, \[x0]!
+.*:	f8200c01 	ldraa	x1, \[x0]!
+.*:	f8a00c02 	ldrab	x2, \[x0]!
diff --git a/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.s b/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.s
new file mode 100644
index 0000000..d0694c90
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ldraa-ldrab-no-offset.s
@@ -0,0 +1,7 @@
+.text
+
+	ldraa   x1, [x0]!
+	ldrab   x2, [x0]!
+
+	ldraa   x1, [x0, #0]!
+	ldrab   x2, [x0, #0]!
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dc22f41..d88aee3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-10-30  Delia Burduv   <delia.burduv@arm.com>
+
+	* aarch64-opc.c (print_immediate_offset_address): Don't print the
+	immediate for the writeback form of ldraa/ldrab if it is 0.
+	* aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
+	* aarch64-opc-2.c: Regenerated.
+
 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-gen.c (operand_type_shorthands): Delete.
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 178d210..53d5946 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -112,7 +112,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
-  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with an optional 10-bit scaled, signed immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 2e205e5..992a2af 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3063,7 +3063,12 @@ print_immediate_offset_address (char *buf, size_t size,
   if (opnd->addr.writeback)
     {
       if (opnd->addr.preind)
-	snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        {
+	  if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
+            snprintf (buf, size, "[%s]!", base);
+          else
+	    snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        }
       else
 	snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
     }
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ee36f1c..00168dd 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5141,7 +5141,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index),	\
       "an address with 9-bit negative or unaligned immediate offset")	\
     Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
-      "an address with 10-bit scaled, signed immediate offset")		\
+      "an address with an optional 10-bit scaled, signed immediate offset")		\
     Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\
       "an address with 11-bit signed immediate (multiple of 16) offset")\
     Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12),	\