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authorYvan Roux <yvan.roux@foss.st.com>2022-06-09 16:31:40 +0200
committerYvan Roux <yvan.roux@foss.st.com>2022-06-09 16:31:40 +0200
commit148ca9dd5cf96049c0db17c1230e4b96c0ac054a (patch)
treec47d4a7070afc733af80299192a4abb6dc74ee5d
parent575a212a78c6f7e213933cf96d9a63642edc5069 (diff)
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gdb/arm: Terminate unwinding when LR is 0xffffffff
ARMv7-M Architecture Reference "A2.3.1 Arm core registers" states that LR is set to 0xffffffff on reset. ARMv8-M Architecture Reference "B3.3 Registers" states that LR is set to 0xffffffff on warm reset if Main Extension is implemented, otherwise the value is unknown. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@st.com> Signed-off-by: Yvan Roux <yvan.roux@foss.st.com>
-rw-r--r--gdb/arm-tdep.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 591a2da..09670b6 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3330,6 +3330,17 @@ arm_m_exception_cache (struct frame_info *this_frame)
lr = get_frame_register_unsigned (this_frame, ARM_LR_REGNUM);
sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
+ /* ARMv7-M Architecture Reference "A2.3.1 Arm core registers"
+ states that LR is set to 0xffffffff on reset. ARMv8-M Architecture
+ Reference "B3.3 Registers" states that LR is set to 0xffffffff on warm
+ reset if Main Extension is implemented, otherwise the value is unknown. */
+ if (lr == 0xffffffff)
+ {
+ /* Terminate any further stack unwinding by referring to self. */
+ arm_cache_set_active_sp_value (cache, tdep, sp);
+ return cache;
+ }
+
fnc_return = ((lr & 0xfffffffe) == 0xfefffffe);
if (tdep->have_sec_ext && fnc_return)
{