[ARC] Add arithmetic and logic instructions for nps

This commit completes the implementation of arithmetic and logic
instructions for the NPS-400. These instructions are:

- calcbsd / calcbxd
- calckey / calcxkey
- mxb / imxb
- addl, subl, orl, andl, xorl
- andab / orab
- lbdsize
- bdlen
- csms, csma, cbba
- zncv
- hofs

6 files changed, 582 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5bc1de7..af4e9c9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-13  Graham Markall <graham.markall@embecosm.com>
+
+	* testsuite/gas/arc/nps400-6.s: Add tests of calcbsd, calcbxd,
+	calckey, calcxkey, mxb, imxb, addl, subl, andl, orl, xorl, andab, orab,
+	lbdsize, bdlen, csms, csma, cbba, zncv, and hofs.
+	* testsuite/gas/arc/nps400-6.d: Likewise.
+
 2016-06-14  Nick Clifton  <nickc@redhat.com>
 
 	* config/tc-nds32.c (nds32_get_align): Avoid left shifting a
diff --git a/gas/testsuite/gas/arc/nps400-6.d b/gas/testsuite/gas/arc/nps400-6.d
index 3292177..6a67461 100644
--- a/gas/testsuite/gas/arc/nps400-6.d
+++ b/gas/testsuite/gas/arc/nps400-6.d
@@ -68,3 +68,164 @@ Disassembly of section .text:
   ec:	4820 4610           	calcxd	r0,r0,r1,0x40
   f0:	4a10 4710           	calcxd.f	r2,r2,r0,0x80
   f4:	4940 4810           	calcxd	r1,r1,r2,0x100
+  f8:	4800 0030           	calcbsd	r0,r0,r0
+  fc:	4910 0030           	calcbsd.f	r1,r1,r0
+ 100:	4940 0030           	calcbsd	r1,r1,r2
+ 104:	4b50 0030           	calcbsd.f	r3,r3,r2
+ 108:	4800 4030           	calcbxd	r0,r0,r0
+ 10c:	4910 4030           	calcbxd.f	r1,r1,r0
+ 110:	4940 4030           	calcbxd	r1,r1,r2
+ 114:	4b50 4030           	calcbxd.f	r3,r3,r2
+ 118:	4800 0050           	calckey	r0,r0,r0
+ 11c:	4910 0050           	calckey.f	r1,r1,r0
+ 120:	4940 0050           	calckey	r1,r1,r2
+ 124:	4b50 0050           	calckey.f	r3,r3,r2
+ 128:	4800 4050           	calcxkey	r0,r0,r0
+ 12c:	4910 4050           	calcxkey.f	r1,r1,r0
+ 130:	4940 4050           	calcxkey	r1,r1,r2
+ 134:	4b50 4050           	calcxkey.f	r3,r3,r2
+ 138:	582b 0440           	mxb	r0,r1,0,0x1,0x2
+ 13c:	582b 0e38           	mxb	r0,r1,0x7,0x8,0x7
+ 140:	582b 01f8           	mxb	r0,r1,0x7,0x7,0x8
+ 144:	5a6b a708           	mxb.s	r2,r3,0x1,0x4,0x3,0x2
+ 148:	5a6b fe38           	mxb.s	r2,r3,0x7,0x8,0x7,0x7
+ 14c:	5a6b f1f8           	mxb.s	r2,r3,0x7,0x7,0x8,0x7
+ 150:	5a6b 8e38           	mxb.s	r2,r3,0x7,0x8,0x7,0x8
+ 154:	582b 0441           	imxb	r0,r1,0,0x1,0x2
+ 158:	582b 0e39           	imxb	r0,r1,0x7,0x8,0x7
+ 15c:	582b 01f9           	imxb	r0,r1,0x7,0x7,0x8
+ 160:	5a6b a709           	imxb.s	r2,r3,0x1,0x4,0x3,0x2
+ 164:	5a6b fe39           	imxb.s	r2,r3,0x7,0x8,0x7,0x7
+ 168:	5a6b f1f9           	imxb.s	r2,r3,0x7,0x7,0x8,0x7
+ 16c:	5a6b 8e39           	imxb.s	r2,r3,0x7,0x8,0x7,0x8
+ 170:	480a 0000           	addl	r0,r0,0
+ 174:	484a 7fff           	addl	r2,r2,32767
+ 178:	48aa 8000           	addl	r5,r5,-32768
+ 17c:	495a 0000           	addl.f	r10,r10,0
+ 180:	497a 0001           	addl.f	r11,r11,1
+ 184:	499a ffff           	addl.f	r12,r12,-1
+ 188:	480b 0000           	subl	r0,r0,0
+ 18c:	484b 7fff           	subl	r2,r2,32767
+ 190:	48ab 8000           	subl	r5,r5,-32768
+ 194:	495b 0000           	subl.f	r10,r10,0
+ 198:	497b 0001           	subl.f	r11,r11,1
+ 19c:	499b ffff           	subl.f	r12,r12,-1
+ 1a0:	480d 0000           	andl	r0,r0,0
+ 1a4:	482d 0001           	andl	r1,r1,0x1
+ 1a8:	484d ffff           	andl	r2,r2,0xffff
+ 1ac:	495d 0000           	andl.f	r10,r10,0
+ 1b0:	497d 0001           	andl.f	r11,r11,0x1
+ 1b4:	499d ffff           	andl.f	r12,r12,0xffff
+ 1b8:	480c 0000           	orl	r0,r0,0
+ 1bc:	482c 0001           	orl	r1,r1,0x1
+ 1c0:	484c ffff           	orl	r2,r2,0xffff
+ 1c4:	495c 0000           	orl.f	r10,r10,0
+ 1c8:	497c 0001           	orl.f	r11,r11,0x1
+ 1cc:	499c ffff           	orl.f	r12,r12,0xffff
+ 1d0:	480e 0000           	xorl	r0,r0,0
+ 1d4:	482e 0001           	xorl	r1,r1,0x1
+ 1d8:	484e ffff           	xorl	r2,r2,0xffff
+ 1dc:	495e 0000           	xorl.f	r10,r10,0
+ 1e0:	497e 0001           	xorl.f	r11,r11,0x1
+ 1e4:	499e ffff           	xorl.f	r12,r12,0xffff
+ 1e8:	4800 0011           	andab	r0,r0,0,0x1
+ 1ec:	4940 3df1           	andab	r1,r2,0xf,0x10
+ 1f0:	4a70 0011           	andab.f	r2,r3,0,0x1
+ 1f4:	4cb0 3e11           	andab.f	r12,r13,0x10,0x10
+ 1f8:	4800 8011           	andab	r0,r0,r0,0,0x1
+ 1fc:	4940 bdf1           	andab	r1,r1,r2,0xf,0x10
+ 200:	4a70 8011           	andab.f	r2,r2,r3,0,0x1
+ 204:	4cb0 be11           	andab.f	r12,r12,r13,0x10,0x10
+ 208:	4800 0012           	orab	r0,r0,0,0x1
+ 20c:	4940 3df2           	orab	r1,r2,0xf,0x10
+ 210:	4a70 0012           	orab.f	r2,r3,0,0x1
+ 214:	4cb0 3e12           	orab.f	r12,r13,0x10,0x10
+ 218:	4800 8012           	orab	r0,r0,r0,0,0x1
+ 21c:	4940 bdf2           	orab	r1,r1,r2,0xf,0x10
+ 220:	4a70 8012           	orab.f	r2,r2,r3,0,0x1
+ 224:	4cb0 be12           	orab.f	r12,r12,r13,0x10,0x10
+ 228:	382f 0045           	lbdsize	r0,r1
+ 22c:	3a2f 00c5           	lbdsize	r2,r3
+ 230:	382f 8045           	lbdsize.f	r0,r1
+ 234:	3a2f 80c5           	lbdsize.f	r2,r3
+ 238:	4820 0033           	bdlen	r0,r1,0x1
+ 23c:	4960 0013           	bdlen	r1,r3,0x100
+ 240:	4940 1e13           	bdlen	r1,r2,0xf0
+ 244:	4ca0 4013           	bdlen	r12,r13
+ 248:	4830 0033           	bdlen.f	r0,r1,0x1
+ 24c:	4970 0013           	bdlen.f	r1,r3,0x100
+ 250:	4cb0 4013           	bdlen.f	r12,r13
+ 254:	3c2a 150a           	csma	r10,r12,r20
+ 258:	3e2a 7500 1234 5678 	csma	r0,0x12345678,r20
+ 260:	3f2a 0f86 ffff ffff 	csma	r6,r7,0xffffffff
+ 268:	3e2a 7f88 ffff ffff 	csma	r8,0xffffffff,0xffffffff
+ 270:	3e2a 137e           	csma	0,r14,r13
+ 274:	3e2a 72be ffff ffff 	csma	0,0xffffffff,r10
+ 27c:	3c2a 1fbe ffff ffff 	csma	0,r12,0xffffffff
+ 284:	3d6a 0044           	csma	r4,r5,0x1
+ 288:	3e6a 7083 1234 5678 	csma	r3,0x12345678,0x2
+ 290:	396a 013e           	csma	0,r1,0x4
+ 294:	3e6a 707e ffff ffff 	csma	0,0xffffffff,0x1
+ 29c:	3c2c 150a           	csms	r10,r12,r20
+ 2a0:	3e2c 7500 1234 5678 	csms	r0,0x12345678,r20
+ 2a8:	3f2c 0f86 ffff ffff 	csms	r6,r7,0xffffffff
+ 2b0:	3e2c 7f88 ffff ffff 	csms	r8,0xffffffff,0xffffffff
+ 2b8:	3e2c 137e           	csms	0,r14,r13
+ 2bc:	3e2c 72be ffff ffff 	csms	0,0xffffffff,r10
+ 2c4:	3c2c 1fbe ffff ffff 	csms	0,r12,0xffffffff
+ 2cc:	3d6c 0044           	csms	r4,r5,0x1
+ 2d0:	3e6c 7083 1234 5678 	csms	r3,0x12345678,0x2
+ 2d8:	396c 013e           	csms	0,r1,0x4
+ 2dc:	3e6c 707e ffff ffff 	csms	0,0xffffffff,0x1
+ 2e4:	3c2d 150a           	cbba	r10,r12,r20
+ 2e8:	3e2d 7500 1234 5678 	cbba	r0,0x12345678,r20
+ 2f0:	3f2d 0f86 ffff ffff 	cbba	r6,r7,0xffffffff
+ 2f8:	3e2d 7f88 ffff ffff 	cbba	r8,0xffffffff,0xffffffff
+ 300:	3e2d 137e           	cbba	0,r14,r13
+ 304:	3e2d 72be ffff ffff 	cbba	0,0xffffffff,r10
+ 30c:	3c2d 1fbe ffff ffff 	cbba	0,r12,0xffffffff
+ 314:	3d6d 0044           	cbba	r4,r5,0x1
+ 318:	3e6d 7083 1234 5678 	cbba	r3,0x12345678,0x2
+ 320:	396d 013e           	cbba	0,r1,0x4
+ 324:	3e6d 707e ffff ffff 	cbba	0,0xffffffff,0x1
+ 32c:	3c2d 950a           	cbba.f	r10,r12,r20
+ 330:	3e2d f500 1234 5678 	cbba.f	r0,0x12345678,r20
+ 338:	3f2d 8f86 ffff ffff 	cbba.f	r6,r7,0xffffffff
+ 340:	3e2d ff88 ffff ffff 	cbba.f	r8,0xffffffff,0xffffffff
+ 348:	3e2d 937e           	cbba.f	0,r14,r13
+ 34c:	3e2d f2be ffff ffff 	cbba.f	0,0xffffffff,r10
+ 354:	3c2d 9fbe ffff ffff 	cbba.f	0,r12,0xffffffff
+ 35c:	3d6d 8044           	cbba.f	r4,r5,0x1
+ 360:	3e6d f083 1234 5678 	cbba.f	r3,0x12345678,0x2
+ 368:	396d 813e           	cbba.f	0,r1,0x4
+ 36c:	3e6d f07e ffff ffff 	cbba.f	0,0xffffffff,0x1
+ 374:	3c35 150a           	zncv.rd	r10,r12,r20
+ 378:	3e35 7500 1234 5678 	zncv.rd	r0,0x12345678,r20
+ 380:	3f35 0f86 ffff ffff 	zncv.rd	r6,r7,0xffffffff
+ 388:	3e35 7f88 ffff ffff 	zncv.rd	r8,0xffffffff,0xffffffff
+ 390:	3e35 137e           	zncv.rd	0,r14,r13
+ 394:	3e35 72be ffff ffff 	zncv.rd	0,0xffffffff,r10
+ 39c:	3c35 1fbe ffff ffff 	zncv.rd	0,r12,0xffffffff
+ 3a4:	3d75 0044           	zncv.rd	r4,r5,0x1
+ 3a8:	3e75 7083 1234 5678 	zncv.rd	r3,0x12345678,0x2
+ 3b0:	3975 013e           	zncv.rd	0,r1,0x4
+ 3b4:	3e75 707e ffff ffff 	zncv.rd	0,0xffffffff,0x1
+ 3bc:	39b5 0fff           	zncv.rd	r1,r1,-1
+ 3c0:	3eb5 7fff ffff ffff 	zncv.rd	0,0xffffffff,-1
+ 3c8:	3c35 950a           	zncv.wr	r10,r12,r20
+ 3cc:	3e35 f500 1234 5678 	zncv.wr	r0,0x12345678,r20
+ 3d4:	3f35 8f86 ffff ffff 	zncv.wr	r6,r7,0xffffffff
+ 3dc:	3e35 ff88 ffff ffff 	zncv.wr	r8,0xffffffff,0xffffffff
+ 3e4:	3e35 937e           	zncv.wr	0,r14,r13
+ 3e8:	3e35 f2be ffff ffff 	zncv.wr	0,0xffffffff,r10
+ 3f0:	3c35 9fbe ffff ffff 	zncv.wr	0,r12,0xffffffff
+ 3f8:	3d75 8044           	zncv.wr	r4,r5,0x1
+ 3fc:	3e75 f083 1234 5678 	zncv.wr	r3,0x12345678,0x2
+ 404:	3975 813e           	zncv.wr	0,r1,0x4
+ 408:	3e75 f07e ffff ffff 	zncv.wr	0,0xffffffff,0x1
+ 410:	39b5 8fff           	zncv.wr	r1,r1,-1
+ 414:	3eb5 ffff ffff ffff 	zncv.wr	0,0xffffffff,-1
+ 41c:	3a36 00c1           	hofs	r1,r2,r3
+ 420:	3d36 8184           	hofs.f	r4,r5,r6
+ 424:	3876 13c7           	hofs	r7,r8,0xf0,0
+ 428:	3876 9807           	hofs.f	r7,r8,0,0x1
diff --git a/gas/testsuite/gas/arc/nps400-6.s b/gas/testsuite/gas/arc/nps400-6.s
index 4a94a0c..797097d 100644
--- a/gas/testsuite/gas/arc/nps400-6.s
+++ b/gas/testsuite/gas/arc/nps400-6.s
@@ -40,6 +40,52 @@
         \mnem\()	r1, r1, r2, 256
         .endm
 
+        .macro calcbsxdkey_test mnem
+        \mnem\()        r0, r0, r0
+        \mnem\().f      r1, r1, r0
+        \mnem\()        r1, r1, r2
+        \mnem\().f      r3, r3, r2
+        .endm
+
+        .macro mxb_like_test mnem
+        \mnem\()        r0, r1, 0, 1, 2
+        \mnem\()        r0, r1, 7, 8, 7
+        \mnem\()        r0, r1, 7, 7, 8
+        \mnem\().s      r2, r3, 1, 4, 3, 2
+        \mnem\().s      r2, r3, 7, 8, 7, 7
+        \mnem\().s      r2, r3, 7, 7, 8, 7
+        \mnem\().s      r2, r3, 7, 8, 7, 8
+        .endm
+
+        .macro addsubl_test mnem
+        \mnem\()        r0, r0, 0
+        \mnem\()        r2, r2, 32767
+        \mnem\()        r5, r5, -32768
+        \mnem\().f      r10, r10, 0
+        \mnem\().f      r11, r11, 1
+        \mnem\().f      r12, r12, -1
+        .endm
+
+        .macro andorxorl_test mnem
+        \mnem\()        r0, r0, 0
+        \mnem\()        r1, r1, 1
+        \mnem\()        r2, r2, 65535
+        \mnem\().f      r10, r10, 0
+        \mnem\().f      r11, r11, 1
+        \mnem\().f      r12, r12, 65535
+        .endm
+
+        .macro andorab_test mnem
+        \mnem\()        r0, r0, 0, 1
+        \mnem\()        r1, r2, 15, 16
+        \mnem\().f      r2, r3, 0, 1
+        \mnem\().f      r12, r13, 16, 16
+        \mnem\()        r0, r0, r0, 0, 1
+        \mnem\()        r1, r1, r2, 15, 16
+        \mnem\().f      r2, r2, r3, 0, 1
+        \mnem\().f      r12, r12, r13, 16, 16
+        .endm
+
         addb_like_test addb
         addb_like_test subb
         addb_like_test adcb
@@ -65,3 +111,78 @@
 
         calcsxd_test    calcsd
         calcsxd_test    calcxd
+
+        calcbsxdkey_test calcbsd
+        calcbsxdkey_test calcbxd
+        calcbsxdkey_test calckey
+        calcbsxdkey_test calcxkey
+
+        mxb_like_test mxb
+        mxb_like_test imxb
+
+        addsubl_test addl
+        addsubl_test subl
+
+        andorxorl_test andl
+        andorxorl_test orl
+        andorxorl_test xorl
+
+        andorab_test andab
+        andorab_test orab
+
+        lbdsize         r0, r1
+        lbdsize         r2, r3
+        lbdsize.f       r0, r1
+        lbdsize.f       r2, r3
+
+        bdlen           r0, r1, 1
+        bdlen           r1, r3, 256
+        bdlen           r1, r2, 240
+        bdlen           r12, r13
+        bdlen.f         r0, r1, 1
+        bdlen.f         r1, r3, 256
+        bdlen.f         r12, r13
+
+        .macro cscb_test mnem
+        \mnem\()        r10,r12,r20
+        \mnem\()        r0,0x12345678,r20
+        \mnem\()        r6,r7,0xffffffff
+        \mnem\()        r8,0xffffffff,0xffffffff
+        \mnem\()        0,r14,r13
+        \mnem\()        0,0xffffffff,r10
+        \mnem\()        0,r12,0xffffffff
+        \mnem\()        r4,r5,0x1
+        \mnem\()        r3,0x12345678,0x2
+        \mnem\()        0,r1,0x4
+        \mnem\()        0,0xffffffff,0x1
+        .endm
+
+        cscb_test csma
+        cscb_test csms
+        cscb_test cbba
+        cscb_test cbba.f
+
+        .macro zncv_test mnem
+        \mnem\()        r10,r12,r20
+        \mnem\()        r0,0x12345678,r20
+        \mnem\()        r6,r7,0xffffffff
+        \mnem\()        r8,0xffffffff,0xffffffff
+        \mnem\()        0,r14,r13
+        \mnem\()        0,0xffffffff,r10
+        \mnem\()        0,r12,0xffffffff
+        \mnem\()        r4,r5,0x1
+        \mnem\()        r3,0x12345678,0x2
+        \mnem\()        0,r1,0x4
+        \mnem\()        0,0xffffffff,0x1
+        \mnem\()        r1,r1,-1
+        \mnem\()        0,0xffffffff,-1
+        .endm
+
+        zncv_test zncv.rd
+        zncv_test zncv.wr
+
+        hofs            r1, r2, r3
+        hofs.f          r4, r5, r6
+        hofs            r7, r8, 240, 0
+        hofs.f          r7, r8, 0, 1
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fbde3e1..6b54926 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,28 @@
+2016-06-13  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
+	imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
+	csma, cbba, zncv, and hofs.
+	* arc-opc.c: Add flag classes, insert/extract functions, and operands to
+	support the above instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add andab and orab instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add addl-like instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add mxb and imxb instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
+	instructions.
+
 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
 	* s390-dis.c (option_use_insn_len_bits_p): New file scope
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 473a586..fe6a195 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -191,6 +191,182 @@ DIV_LIKE ("divm", 0x0)
 { "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 { "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 
+{ "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+{ "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+{ "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+{ "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+
+#define ADDL_LIKE(NAME,SUBOP2,SHIM)                                     \
+  { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }},
+
+ADDL_LIKE ("addl", 0xA, NPS_SIMM16)
+ADDL_LIKE ("subl", 0xB, NPS_SIMM16)
+ADDL_LIKE ("orl", 0xC, NPS_UIMM16)
+ADDL_LIKE ("andl", 0xD, NPS_UIMM16)
+ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
+
+{ "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+
+{ "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RC }, { C_F }},
+
+{ "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+/* csma a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
+{ "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* csma a,limm,c   0011111000100001F111CCCCCCAAAAAA */
+{ "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* csma a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
+{ "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* csma 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
+{ "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* csma 0,limm,c   0011111000100001F111CCCCCC111110 */
+{ "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* csma 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
+{ "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* csma 0,b,limm   00111bbb00100001FBBB111110111110 */
+{ "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* csma a,b,limm   00111bbb00100001FBBB111110AAAAAA */
+{ "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* csma a,limm,limm    0011111000100001F111111110AAAAAA */
+{ "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* csma a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
+{ "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csma 0,limm,u6   0011111001100001F111uuuuuu111110 */
+{ "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csms a,b,c   00111bbb00101100FBBBCCCCCCAAAAAA */
+{ "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* csma a,limm,c   0011111000101100F111CCCCCCAAAAAA */
+{ "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* csms a,b,u6   00111bbb01101100FBBBuuuuuuAAAAAA */
+{ "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* csms 0,b,c   00111bbb00101100FBBBCCCCCC111110 */
+{ "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* csms 0,limm,c   0011111000101100F111CCCCCC111110 */
+{ "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* csms 0,b,u6   00111bbb01101100FBBBuuuuuu111110 */
+{ "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* csms 0,b,limm   00111bbb00101100FBBB111110111110 */
+{ "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* csms a,b,limm   00111bbb00101100FBBB111110AAAAAA */
+{ "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* csms a,limm,limm   0011111000101100F111111110AAAAAA */
+{ "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* csms a,limm,u6   0011111001101100F111uuuuuuAAAAAA */
+{ "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csms 0,limm,u6   0011111001101100F111uuuuuu111110 */
+{ "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbba a,b,c   00111bbb00101101FBBBCCCCCCAAAAAA */
+{ "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* cbba a,limm,c    0011111000101101F111CCCCCCAAAAAA */
+{ "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* cbba a,b,u6   00111bbb01101101FBBBuuuuuuAAAAAA */
+{ "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* cbba 0,b,c   00111bbb00101101FBBBCCCCCC111110 */
+{ "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* cbba 0,limm,c   0011111000101101F111CCCCCC111110 */
+{ "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* cbba 0,b,u6   00111bbb01101101FBBBuuuuuu111110 */
+{ "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* cbba 0,b,limm   00111bbb00101101FBBB111110111110 */
+{ "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* cbba a,b,limm   00111bbb00101101FBBB111110AAAAAA */
+{ "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* cbba a,limm,limm   0011111000101101F111111110AAAAAA */
+{ "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* cbba a,limm,u6   0011111001101101F111uuuuuuAAAAAA */
+{ "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* cbba 0,limm,u6   0011111001101101F111uuuuuu111110 */
+{ "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* zncv<.rd|.wr> a,b,c   00111bbb001101010BBBCCCCCCAAAAAA */
+{ "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,b,u6   00111bbb011101010BBBuuuuuuAAAAAA */
+{ "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> b,b,s12   00111bbb101101010BBBssssssSSSSSS */
+{ "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,b,limm   00111bbb001101010BBB111110AAAAAA */
+{ "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,c   00111110001101010111CCCCCCAAAAAA */
+{ "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,u6   00111110011101010111uuuuuuAAAAAA */
+{ "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,limm   00111110001101010111111110AAAAAA */
+{ "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,c 00111bbb001101010BBBCCCCCC111110 */
+{ "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,u6   00111bbb011101010BBBuuuuuu111110 */
+{ "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,limm   00111bbb001101010BBB111110111110 */
+{ "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,c   00111110001101010111CCCCCC111110 */
+{ "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,u6   00111110011101010111uuuuuu111110 */
+{ "zncv", 0x3e75703e, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,s12   00111110101101010111ssssssSSSSSS */
+{ "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }},
+
+/* hofs a,b,c */
+{ "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* hofs a,b,min_hofs,psbc */
+{ "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
+
 /****                  Protocol Decoder Instructions                  ****/
 
 /* dctcp b,c  00111bbb001011110bbbcccccc000000 */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 4c69a16..7e0ba46 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1110,6 +1110,55 @@ extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
   return value;
 }
 
+#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS)         \
+static unsigned                                                         \
+insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED,                      \
+                   int value ATTRIBUTE_UNUSED,                          \
+                   const char **errmsg ATTRIBUTE_UNUSED)                \
+{                                                                       \
+  if (value < 1 || value > UPPER)                                       \
+    *errmsg = _("Value must be in the range 1 to " #UPPER);             \
+  if (value == UPPER)                                                   \
+    value = 0;                                                          \
+  return insn | (value << SHIFT);                                       \
+}                                                                       \
+                                                                        \
+static int                                                              \
+extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED,                     \
+                    bfd_boolean * invalid ATTRIBUTE_UNUSED)             \
+{                                                                       \
+  int value = (insn >> SHIFT) & ((1 << BITS) - 1);                      \
+  if (value == 0)                                                       \
+    value = UPPER;                                                      \
+  return value;                                                         \
+}
+
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
+
+static unsigned
+insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
+                     int value ATTRIBUTE_UNUSED,
+                     const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value < 0 || value > 240)
+    *errmsg = _("Value must be in the range 0 to 240");
+  if ((value % 16) != 0)
+    *errmsg = _("Value must be a multiple of 16");
+  value = value / 16;
+  return insn | (value << 6);
+}
+
+static int
+extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
+                      bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 6) & 0xF;
+  return value * 16;
+}
+
 /* Include the generic extract/insert functions.  Order is important
    as some of the functions present in the .h may be disabled via
    defines.  */
@@ -1314,6 +1363,15 @@ const struct arc_flag_operand arc_flag_operands[] =
 
 #define F_NPS_AL     (F_NPS_AR + 1)
   { "al",  1, 1, 0, 1 },
+
+#define F_NPS_S      (F_NPS_AL + 1)
+  { "s",   0, 0, 0, 1 },
+
+#define F_NPS_ZNCV_RD      (F_NPS_S + 1)
+  { "rd",  0, 1, 15, 1 },
+
+#define F_NPS_ZNCV_WR      (F_NPS_ZNCV_RD + 1)
+  { "wr",  1, 1, 15, 1 },
 };
 
 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -1420,6 +1478,12 @@ const struct arc_flag_class arc_flag_classes[] =
 
 #define C_NPS_AR_AL     (C_NPS_SX + 1)
   { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
+
+#define C_NPS_S    (C_NPS_AR_AL + 1)
+  { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
+
+#define C_NPS_ZNCV    (C_NPS_S + 1)
+  { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
 };
 
 const unsigned char flags_none[] = { 0 };
@@ -1785,7 +1849,10 @@ const struct arc_operand arc_operands[] =
 #define NPS_UIMM16		(NPS_BITOP_UIMM8 + 1)
   { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
 
-#define NPS_RFLT_UIMM6		(NPS_UIMM16 + 1)
+#define NPS_SIMM16              (NPS_UIMM16 + 1)
+  { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
+
+#define NPS_RFLT_UIMM6		(NPS_SIMM16 + 1)
   { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
 
 #define NPS_XLDST_UIMM16	(NPS_RFLT_UIMM6 + 1)
@@ -1889,6 +1956,30 @@ const struct arc_operand arc_operands[] =
 
 #define NPS_BITOP_INS_EXT	(NPS_BITOP_MOD1 + 1)
   { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
+
+#define NPS_FIELD_START_POS     (NPS_BITOP_INS_EXT + 1)
+  { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_FIELD_SIZE          (NPS_FIELD_START_POS + 1)
+  { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
+
+#define NPS_SHIFT_FACTOR        (NPS_FIELD_SIZE + 1)
+  { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
+
+#define NPS_BITS_TO_SCRAMBLE    (NPS_SHIFT_FACTOR + 1)
+  { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
+
+#define NPS_SRC2_POS_5B         (NPS_BITS_TO_SCRAMBLE + 1)
+  { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BDLEN_MAX_LEN       (NPS_SRC2_POS_5B + 1)
+  { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
+
+#define NPS_MIN_HOFS       (NPS_BDLEN_MAX_LEN + 1)
+  { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
+
+#define NPS_PSBC       (NPS_MIN_HOFS + 1)
+  { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
 };
 
 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);