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authorFred Fish <fnf@specifix.com>1997-02-07 00:28:19 +0000
committerFred Fish <fnf@specifix.com>1997-02-07 00:28:19 +0000
commit12e8f8af1f2a86ba105a83cddbd5186f89bc805c (patch)
treec41412551337e6fde20c47b6aa6da2375d6cf051
parent6382554a6c4a32acb09f35c46c44e871136e96ba (diff)
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* tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
endmask fields, which are somewhat weird in that 0 and 32 are treated exactly the same.
-rw-r--r--include/opcode/ChangeLog6
-rw-r--r--include/opcode/tic80.h9
2 files changed, 15 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 64684cf..9191de9 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,4 +1,10 @@
start-sanitize-tic80
+Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
+ endmask fields, which are somewhat weird in that 0 and 32 are
+ treated exactly the same.
+
Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com>
* tic80.h: Change all the OPERAND defines to use the form (1 << X)
diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h
index 4065528..f37d938 100644
--- a/include/opcode/tic80.h
+++ b/include/opcode/tic80.h
@@ -200,6 +200,15 @@ extern const struct tic80_operand tic80_operands[];
#define TIC80_OPERAND_BASEREL (1 << 11)
+/* This operand is an "endmask" field for a shift instruction.
+ It is treated special in that it can have values of 0-32,
+ where 0 and 32 result in the same instruction. The assembler
+ must be able to accept both endmask values. This disassembler
+ has no way of knowing from the instruction which value was
+ given at assembly time, so it just uses '0'. */
+
+#define TIC80_OPERAND_ENDMASK (1 << 12)
+
/* This operand is one of the 32 general purpose registers.
The disassembler prints these with a leading 'r'. */