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author | Jan Beulich <jbeulich@suse.com> | 2022-09-30 11:44:32 +0200 |
---|---|---|
committer | Jan Beulich <jbeulich@suse.com> | 2022-09-30 11:44:32 +0200 |
commit | 0b8c36f7177afa59cb1527c62c3d04030c9a092d (patch) | |
tree | 9de0a0854b20dda6d7fc46b055a4dfd2bc329eb7 | |
parent | b0423163b808c463fe35e861471f80123f0b309f (diff) | |
download | gdb-0b8c36f7177afa59cb1527c62c3d04030c9a092d.zip gdb-0b8c36f7177afa59cb1527c62c3d04030c9a092d.tar.gz gdb-0b8c36f7177afa59cb1527c62c3d04030c9a092d.tar.bz2 |
RISC-V: fallout from "re-arrange opcode table for consistent alias handling"
Several new testcasee have appeared since the submission of said change,
some of which now also need adjustment.
-rw-r--r-- | gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/dis-addr-overflow-32.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/dis-addr-overflow-64.d | 8 |
4 files changed, 14 insertions, 14 deletions
diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d index 3cd9d4e..c4e4cfe 100644 --- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d @@ -9,10 +9,10 @@ Disassembly of section .text: 0+ffffffe0 <_start>: [ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0 -[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a> +[ ]+ffffffe4:[ ]+0182831b[ ]+addw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a> [ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0 -[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b> +[ ]+ffffffec:[ ]+01c38e1b[ ]+addw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b> [ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0 -[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a> +[ ]+fffffff4:[ ]+2eb1[ ]+addw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a> [ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0 -[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b> +[ ]+fffffffa:[ ]+2f49[ ]+addw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b> diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d index 2c68d6b..d5f84db 100644 --- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d @@ -9,10 +9,10 @@ Disassembly of section .text: 0+7fffffe0 <_start>: [ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0 -[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a> +[ ]+7fffffe4:[ ]+0182831b[ ]+addw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a> [ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0 -[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b> +[ ]+7fffffec:[ ]+01c38e1b[ ]+addw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b> [ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0 -[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a> +[ ]+7ffffff4:[ ]+2eb1[ ]+addw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a> [ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0 -[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b> +[ ]+7ffffffa:[ ]+2f49[ ]+addw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d index 43f712a..287c5ea 100644 --- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d @@ -19,9 +19,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb [ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffb000 <addr_jalr_3> [ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa -[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr> +[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+add[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr> [ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9 -[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c> +[ ]+[0-9a-f]+:[ ]+1fb1[ ]+add[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c> [ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos> [ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg> [ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos> diff --git a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d index 065ee25..1966a5e 100644 --- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d +++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d @@ -19,13 +19,13 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb [ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffffffffffb000 <addr_jalr_3> [ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa -[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr> +[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+add[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr> [ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9 -[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c> +[ ]+[0-9a-f]+:[ ]+1fb1[ ]+add[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c> [ ]+[0-9a-f]+:[ ]+ffff8b37[ ]+lui[ ]+s6,0xffff8 -[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addiw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w> +[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w> [ ]+[0-9a-f]+:[ ]+ffff7c37[ ]+lui[ ]+s8,0xffff7 -[ ]+[0-9a-f]+:[ ]+3c11[ ]+addiw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c> +[ ]+[0-9a-f]+:[ ]+3c11[ ]+addw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c> [ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos> [ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg> [ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos> |