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authorMike Frysinger <vapier@gentoo.org>2012-03-19 05:25:50 +0000
committerMike Frysinger <vapier@gentoo.org>2012-03-19 05:25:50 +0000
commit6aafca16ed58c0c761a5918f262fd80ae0386fee (patch)
treedc23551c0faea4ba92bb4fe9e699ace1dabac24d
parentdbe91450952a17d927e206f760417c0509bc982a (diff)
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sim: bfin: add tests for new shift behavior
-rw-r--r--sim/testsuite/sim/bfin/ChangeLog4
-rw-r--r--sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s7
2 files changed, 11 insertions, 0 deletions
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index 1dc3cca..828ad62 100644
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,3 +1,7 @@
+2012-03-19 Stuart Henderson <stuart.henderson@analog.com>
+
+ * c_dsp32shiftim_amix.s: Check edge cases in shift behavior.
+
2012-03-19 Robin Getz <robin.getz@analog.com>
* random_0014.S, random_0015.S, random_0016.S: New tests for shifts.
diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s
index 1bf9178..d1c0c20 100644
--- a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s
+++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s
@@ -114,6 +114,13 @@ R7 = R2 << 5 (S); /* r7 = 0x80000000 */
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
+imm32 r0, 0xFFFFFFF4;
+imm32 r2, 0xFFF00001;
+R6 = R0 << 31 (S); /* r6 = 0x80000000 */
+R7 = R2 << 31 (S); /* r7 = 0x80000000 */
+CHECKREG r6, 0x80000000;
+CHECKREG r7, 0x80000000;
+
// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;