From 6aafca16ed58c0c761a5918f262fd80ae0386fee Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 19 Mar 2012 05:25:50 +0000 Subject: sim: bfin: add tests for new shift behavior --- sim/testsuite/sim/bfin/ChangeLog | 4 ++++ sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index 1dc3cca..828ad62 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2012-03-19 Stuart Henderson + + * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. + 2012-03-19 Robin Getz * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s index 1bf9178..d1c0c20 100644 --- a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s +++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s @@ -114,6 +114,13 @@ R7 = R2 << 5 (S); /* r7 = 0x80000000 */ CHECKREG r6, 0x80000000; CHECKREG r7, 0x80000000; +imm32 r0, 0xFFFFFFF4; +imm32 r2, 0xFFF00001; +R6 = R0 << 31 (S); /* r6 = 0x80000000 */ +R7 = R2 << 31 (S); /* r7 = 0x80000000 */ +CHECKREG r6, 0x80000000; +CHECKREG r7, 0x80000000; + // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok imm32 r0, 0x80f080f0; -- cgit v1.1