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author | Jamey Hicks <jamey.hicks@gmail.com> | 2019-05-14 10:40:04 +0100 |
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committer | Nick Clifton <nickc@redhat.com> | 2019-05-14 10:42:25 +0100 |
commit | 37d0d09177dc02e0002ab8b90d9b7bc402af9240 (patch) | |
tree | 637533c2e254a181fb4fdceced99cf406e952936 /.gitattributes | |
parent | 3076e59490428c9719765f9b007d6d0d0238f006 (diff) | |
download | gdb-37d0d09177dc02e0002ab8b90d9b7bc402af9240.zip gdb-37d0d09177dc02e0002ab8b90d9b7bc402af9240.tar.gz gdb-37d0d09177dc02e0002ab8b90d9b7bc402af9240.tar.bz2 |
Add new option to objcopy: --verilog-data-width. Use this option to set the size of byte bundles generated in verilog format files.
PR 19921
binutils* objcopy.c: Add new option --verilog-data-width. Use it to set
the value of VerilogDataWidth.
* doc/binutils.texi: Document the new option.
* testsuite/binutils-all/objcopy.exp: Run tests of new option.
* testsuite/binutils-all/verilog-1.hex: New file.
* testsuite/binutils-all/verilog-2.hex: New file.
* testsuite/binutils-all/verilog-4.hex: New file.
* testsuite/binutils-all/verilog-8.hex: New file.
* NEWS: Mention the new feature.
bfd * verilog.c: (VerilogDataWidth): New variable.
(verilog_write_record): Emit bytes in VerilogDataWidth bundles.
Diffstat (limited to '.gitattributes')
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