libjava/classpath/lib/java/util/AbstractCollection.class

/***************************************************************************
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dominic.Rath@gmx.de                                                   *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "arm.h"
#include "etm.h"
#include "etb.h"
#include "image.h"
#include "arm_disassembler.h"
#include "register.h"
#include "etm_dummy.h"

#if BUILD_OOCD_TRACE == 1
#include "oocd_trace.h"
#endif


/*
 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
 *
 * ETM modules collect instruction and/or data trace information, compress
 * it, and transfer it to a debugging host through either a (buffered) trace
 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
 *
 * There are several generations of these modules.  Original versions have
 * JTAG access through a dedicated scan chain.  Recent versions have added
 * access via coprocessor instructions, memory addressing, and the ARM Debug
 * Interface v5 (ADIv5); and phased out direct JTAG access.
 *
 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
 * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
 * implying non-JTAG connectivity options.
 *
 * Relevant documentation includes:
 *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
 *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
 *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
 */

enum {
	RO,				/* read/only */
	WO,				/* write/only */
	RW,				/* read/write */
};

struct etm_reg_info {
	uint8_t addr;
	uint8_t size;			/* low-N of 32 bits */
	uint8_t mode;			/* RO, WO, RW */
	uint8_t bcd_vers;		/* 1.0, 2.0, etc */
	const char *name;
};

/*
 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
 * (Or on some processors, through coprocessor operations.)
 * Newer versions of ETM make some W/O registers R/W, and
 * provide definitions for some previously-unused bits.
 */

/* core registers used to version/configure the ETM */
static const struct etm_reg_info etm_core[] = {
	/* NOTE: we "know" the order here ... */
	{ ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
	{ ETM_ID, 32, RO, 0x20, "ETM_id", },
};

/* basic registers that are always there given the right ETM version */
static const struct etm_reg_info etm_basic[] = {
	/* ETM Trace Registers */
	{ ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
	{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
	{ ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
	{ ETM_STATUS,  3, RO, 0x11, "ETM_status", },
	{ ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },

	/* TraceEnable configuration */
	{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
	{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
	{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
	{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },

	/* ViewData configuration (data trace) */
	{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
	{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
	{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
	{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },

	/* REVISIT exclude VIEWDATA_CTRL2 when it's not there */

	{ 0x78, 12, WO, 0x20, "ETM_sync_freq", },
	{ 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
	{ 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
	{ 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
	{ 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
};

static const struct etm_reg_info etm_fifofull[] = {
	/* FIFOFULL configuration */
	{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
	{ ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
};

static const struct etm_reg_info etm_addr_comp[] = {
	/* Address comparator register pairs */
#define ADDR_COMPARATOR(i) \
		{ ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
				"ETM_addr_" #i "_comparator_value", }, \
		{ ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
				"ETM_addr_" #i "_access_type", }
	ADDR_COMPARATOR(1),
	ADDR_COMPARATOR(2),
	ADDR_COMPARATOR(3),
	ADDR_COMPARATOR(4),
	ADDR_COMPARATOR(5),
	ADDR_COMPARATOR(6),
	ADDR_COMPARATOR(7),
	ADDR_COMPARATOR(8),

	ADDR_COMPARATOR(9),
	ADDR_COMPARATOR(10),
	ADDR_COMPARATOR(11),
	ADDR_COMPARATOR(12),
	ADDR_COMPARATOR(13),
	ADDR_COMPARATOR(14),
	ADDR_COMPARATOR(15),
	ADDR_COMPARATOR(16),
	{ 0, 0, 0, 0, NULL }
#undef ADDR_COMPARATOR
};

static const struct etm_reg_info etm_data_comp[] = {
	/* Data Value Comparators (NOTE: odd addresses are reserved) */
#define DATA_COMPARATOR(i) \
		{ ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
				"ETM_data_" #i "_comparator_value", }, \
		{ ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
				"ETM_data_" #i "_comparator_mask", }
	DATA_COMPARATOR(1),
	DATA_COMPARATOR(2),
	DATA_COMPARATOR(3),
	DATA_COMPARATOR(4),
	DATA_COMPARATOR(5),
	DATA_COMPARATOR(6),
	DATA_COMPARATOR(7),
	DATA_COMPARATOR(8),
	{ 0, 0, 0, 0, NULL }
#undef DATA_COMPARATOR
};

static const struct etm_reg_info etm_counters[] = {
#define ETM_COUNTER(i) \
		{ ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
				"ETM_counter_" #i "_reload_value", }, \
		{ ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
				"ETM_counter_" #i "_enable", }, \
		{ ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
				"ETM_counter_" #i "_reload_event", }, \
		{ ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
				"ETM_counter_" #i "_value", }
	ETM_COUNTER(1),
	ETM_COUNTER(2),
	ETM_COUNTER(3),
	ETM_COUNTER(4),
	{ 0, 0, 0, 0, NULL }
#undef ETM_COUNTER
};

static const struct etm_reg_info etm_sequencer[] = {
#define ETM_SEQ(i) \
		{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
				"ETM_sequencer_event" #i, }
	ETM_SEQ(0),				/* 1->2 */
	ETM_SEQ(1),				/* 2->1 */
	ETM_SEQ(2),				/* 2->3 */
	ETM_SEQ(3),				/* 3->1 */
	ETM_SEQ(4),				/* 3->2 */
	ETM_SEQ(5),				/* 1->3 */
#undef ETM_SEQ
	/* 0x66 reserved */
	{ ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
};

static const struct etm_reg_info etm_outputs[] = {
#define ETM_OUTPUT(i) \
		{ ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
				"ETM_external_output" #i, }

	ETM_OUTPUT(1),
	ETM_OUTPUT(2),
	ETM_OUTPUT(3),
	ETM_OUTPUT(4),
	{ 0, 0, 0, 0, NULL }
#undef ETM_OUTPUT
};

#if 0
	/* registers from 0x6c..0x7f were added after ETMv1.3 */

	/* Context ID Comparators */
	{ 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
	{ 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
	{ 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
	{ 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
#endif

static int etm_get_reg(struct reg *reg);
static int etm_read_reg_w_check(struct reg *reg,
	uint8_t *check_value, uint8_t *check_mask);
static int etm_register_user_commands(struct command_context *cmd_ctx);
static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
static int etm_write_reg(struct reg *reg, uint32_t value);

static const struct reg_arch_type etm_scan6_type = {
	.get = etm_get_reg,
	.set = etm_set_reg_w_exec,
};

/* Look up register by ID ... most ETM instances only
 * support a subset of the possible registers.
 */
static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
{
	struct reg_cache *cache = etm_ctx->reg_cache;
	unsigned i;

	for (i = 0; i < cache->num_regs; i++) {
		struct etm_reg *reg = cache->reg_list[i].arch_info;

		if (reg->reg_info->addr == id)
			return &cache->reg_list[i];
	}

	/* caller asking for nonexistent register is a bug!
	 * REVISIT say which of the N targets was involved */
	LOG_ERROR("ETM: register 0x%02x not available", id);
	return NULL;
}

static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
	struct reg_cache *cache, struct etm_reg *ereg,
	const struct etm_reg_info *r, unsigned nreg)
{
	struct reg *reg = cache->reg_list;

	reg += cache->num_regs;
	ereg += cache->num_regs;

	/* add up to "nreg" registers from "r", if supported by this
	 * version of the ETM, to the specified cache.
	 */
	for (; nreg--; r++) {
		/* No more registers to add */
		if (!r->size) {
			LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
			return;
		}

		/* this ETM may be too old to have some registers */
		if (r->bcd_vers > bcd_vers)
			continue;

		reg->name = r->name;
		reg->size = r->size;
		reg->value = &ereg->value;
		reg->arch_info = ereg;
		reg->type = &etm_scan6_type;
		reg++;
		cache->num_regs++;

		ereg->reg_info = r;
		ereg->jtag_info = jtag_info;
		ereg++;
	}
}

struct reg_cache *etm_build_reg_cache(struct target *target,
	struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
{
	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
	struct reg *reg_list = NULL;
	struct etm_reg *arch_info = NULL;
	unsigned bcd_vers, config;

	/* the actual registers are kept in two arrays */
	reg_list = calloc(128, sizeof(struct reg));
	arch_info = calloc(128, sizeof(struct etm_reg));

	/* fill in values for the reg cache */
	reg_cache->name = "etm registers";
	reg_cache->next = NULL;
	reg_cache->reg_list = reg_list;
	reg_cache->num_regs = 0;

	/* add ETM_CONFIG, then parse its values to see
	 * which other registers exist in this ETM
	 */
	etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
		etm_core, 1);

	etm_get_reg(reg_list);
	etm_ctx->config = buf_get_u32(arch_info->value, 0, 32);
	config = etm_ctx->config;

	/* figure ETM version then add base registers */
	if (config & (1 << 31)) {
		LOG_WARNING("ETMv2+ support is incomplete");

		/* REVISIT more registers may exist; they may now be
		 * readable; more register bits have defined meanings;
		 * don't presume trace start/stop support is present;
		 * and include any context ID comparator registers.
		 */
		etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
			etm_core + 1, 1);
		etm_get_reg(reg_list + 1);
		etm_ctx->id = buf_get_u32(
				arch_info[1].value, 0, 32);
		LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
		bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);

	} else {
		switch (config >> 28) {
			case 7:
			case 5:
			case 3:
				bcd_vers = 0x13;
				break;
			case 4:
			case 2:
				bcd_vers = 0x12;
				break;
			case 1:
				bcd_vers = 0x11;
				break;
			case 0:
				bcd_vers = 0x10;
				break;
			default:
				LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
				goto fail;
		}
	}
	etm_ctx->bcd_vers = bcd_vers;
	LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);

	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
		etm_basic, ARRAY_SIZE(etm_basic));

	/* address and data comparators; counters; outputs */
	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
		etm_addr_comp, 4 * (0x0f & (config >> 0)));
	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
		etm_data_comp, 2 * (0x0f & (config >> 4)));
	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
		etm_counters, 4 * (0x07 & (config >> 13)));
	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
		etm_outputs, (0x07 & (config >> 20)));

	/* FIFOFULL presence is optional
	 * REVISIT for ETMv1.2 and later, don't bother adding this
	 * unless ETM_SYS_CONFIG says it's also *supported* ...
	 */
	if (config & (1 << 23))
		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
			etm_fifofull, ARRAY_SIZE(etm_fifofull));

	/* sequencer is optional (for state-dependant triggering) */
	if (config & (1 << 16))
		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
			etm_sequencer, ARRAY_SIZE(etm_sequencer));

	/* REVISIT could realloc and likely save half the memory
	 * in the two chunks we allocated...
	 */

	/* the ETM might have an ETB connected */
	if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
		struct etb *etb = etm_ctx->capture_driver_priv;

		if (!etb) {
			LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
			goto fail;
		}

		reg_cache->next = etb_build_reg_cache(etb);

		etb->reg_cache = reg_cache->next;
	}

	etm_ctx->reg_cache = reg_cache;
	return reg_cache;

fail:
	free(reg_cache);
	free(reg_list);
	free(arch_info);
	return NULL;
}

static int etm_read_reg(struct reg *reg)
{
	return etm_read_reg_w_check(reg, NULL, NULL);
}

static int etm_store_reg(struct reg *reg)
{
	return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}

int etm_setup(struct target *target)
{
	int retval;
	uint32_t etm_ctrl_value;
	struct arm *arm = target_to_arm(target);
	struct etm_context *etm_ctx = arm->etm;
	struct reg *etm_ctrl_reg;

	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
	if (!etm_ctrl_reg)
		return ERROR_OK;

	/* initialize some ETM control register settings */
	etm_get_reg(etm_ctrl_reg);
	etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);

	/* clear the ETM powerdown bit (0) */
	etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;

	/* configure port width (21,6:4), mode (13,17:16) and
	 * for older modules clocking (13)
	 */
	etm_ctrl_value = (etm_ctrl_value
		& ~ETM_PORT_WIDTH_MASK
		& ~ETM_PORT_MODE_MASK
		& ~ETM_CTRL_DBGRQ
		& ~ETM_PORT_CLOCK_MASK)
		| etm_ctx->control;

	buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
	etm_store_reg(etm_ctrl_reg);

	etm_ctx->control = etm_ctrl_value;

	retval = jtag_execute_queue();
	if (retval != ERROR_OK)
		return retval;

	/* REVISIT for ETMv3.0 and later, read ETM_sys_config to
	 * verify that those width and mode settings are OK ...
	 */

	retval = etm_ctx->capture_driver->init(etm_ctx);
	if (retval != ERROR_OK) {
		LOG_ERROR("ETM capture driver initialization failed");
		return retval;
	}
	return ERROR_OK;
}

static int etm_get_reg(struct reg *reg)
{
	int retval;

	retval = etm_read_reg(reg);
	if (retval != ERROR_OK) {
		LOG_ERROR("BUG: error scheduling etm register read");
		return retval;
	}

	retval = jtag_execute_queue();
	if (retval != ERROR_OK) {
		LOG_ERROR("register read failed");
		return retval;
	}

	return ERROR_OK;
}

static int etm_read_reg_w_check(struct reg *reg,
	uint8_t *check_value, uint8_t *check_mask)
{
	struct etm_reg *etm_reg = reg->arch_info;
	const struct etm_reg_info *r = etm_reg->reg_info;
	uint8_t reg_addr = r->addr & 0x7f;
	struct scan_field fields[3];
	int retval;

	if (etm_reg->reg_info->mode == WO) {
		LOG_ERROR("BUG: can't read write-only register %s", r->name);
		return ERROR_COMMAND_SYNTAX_ERROR;
	}

	LOG_DEBUG("%s (%u)", r->name, reg_addr);

	retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
	if (retval != ERROR_OK)
		return retval;
	retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
			etm_reg->jtag_info->intest_instr,
			NULL,
			TAP_IDLE);
	if (retval != ERROR_OK)
		return retval;

	fields[0].num_bits = 32;
	fields[0].out_value = reg->value;
	fields[0].in_value = NULL;
	fields[0].check_value = NULL;
	fields[0].check_mask = NULL;

	fields[1].num_bits = 7;
	uint8_t temp1;
	fields[1].out_value = &temp1;
	buf_set_u32(&temp1, 0, 7, reg_addr);
	fields[1].in_value = NULL;
	fields[1].check_value = NULL;
	fields[1].check_mask = NULL;

	fields[2].num_bits = 1;
	uint8_t temp2;
	fields[2].out_value = &temp2;
	buf_set_u32(&temp2, 0, 1, 0);
	fields[2].in_value = NULL;
	fields[2].check_value = NULL;
	fields[2].check_mask = NULL;

	jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);

	fields[0].in_value = reg->value;
	fields[0].check_value = check_value;
	fields[0].check_mask = check_mask;

	jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);

	return ERROR_OK;
}

static int etm_set_reg(struct reg *reg, uint32_t value)
{
	int retval = etm_write_reg(reg, value);
	if (retval != ERROR_OK) {
		LOG_ERROR("BUG: error scheduling etm register write");
		return retval;
	}

	buf_set_u32(reg->value, 0, reg->size, value);
	reg->valid = 1;
	reg->dirty = 0;

	return ERROR_OK;
}

static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
{
	int retval;

	etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));

	retval = jtag_execute_queue();
	if (retval != ERROR_OK) {
		LOG_ERROR("register write failed");
		return retval;
	}
	return ERROR_OK;
}

static int etm_write_reg(struct reg *reg, uint32_t value)
{
	struct etm_reg *etm_reg = reg->arch_info;
	const struct etm_reg_info *r = etm_reg->reg_info;
	uint8_t reg_addr = r->addr & 0x7f;
	struct scan_field fields[3];
	int retval;

	if (etm_reg->reg_info->mode == RO) {
		LOG_ERROR("BUG: can't write read--only register %s", r->name);
		return ERROR_COMMAND_SYNTAX_ERROR;
	}

	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);

	retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
	if (retval != ERROR_OK)
		return retval;
	retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
			etm_reg->jtag_info->intest_instr,
			NULL,
			TAP_IDLE);
	if (retval != ERROR_OK)
		return retval;

	fields[0].num_bits = 32;
	uint8_t tmp1[4];
	fields[0].out_value = tmp1;
	buf_set_u32(tmp1, 0, 32, value);
	fields[0].in_value = NULL;

	fields[1].num_bits = 7;
	uint8_t tmp2;
	fields[1].out_value = &tmp2;
	buf_set_u32(&tmp2, 0, 7, reg_addr);
	fields[1].in_value = NULL;

	fields[2].num_bits = 1;
	uint8_t tmp3;
	fields[2].out_value = &tmp3;
	buf_set_u32(&tmp3, 0, 1, 1);
	fields[2].in_value = NULL;

	jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);

	return ERROR_OK;
}


/* ETM trace analysis functionality */

static struct etm_capture_driver *etm_capture_drivers[] = {
	&etb_capture_driver,
	&etm_dummy_capture_driver,
#if BUILD_OOCD_TRACE == 1
	&oocd_trace_capture_driver,
#endif
	NULL
};

static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
{
	int i;
	int section = -1;
	size_t size_read;
	uint32_t opcode;
	int retval;

	if (!ctx->image)
		return ERROR_TRACE_IMAGE_UNAVAILABLE;

	/* search for the section the current instruction belongs to */
	for (i = 0; i < ctx->image->num_sections; i++) {
		if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
			(ctx->image->sections[i].base_address + ctx->image->sections[i].size >
			ctx->current_pc)) {
			section = i;
			break;
		}
	}

	if (section == -1) {
		/* current instruction couldn't be found in the image */
		return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
	}

	if (ctx->core_state == ARM_STATE_ARM) {
		uint8_t buf[4];
		retval = image_read_section(ctx->image, section,
				ctx->current_pc -
				ctx->image->sections[section].base_address,
				4, buf, &size_read);
		if (retval != ERROR_OK) {
			LOG_ERROR("error while reading instruction");
			return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
		}
		opcode = target_buffer_get_u32(ctx->target, buf);
		arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
	} else if (ctx->core_state == ARM_STATE_THUMB) {
		uint8_t buf[2];
		retval = image_read_section(ctx->image, section,
				ctx->current_pc -
				ctx->image->sections[section].base_address,
				2, buf, &size_read);
		if (retval != ERROR_OK) {
			LOG_ERROR("error while reading instruction");
			return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
		}
		opcode = target_buffer_get_u16(ctx->target, buf);
		thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
	} else if (ctx->core_state == ARM_STATE_JAZELLE) {
		LOG_ERROR("BUG: tracing of jazelle code not supported");
		return ERROR_FAIL;
	} else {
		LOG_ERROR("BUG: unknown core state encountered");
		return ERROR_FAIL;
	}

	return ERROR_OK;
}

static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
{
	while (ctx->data_index < ctx->trace_depth) {
		/* if the caller specified an address packet offset, skip until the
		 * we reach the n-th cycle marked with tracesync */
		if (apo > 0) {
			if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
				apo--;

			if (apo > 0) {
				ctx->data_index++;
				ctx->data_half = 0;
			}
			continue;
		}

		/* no tracedata output during a TD cycle
		 * or in a trigger cycle */
		if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
			|| (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
			ctx->data_index++;
			ctx->data_half = 0;
			continue;
		}

		/* FIXME there are more port widths than these... */
		if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
			if (ctx->data_half == 0) {
				*packet = ctx->trace_data[ctx->data_index].packet & 0xff;
				ctx->data_half = 1;
			} else {
				*packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
				ctx->data_half = 0;
				ctx->data_index++;
			}
		} else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
			*packet = ctx->trace_data[ctx->data_index].packet & 0xff;
			ctx->data_index++;
		} else {
			/* on a 4-bit port, a packet will be output during two consecutive cycles */
			if (ctx->data_index > (ctx->trace_depth - 2))
				return -1;

			*packet = ctx->trace_data[ctx->data_index].packet & 0xf;
			*packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
			ctx->data_index += 2;
		}

		return 0;
	}

	return -1;
}

static int etmv1_branch_address(struct etm_context *ctx)
{
	int retval;
	uint8_t packet;
	int shift = 0;
	int apo;
	uint32_t i;

	/* quit analysis if less than two cycles are left in the trace
	 * because we can't extract the APO */
	if (ctx->data_index > (ctx->trace_depth - 2))
		return -1;

	/* a BE could be output during an APO cycle, skip the current
	 * and continue with the new one */
	if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
		return 1;
	if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
		return 2;

	/* address packet offset encoded in the next two cycles' pipestat bits */
	apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
	apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;

	/* count number of tracesync cycles between current pipe_index and data_index
	 * i.e. the number of tracesyncs that data_index already passed by
	 * to subtract them from the APO */
	for (i = ctx->pipe_index; i < ctx->data_index; i++) {
		if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
			apo--;
	}

	/* extract up to four 7-bit packets */
	do {
		retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
		if (retval != 0)
			return -1;
		ctx->last_branch &= ~(0x7f << shift);
		ctx->last_branch |= (packet & 0x7f) << shift;
		shift += 7;
	} while ((packet & 0x80) && (shift < 28));

	/* one last packet holding 4 bits of the address, plus the branch reason code */
	if ((shift == 28) && (packet & 0x80)) {
		retval = etmv1_next_packet(ctx, &packet, 0);
		if (retval != 0)
			return -1;
		ctx->last_branch &= 0x0fffffff;
		ctx->last_branch |= (packet & 0x0f) << 28;
		ctx->last_branch_reason = (packet & 0x70) >> 4;
		shift += 4;
	} else
		ctx->last_branch_reason = 0;

	if (shift == 32)
		ctx->pc_ok = 1;

	/* if a full address was output, we might have branched into Jazelle state */
	if ((shift == 32) && (packet & 0x80))
		ctx->core_state = ARM_STATE_JAZELLE;
	else {
		/* if we didn't branch into Jazelle state, the current processor state is
		 * encoded in bit 0 of the branch target address */
		if (ctx->last_branch & 0x1) {
			ctx->core_state = ARM_STATE_THUMB;
			ctx->last_branch &= ~0x1;
		} else {
			ctx->core_state = ARM_STATE_ARM;
			ctx->last_branch &= ~0x3;
		}
	}

	return 0;
}

static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
{
	int j;
	uint8_t buf[4];
	int retval;

	for (j = 0; j < size; j++) {
		retval = etmv1_next_packet(ctx, &buf[j], 0);
		if (retval != 0)
			return -1;
	}

	if (size == 8) {
		LOG_ERROR("TODO: add support for 64-bit values");
		return -1;
	} else if (size == 4)
		*data = target_buffer_get_u32(ctx->target, buf);
	else if (size == 2)
		*data = target_buffer_get_u16(ctx->target, buf);
	else if (size == 1)
		*data = buf[0];
	else
		return -1;

	return 0;
}

static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
{
	int retval;
	struct arm_instruction instruction;

	/* read the trace data if it wasn't read already */
	if (ctx->trace_depth == 0)
		ctx->capture_driver->read_trace(ctx);

	if (ctx->trace_depth == 0) {
		command_print(cmd_ctx, "Trace is empty.");
		return ERROR_OK;
	}

	/* start at the beginning of the captured trace */
	ctx->pipe_index = 0;
	ctx->data_index = 0;
	ctx->data_half = 0;

	/* neither the PC nor the data pointer are valid */
	ctx->pc_ok = 0;
	ctx->ptr_ok = 0;

	while (ctx->pipe_index < ctx->trace_depth) {
		uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
		uint32_t next_pc = ctx->current_pc;
		uint32_t old_data_index = ctx->data_index;
		uint32_t old_data_half = ctx->data_half;
		uint32_t old_index = ctx->pipe_index;
		uint32_t last_instruction = ctx->last_instruction;
		uint32_t cycles = 0;
		int current_pc_ok = ctx->pc_ok;

		if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
			command_print(cmd_ctx, "--- trigger ---");

		/* instructions execute in IE/D or BE/D cycles */
		if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
			ctx->last_instruction = ctx->pipe_index;

		/* if we don't have a valid pc skip until we reach an indirect branch */
		if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
			ctx->pipe_index++;
			continue;
		}

		/* any indirect branch could have interrupted instruction flow
		 * - the branch reason code could indicate a trace discontinuity
		 * - a branch to the exception vectors indicates an exception
		 */
		if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
			/* backup current data index, to be able to consume the branch address
			 * before examining data address and values
			 */
			old_data_index = ctx->data_index;
			old_data_half = ctx->data_half;

			ctx->last_instruction = ctx->pipe_index;

			retval = etmv1_branch_address(ctx);
			if (retval != 0) {
				/* negative return value from etmv1_branch_address means we ran out of packets,
				 * quit analysing the trace */
				if (retval < 0)
					break;

				/* a positive return values means the current branch was abandoned,
				 * and a new branch was encountered in cycle ctx->pipe_index + retval;
				 */
				LOG_WARNING(
					"abandoned branch encountered, correctness of analysis uncertain");
				ctx->pipe_index += retval;
				continue;
			}

			/* skip over APO cycles */
			ctx->pipe_index += 2;

			switch (ctx->last_branch_reason) {
				case 0x0:	/* normal PC change */
					next_pc = ctx->last_branch;
					break;
				case 0x1:	/* tracing enabled */
					command_print(cmd_ctx,
						"--- tracing enabled at 0x%8.8" PRIx32 " ---",
						ctx->last_branch);
					ctx->current_pc = ctx->last_branch;
ofs	hex dump	ascii
0000	ca fe ba be 00 00 00 31 00 97 07 00 02 01 00 1c 6a 61 76 61 2f 75 74 69 6c 2f 41 62 73 74 72 61	.......1........java/util/Abstra
0020	63 74 43 6f 6c 6c 65 63 74 69 6f 6e 07 00 04 01 00 10 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65	ctCollection......java/lang/Obje
0040	63 74 07 00 06 01 00 14 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 07 00 08 01	ct......java/util/Collection....
0060	00 12 6a 61 76 61 2f 6c 61 6e 67 2f 49 74 65 72 61 62 6c 65 01 00 06 3c 69 6e 69 74 3e 01 00 03	..java/lang/Iterable...<init>...
0080	28 29 56 01 00 04 43 6f 64 65 0a 00 03 00 0d 0c 00 09 00 0a 01 00 0f 4c 69 6e 65 4e 75 6d 62 65	()V...Code.............LineNumbe
00a0	72 54 61 62 6c 65 01 00 12 4c 6f 63 61 6c 56 61 72 69 61 62 6c 65 54 61 62 6c 65 01 00 04 74 68	rTable...LocalVariableTable...th
00c0	69 73 01 00 1e 4c 6a 61 76 61 2f 75 74 69 6c 2f 41 62 73 74 72 61 63 74 43 6f 6c 6c 65 63 74 69	is...Ljava/util/AbstractCollecti
00e0	6f 6e 3b 01 00 16 4c 6f 63 61 6c 56 61 72 69 61 62 6c 65 54 79 70 65 54 61 62 6c 65 01 00 23 4c	on;...LocalVariableTypeTable..#L
0100	6a 61 76 61 2f 75 74 69 6c 2f 41 62 73 74 72 61 63 74 43 6f 6c 6c 65 63 74 69 6f 6e 3c 54 45 3b	java/util/AbstractCollection<TE;
0120	3e 3b 01 00 08 69 74 65 72 61 74 6f 72 01 00 16 28 29 4c 6a 61 76 61 2f 75 74 69 6c 2f 49 74 65	>;...iterator...()Ljava/util/Ite
0140	72 61 74 6f 72 3b 01 00 09 53 69 67 6e 61 74 75 72 65 01 00 1b 28 29 4c 6a 61 76 61 2f 75 74 69	rator;...Signature...()Ljava/uti
0160	6c 2f 49 74 65 72 61 74 6f 72 3c 54 45 3b 3e 3b 01 00 04 73 69 7a 65 01 00 03 28 29 49 01 00 03	l/Iterator<TE;>;...size...()I...
0180	61 64 64 01 00 15 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 29 5a 01 00 06 28 54	add...(Ljava/lang/Object;)Z...(T
01a0	45 3b 29 5a 07 00 1e 01 00 27 6a 61 76 61 2f 6c 61 6e 67 2f 55 6e 73 75 70 70 6f 72 74 65 64 4f	E;)Z.....'java/lang/UnsupportedO
01c0	70 65 72 61 74 69 6f 6e 45 78 63 65 70 74 69 6f 6e 0a 00 1d 00 0d 01 00 01 6f 01 00 12 4c 6a 61	perationException........o...Lja
01e0	76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 01 00 03 54 45 3b 01 00 06 61 64 64 41 6c 6c 01 00	va/lang/Object;...TE;...addAll..
0200	19 28 4c 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 3b 29 5a 01 00 1f 28 4c 6a	.(Ljava/util/Collection;)Z...(Lj
0220	61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 3c 2b 54 45 3b 3e 3b 29 5a 0b 00 05 00	ava/util/Collection<+TE;>;)Z....
0240	27 0c 00 14 00 15 0b 00 05 00 29 0c 00 18 00 19 0b 00 2b 00 2d 07 00 2c 01 00 12 6a 61 76 61 2f	'.........).......+.-..,...java/
0260	75 74 69 6c 2f 49 74 65 72 61 74 6f 72 0c 00 2e 00 2f 01 00 04 6e 65 78 74 01 00 14 28 29 4c 6a	util/Iterator..../...next...()Lj
0280	61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 0a 00 01 00 31 0c 00 1a 00 1b 01 00 01 63 01 00	ava/lang/Object;....1........c..
02a0	16 4c 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 3b 01 00 03 69 74 72 01 00 14	.Ljava/util/Collection;...itr...
02c0	4c 6a 61 76 61 2f 75 74 69 6c 2f 49 74 65 72 61 74 6f 72 3b 01 00 08 6d 6f 64 69 66 69 65 64 01	Ljava/util/Iterator;...modified.
02e0	00 01 5a 01 00 03 70 6f 73 01 00 01 49 01 00 1c 4c 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65	..Z...pos...I...Ljava/util/Colle
0300	63 74 69 6f 6e 3c 2b 54 45 3b 3e 3b 01 00 1a 4c 6a 61 76 61 2f 75 74 69 6c 2f 49 74 65 72 61 74	ction<+TE;>;...Ljava/util/Iterat
0320	6f 72 3c 2b 54 45 3b 3e 3b 01 00 05 63 6c 65 61 72 0a 00 01 00 27 0a 00 01 00 29 0b 00 2b 00 40	or<+TE;>;...clear....'....)..+.@
0340	0c 00 41 00 0a 01 00 06 72 65 6d 6f 76 65 01 00 19 4c 6a 61 76 61 2f 75 74 69 6c 2f 49 74 65 72	..A.....remove...Ljava/util/Iter
0360	61 74 6f 72 3c 54 45 3b 3e 3b 01 00 08 63 6f 6e 74 61 69 6e 73 0a 00 01 00 45 0c 00 46 00 47 01	ator<TE;>;...contains....E..F.G.
0380	00 06 65 71 75 61 6c 73 01 00 27 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 4c 6a	..equals..'(Ljava/lang/Object;Lj
03a0	61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 29 5a 01 00 0b 63 6f 6e 74 61 69 6e 73 41 6c 6c	ava/lang/Object;)Z...containsAll
03c0	01 00 1c 28 4c 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 3c 2a 3e 3b 29 5a 0a	...(Ljava/util/Collection<*>;)Z.
03e0	00 01 00 4b 0c 00 43 00 1b 01 00 19 4c 6a 61 76 61 2f 75 74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f	...K..C.....Ljava/util/Collectio
0400	6e 3c 2a 3e 3b 01 00 17 4c 6a 61 76 61 2f 75 74 69 6c 2f 49 74 65 72 61 74 6f 72 3c 2a 3e 3b 01	n<>;...Ljava/util/Iterator<>;.
0420	00 07 69 73 45 6d 70 74 79 01 00 03 28 29 5a 01 00 09 72 65 6d 6f 76 65 41 6c 6c 0a 00 01 00 52	..isEmpty...()Z...removeAll....R
0440	0c 00 53 00 24 01 00 11 72 65 6d 6f 76 65 41 6c 6c 49 6e 74 65 72 6e 61 6c 0b 00 05 00 4b 01 00	..S.$...removeAllInternal....K..
0460	09 72 65 74 61 69 6e 41 6c 6c 0a 00 01 00 57 0c 00 58 00 24 01 00 11 72 65 74 61 69 6e 41 6c 6c	.retainAll....W..X.$...retainAll
0480	49 6e 74 65 72 6e 61 6c 01 00 07 74 6f 41 72 72 61 79 01 00 15 28 29 5b 4c 6a 61 76 61 2f 6c 61	Internal...toArray...()[Ljava/la
04a0	6e 67 2f 4f 62 6a 65 63 74 3b 01 00 01 61 01 00 13 5b 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a	ng/Object;...a...[Ljava/lang/Obj
04c0	65 63 74 3b 01 00 28 28 5b 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 29 5b 4c 6a 61	ect;..(([Ljava/lang/Object;)[Lja
04e0	76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 01 00 20 3c 54 3a 4c 6a 61 76 61 2f 6c 61 6e 67 2f	va/lang/Object;...<T:Ljava/lang/
0500	4f 62 6a 65 63 74 3b 3e 28 5b 54 54 3b 29 5b 54 54 3b 0a 00 03 00 60 0c 00 61 00 62 01 00 08 67	Object;>([TT;)[TT;....`..a.b...g
0520	65 74 43 6c 61 73 73 01 00 13 28 29 4c 6a 61 76 61 2f 6c 61 6e 67 2f 43 6c 61 73 73 3b 0a 00 64	etClass...()Ljava/lang/Class;..d
0540	00 66 07 00 65 01 00 0f 6a 61 76 61 2f 6c 61 6e 67 2f 43 6c 61 73 73 0c 00 67 00 62 01 00 10 67	.f..e...java/lang/Class..g.b...g
0560	65 74 43 6f 6d 70 6f 6e 65 6e 74 54 79 70 65 0a 00 69 00 6b 07 00 6a 01 00 17 6a 61 76 61 2f 6c	etComponentType..i.k..j...java/l
0580	61 6e 67 2f 72 65 66 6c 65 63 74 2f 41 72 72 61 79 0c 00 6c 00 6d 01 00 0b 6e 65 77 49 6e 73 74	ang/reflect/Array..l.m...newInst
05a0	61 6e 63 65 01 00 26 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f 43 6c 61 73 73 3b 49 29 4c 6a 61 76 61	ance..&(Ljava/lang/Class;I)Ljava
05c0	2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 07 00 5c 01 00 08 74 6f 53 74 72 69 6e 67 01 00 14 28 29	/lang/Object;..\...toString...()
05e0	4c 6a 61 76 61 2f 6c 61 6e 67 2f 53 74 72 69 6e 67 3b 07 00 72 01 00 1d 67 6e 75 2f 6a 61 76 61	Ljava/lang/String;..r...gnu/java
0600	2f 6c 61 6e 67 2f 43 50 53 74 72 69 6e 67 42 75 69 6c 64 65 72 08 00 74 01 00 01 5b 0a 00 71 00	/lang/CPStringBuilder..t...[..q.
0620	76 0c 00 09 00 77 01 00 15 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f 53 74 72 69 6e 67 3b 29 56 0b 00	v....w...(Ljava/lang/String;)V..
0640	2b 00 79 0c 00 7a 00 4f 01 00 07 68 61 73 4e 65 78 74 08 00 7c 01 00 06 3c 74 68 69 73 3e 0a 00	+.y..z.O...hasNext..\|...<this>..
0660	71 00 7e 0c 00 7f 00 80 01 00 06 61 70 70 65 6e 64 01 00 33 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f	q.~........append..3(Ljava/lang/
0680	53 74 72 69 6e 67 3b 29 4c 67 6e 75 2f 6a 61 76 61 2f 6c 61 6e 67 2f 43 50 53 74 72 69 6e 67 42	String;)Lgnu/java/lang/CPStringB
06a0	75 69 6c 64 65 72 3b 0a 00 71 00 82 0c 00 7f 00 83 01 00 33 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f	uilder;..q.........3(Ljava/lang/
06c0	4f 62 6a 65 63 74 3b 29 4c 67 6e 75 2f 6a 61 76 61 2f 6c 61 6e 67 2f 43 50 53 74 72 69 6e 67 42	Object;)Lgnu/java/lang/CPStringB
06e0	75 69 6c 64 65 72 3b 08 00 85 01 00 02 2c 20 08 00 87 01 00 01 5d 0a 00 71 00 89 0c 00 6f 00 70	uilder;......,.......]..q....o.p
0700	01 00 01 72 01 00 1f 4c 67 6e 75 2f 6a 61 76 61 2f 6c 61 6e 67 2f 43 50 53 74 72 69 6e 67 42 75	...r...Lgnu/java/lang/CPStringBu
0720	69 6c 64 65 72 3b 0a 00 03 00 8d 0c 00 46 00 1b 01 00 02 6f 31 01 00 02 6f 32 01 00 08 68 61 73	ilder;.......F.....o1...o2...has
0740	68 43 6f 64 65 01 00 15 28 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 29 49 0a 00 03	hCode...(Ljava/lang/Object;)I...
0760	00 93 0c 00 90 00 19 01 00 0a 53 6f 75 72 63 65 46 69 6c 65 01 00 17 41 62 73 74 72 61 63 74 43	..........SourceFile...AbstractC
0780	6f 6c 6c 65 63 74 69 6f 6e 2e 6a 61 76 61 01 00 5c 3c 45 3a 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f	ollection.java..\<E:Ljava/lang/O
07a0	62 6a 65 63 74 3b 3e 4c 6a 61 76 61 2f 6c 61 6e 67 2f 4f 62 6a 65 63 74 3b 4c 6a 61 76 61 2f 75	bject;>Ljava/lang/Object;Ljava/u
07c0	74 69 6c 2f 43 6f 6c 6c 65 63 74 69 6f 6e 3c 54 45 3b 3e 3b 4c 6a 61 76 61 2f 6c 61 6e 67 2f 49	til/Collection<TE;>;Ljava/lang/I
07e0	74 65 72 61 62 6c 65 3c 54 45 3b 3e 3b 04 21 00 01 00 03 00 02 00 05 00 07 00 00 00 13 00 04 00	terable<TE;>;.!.................
0800	09 00 0a 00 01 00 0b 00 00 00 45 00 01 00 01 00 00 00 05 2a b7 00 0c b1 00 00 00 03 00 0e 00 00	..........E........*............
0820	00 0a 00 02 00 00 00 51 00 04 00 53 00 0f 00 00 00 0c 00 01 00 00 00 05 00 10 00 11 00 00 00 12	.......Q...S....................
0840	00 00 00 0c 00 01 00 00 00 05 00 10 00 13 00 00 04 01 00 14 00 15 00 01 00 16 00 00 00 02 00 17	................................
0860	04 01 00 18 00 19 00 00 00 01 00 1a 00 1b 00 02 00 16 00 00 00 02 00 1c 00 0b 00 00 00 58 00 02	.............................X..
0880	00 02 00 00 00 08 bb 00 1d 59 b7 00 1f bf 00 00 00 03 00 0e 00 00 00 06 00 01 00 00 00 78 00 0f	.........Y...................x..
08a0	00 00 00 16 00 02 00 00 00 08 00 10 00 11 00 00 00 00 00 08 00 20 00 21 00 01 00 12 00 00 00 16	.......................!........
08c0	00 02 00 00 00 08 00 10 00 13 00 00 00 00 00 08 00 20 00 22 00 01 00 01 00 23 00 24 00 02 00 16	...................".....#.$....
08e0	00 00 00 02 00 25 00 0b 00 00 00 bb 00 03 00 05 00 00 00 2b 2b b9 00 26 01 00 4d 03 3e 2b b9 00	.....%.............++..&..M.>+..
0900	28 01 00 36 04 a7 00 10 1d 2a 2c b9 00 2a 01 00 b6 00 30 80 3e 84 04 ff 15 04 9c ff ee 1d ac 00	(..6.....,......0.>...........
0920	00 00 03 00 0e 00 00 00 1e 00 07 00 00 00 94 00 07 00 95 00 09 00 96 00 11 00 97 00 14 00 98 00	................................
0940	21 00 97 00 29 00 99 00 0f 00 00 00 34 00 05 00 00 00 2b 00 10 00 11 00 00 00 00 00 2b 00 32 00	!...).......4.....+.........+.2.
0960	33 00 01 00 07 00 24 00 34 00 35 00 02 00 09 00 22 00 36 00 37 00 03 00 11 00 1a 00 38 00 39 00	3.....$.4.5.....".6.7.......8.9.
0980	04 00 12 00 00 00 20 00 03 00 00 00 2b 00 10 00 13 00 00 00 00 00 2b 00 32 00 3a 00 01 00 07 00	............+.........+.2.:.....
09a0	24 00 34 00 3b 00 02 00 01 00 3c 00 0a 00 01 00 0b 00 00 00 94 00 01 00 03 00 00 00 22 2a b6 00	$.4.;.....<................."*..
09c0	3d 4c 2a b6 00 3e 3d a7 00 10 2b b9 00 2a 01 00 57 2b b9 00 3f 01 00 84 02 ff 1c 9c ff ef b1 00	=L..>=...+....W+..?...........
09e0	00 00 03 00 0e 00 00 00 1e 00 07 00 00 00 aa 00 05 00 ab 00 0a 00 ac 00 0d 00 ae 00 14 00 af 00	................................
0a00	1a 00 ac 00 21 00 b1 00 0f 00 00 00 20 00 03 00 00 00 22 00 10 00 11 00 00 00 05 00 1d 00 34 00	....!............."...........4.
0a20	35 00 01 00 0a 00 18 00 38 00 39 00 02 00 12 00 00 00 16 00 02 00 00 00 22 00 10 00 13 00 00 00	5.......8.9.............".......
0a40	05 00 1d 00 34 00 42 00 01 00 01 00 43 00 1b 00 01 00 0b 00 00 00 a1 00 02 00 04 00 00 00 25 2a	....4.B.....C.................%*
0a60	b6 00 3d 4d 2a b6 00 3e 3e a7 00 12 2b 2c b9 00 2a 01 00 b8 00 44 99 00 05 04 ac 84 03 ff 1d 9c	..=M..>>...+,......D..........
0a80	ff ed 03 ac 00 00 00 03 00 0e 00 00 00 1e 00 07 00 00 00 c0 00 05 00 c1 00 0a 00 c2 00 0d 00 c3	................................
0aa0	00 1a 00 c4 00 1c 00 c2 00 23 00 c5 00 0f 00 00 00 2a 00 04 00 00 00 25 00 10 00 11 00 00 00 00	.........#.......*.....%........
0ac0	00 25 00 20 00 21 00 01 00 05 00 20 00 34 00 35 00 02 00 0a 00 1b 00 38 00 39 00 03 00 12 00 00	.%...!.......4.5.......8.9......
0ae0	00 16 00 02 00 00 00 25 00 10 00 13 00 00 00 05 00 20 00 34 00 42 00 02 00 01 00 48 00 24 00 02	.......%...........4.B.....H.$..
0b00	00 16 00 00 00 02 00 49 00 0b 00 00 00 af 00 02 00 04 00 00 00 29 2b b9 00 26 01 00 4d 2b b9 00	.......I.............)+..&..M+..
0b20	28 01 00 3e a7 00 12 2a 2c b9 00 2a 01 00 b6 00 4a 9a 00 05 03 ac 84 03 ff 1d 9c ff ed 04 ac 00	(..>...,......J...............
0b40	00 00 03 00 0e 00 00 00 1e 00 07 00 00 00 d6 00 07 00 d7 00 0e 00 d8 00 11 00 d9 00 1e 00 da 00	................................
0b60	20 00 d8 00 27 00 db 00 0f 00 00 00 2a 00 04 00 00 00 29 00 10 00 11 00 00 00 00 00 29 00 32 00	....'.......*.....).........).2.
0b80	33 00 01 00 07 00 22 00 34 00 35 00 02 00 0e 00 1b 00 38 00 39 00 03 00 12 00 00 00 20 00 03 00	3.....".4.5.......8.9...........
0ba0	00 00 29 00 10 00 13 00 00 00 00 00 29 00 32 00 4c 00 01 00 07 00 22 00 34 00 4d 00 02 00 01 00	..).........).2.L.....".4.M.....
0bc0	4e 00 4f 00 01 00 0b 00 00 00 47 00 01 00 01 00 00 00 0b 2a b6 00 3e 9a 00 05 04 ac 03 ac 00 00	N.O.......G........*..>.........
0be0	00 03 00 0e 00 00 00 06 00 01 00 00 00 e7 00 0f 00 00 00 0c 00 01 00 00 00 0b 00 10 00 11 00 00	................................
0c00	00 12 00 00 00 0c 00 01 00 00 00 0b 00 10 00 13 00 00 00 01 00 41 00 1b 00 01 00 0b 00 00 00 ab	.....................A..........
0c20	00 02 00 04 00 00 00 2b 2a b6 00 3d 4d 2a b6 00 3e 3e a7 00 18 2b 2c b9 00 2a 01 00 b8 00 44 99	.......+..=M..>>...+,..*....D.
0c40	00 0b 2c b9 00 3f 01 00 04 ac 84 03 ff 1d 9c ff e7 03 ac 00 00 00 03 00 0e 00 00 00 22 00 08 00	..,..?......................"...
0c60	00 00 ff 00 05 01 00 00 0a 01 01 00 0d 01 02 00 1a 01 04 00 20 01 05 00 22 01 01 00 29 01 07 00	........................"...)...
0c80	0f 00 00 00 2a 00 04 00 00 00 2b 00 10 00 11 00 00 00 00 00 2b 00 20 00 21 00 01 00 05 00 26 00	....*.....+.........+...!.....&.
0ca0	34 00 35 00 02 00 0a 00 21 00 38 00 39 00 03 00 12 00 00 00 16 00 02 00 00 00 2b 00 10 00 13 00	4.5.....!.8.9.............+.....
0cc0	00 00 05 00 26 00 34 00 42 00 02 00 01 00 50 00 24 00 02 00 16 00 00 00 02 00 49 00 0b 00 00 00	....&.4.B.....P.$.........I.....
0ce0	56 00 02 00 02 00 00 00 06 2a 2b b6 00 51 ac 00 00 00 03 00 0e 00 00 00 06 00 01 00 00 01 1b 00	V........*+..Q..................
0d00	0f 00 00 00 16 00 02 00 00 00 06 00 10 00 11 00 00 00 00 00 06 00 32 00 33 00 01 00 12 00 00 00	......................2.3.......
0d20	16 00 02 00 00 00 06 00 10 00 13 00 00 00 00 00 06 00 32 00 4c 00 01 00 00 00 53 00 24 00 02 00	..................2.L.....S.$...
0d40	16 00 00 00 02 00 49 00 0b 00 00 00 c9 00 02 00 05 00 00 00 31 2a b6 00 3d 4d 03 3e 2a b6 00 3e	......I.............1..=M.>..>
0d60	36 04 a7 00 1a 2b 2c b9 00 2a 01 00 b9 00 54 02 00 99 00 0b 2c b9 00 3f 01 00 04 3e 84 04 ff 15	6....+,..*....T.....,..?...>....
0d80	04 9c ff e4 1d ac 00 00 00 03 00 0e 00 00 00 26 00 09 00 00 01 31 00 05 01 32 00 07 01 33 00 0d	...............&.....1...2...3..
0da0	01 34 00 10 01 35 00 1f 01 37 00 25 01 38 00 27 01 34 00 2f 01 3a 00 0f 00 00 00 34 00 05 00 00	.4...5...7.%.8.'.4./.:.....4....
0dc0	00 31 00 10 00 11 00 00 00 00 00 31 00 32 00 33 00 01 00 05 00 2c 00 34 00 35 00 02 00 07 00 2a	.1.........1.2.3.....,.4.5.....*
0de0	00 36 00 37 00 03 00 0d 00 24 00 38 00 39 00 04 00 12 00 00 00 20 00 03 00 00 00 31 00 10 00 13	.6.7.....$.8.9.............1....
0e00	00 00 00 00 00 31 00 32 00 4c 00 01 00 05 00 2c 00 34 00 42 00 02 00 01 00 55 00 24 00 02 00 16	.....1.2.L.....,.4.B.....U.$....
0e20	00 00 00 02 00 49 00 0b 00 00 00 56 00 02 00 02 00 00 00 06 2a 2b b6 00 56 ac 00 00 00 03 00 0e	.....I.....V........*+..V.......
0e40	00 00 00 06 00 01 00 00 01 4e 00 0f 00 00 00 16 00 02 00 00 00 06 00 10 00 11 00 00 00 00 00 06	.........N......................
0e60	00 32 00 33 00 01 00 12 00 00 00 16 00 02 00 00 00 06 00 10 00 13 00 00 00 00 00 06 00 32 00 4c	.2.3.........................2.L
0e80	00 01 00 00 00 58 00 24 00 02 00 16 00 00 00 02 00 49 00 0b 00 00 00 c9 00 02 00 05 00 00 00 31	.....X.$.........I.............1
0ea0	2a b6 00 3d 4d 03 3e 2a b6 00 3e 36 04 a7 00 1a 2b 2c b9 00 2a 01 00 b9 00 54 02 00 9a 00 0b 2c	..=M.>..>6....+,..*....T.....,
0ec0	b9 00 3f 01 00 04 3e 84 04 ff 15 04 9c ff e4 1d ac 00 00 00 03 00 0e 00 00 00 26 00 09 00 00 01	..?...>...................&.....
0ee0	65 00 05 01 66 00 07 01 67 00 0d 01 68 00 10 01 69 00 1f 01 6b 00 25 01 6c 00 27 01 68 00 2f 01	e...f...g...h...i...k.%.l.'.h./.
0f00	6e 00 0f 00 00 00 34 00 05 00 00 00 31 00 10 00 11 00 00 00 00 00 31 00 32 00 33 00 01 00 05 00	n.....4.....1.........1.2.3.....
0f20	2c 00 34 00 35 00 02 00 07 00 2a 00 36 00 37 00 03 00 0d 00 24 00 38 00 39 00 04 00 12 00 00 00	,.4.5.....*.6.7.....$.8.9.......
0f40	20 00 03 00 00 00 31 00 10 00 13 00 00 00 00 00 31 00 32 00 4c 00 01 00 05 00 2c 00 34 00 42 00	......1.........1.2.L.....,.4.B.
0f60	02 00 01 00 59 00 5a 00 01 00 0b 00 00 00 b0 00 03 00 05 00 00 00 2a 2a b6 00 3d 4c 2a b6 00 3e	....Y.Z...............*..=L..>
0f80	3d 1c bd 00 03 4e 03 36 04 a7 00 10 2d 15 04 2b b9 00 2a 01 00 53 84 04 01 15 04 1c a1 ff f0 2d	=....N.6....-..+..*..S.........-
0fa0	b0 00 00 00 03 00 0e 00 00 00 1e 00 07 00 00 01 7c 00 05 01 7d 00 0a 01 7e 00 0f 01 7f 00 15 01	................\|...}...~.......
0fc0	80 00 1f 01 7f 00 28 01 81 00 0f 00 00 00 34 00 05 00 00 00 2a 00 10 00 11 00 00 00 05 00 25 00	......(.......4.....*.........%.
0fe0	34 00 35 00 01 00 0a 00 20 00 18 00 39 00 02 00 0f 00 1b 00 5b 00 5c 00 03 00 12 00 16 00 38 00	4.5.........9.......[.\.......8.
1000	39 00 04 00 12 00 00 00 16 00 02 00 00 00 2a 00 10 00 13 00 00 00 05 00 25 00 34 00 42 00 01 00	9.............*.........%.4.B...
1020	01 00 59 00 5d 00 02 00 16 00 00 00 02 00 5e 00 0b 00 00 00 e1 00 03 00 05 00 00 00 47 2a b6 00	..Y.].........^.............G*..
1040	3e 3d 2b be 1c a2 00 15 2b b6 00 5f b6 00 63 1c b8 00 68 c0 00 6e 4c a7 00 0d 2b be 1c a4 00 07	>=+.....+.._..c...h..nL...+.....
1060	2b 1c 01 53 2a b6 00 3d 4e 03 36 04 a7 00 10 2b 15 04 2d b9 00 2a 01 00 53 84 04 01 15 04 1c a1	+..S..=N.6....+..-....S.......
1080	ff f0 2b b0 00 00 00 03 00 0e 00 00 00 32 00 0c 00 00 01 9c 00 05 01 9d 00 0b 01 9e 00 12 01 9f	..+..........2..................
10a0	00 13 01 9e 00 1d 01 a0 00 23 01 a1 00 27 01 a3 00 2c 01 a4 00 32 01 a5 00 3c 01 a4 00 45 01 a6	.........#...'...,...2...<...E..
10c0	00 0f 00 00 00 34 00 05 00 00 00 47 00 10 00 11 00 00 00 00 00 47 00 5b 00 5c 00 01 00 05 00 42	.....4.....G.........G.[.\.....B
10e0	00 18 00 39 00 02 00 2c 00 1b 00 34 00 35 00 03 00 2f 00 16 00 38 00 39 00 04 00 12 00 00 00 16	...9...,...4.5.../...8.9........
1100	00 02 00 00 00 47 00 10 00 13 00 00 00 2c 00 1b 00 34 00 42 00 03 00 01 00 6f 00 70 00 01 00 0b	.....G.......,...4.B.....o.p....
1120	00 00 00 f2 00 03 00 05 00 00 00 5a 2a b6 00 3d 4c bb 00 71 59 12 73 b7 00 75 4d 2b b9 00 78 01	...........Z*..=L..qY.s..uM+..x.
1140	00 3e a7 00 34 2b b9 00 2a 01 00 3a 04 19 04 2a a6 00 0d 2c 12 7b b6 00 7d 57 a7 00 0a 2c 19 04	.>..4+....:......,.{..}W...,..
1160	b6 00 81 57 2b b9 00 78 01 00 3e 1d 99 00 0a 2c 12 84 b6 00 7d 57 1d 9a ff ce 2c 12 86 b6 00 7d	...W+..x..>....,....}W....,....}
1180	57 2c b6 00 88 b0 00 00 00 03 00 0e 00 00 00 3a 00 0e 00 00 01 b6 00 05 01 b7 00 0f 01 b8 00 16	W,.............:................
11a0	01 b9 00 19 01 bb 00 21 01 bc 00 27 01 bd 00 31 01 bf 00 38 01 c0 00 3f 01 c1 00 43 01 c2 00 4a	.......!...'...1...8...?...C...J
11c0	01 b9 00 4e 01 c4 00 55 01 c5 00 0f 00 00 00 34 00 05 00 00 00 5a 00 10 00 11 00 00 00 05 00 55	...N...U.......4.....Z.........U
11e0	00 34 00 35 00 01 00 0f 00 4b 00 8a 00 8b 00 02 00 16 00 44 00 7a 00 37 00 03 00 21 00 29 00 20	.4.5.....K.........D.z.7...!.)..
1200	00 21 00 04 00 12 00 00 00 0c 00 01 00 00 00 5a 00 10 00 13 00 00 00 18 00 46 00 47 00 01 00 0b	.!.............Z.........F.G....
1220	00 00 00 4a 00 02 00 02 00 00 00 16 2a c7 00 0f 2b c7 00 07 04 a7 00 0c 03 a7 00 08 2a 2b b6 00	...J...........+...........+..
1240	8c ac 00 00 00 02 00 0e 00 00 00 06 00 01 00 00 01 d3 00 0f 00 00 00 16 00 02 00 00 00 16 00 8e	................................
1260	00 21 00 00 00 00 00 16 00 8f 00 21 00 01 00 18 00 90 00 91 00 01 00 0b 00 00 00 37 00 01 00 01	.!.........!...............7....
1280	00 00 00 0d 2a c7 00 07 03 a7 00 07 2a b6 00 92 ac 00 00 00 02 00 0e 00 00 00 06 00 01 00 00 01	..............................
12a0	e0 00 0f 00 00 00 0c 00 01 00 00 00 0d 00 20 00 21 00 00 00 02 00 94 00 00 00 02 00 95 00 16 00	................!...............
12c0	00 00 02 00 96	.....