aboutsummaryrefslogtreecommitdiff
path: root/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
blob: 2fae8dc23bcff401190da5e6f69066c0874834de (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
/* { dg-do compile } */
/* { dg-require-effective-target ppc_float128_hw } */
/* { dg-require-effective-target power10_ok } */
/* { dg-options "-mdejagnu-cpu=power10 -O2" } */

#ifndef TYPE
#ifdef __LONG_DOUBLE_IEEE128__
#define TYPE long double

#else
#define TYPE _Float128
#endif
#endif

/* Verify that the ISA 3.1 (power10) IEEE 128-bit conditional move instructions
   are generated.  */

TYPE
eq (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a == b) ? c : d;
}

TYPE
ne (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a != b) ? c : d;
}

TYPE
lt (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a < b) ? c : d;
}

TYPE
le (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a <= b) ? c : d;
}

TYPE
gt (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a > b) ? c : d;
}

TYPE
ge (TYPE a, TYPE b, TYPE c, TYPE d)
{
  return (a >= b) ? c : d;
}

/* { dg-final { scan-assembler-times {\mxscmpeqqp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxscmpgeqp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxscmpgtqp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsel\M}     6 } } */
/* { dg-final { scan-assembler-not   {\mxscmpuqp\M}    } } */