1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
|
/* RTL-based forward propagation pass for GNU compiler.
Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Contributed by Paolo Bonzini and Steven Bosscher.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "toplev.h"
#include "timevar.h"
#include "rtl.h"
#include "tm_p.h"
#include "insn-config.h"
#include "recog.h"
#include "flags.h"
#include "obstack.h"
#include "basic-block.h"
#include "output.h"
#include "df.h"
#include "target.h"
#include "cfgloop.h"
#include "tree-pass.h"
#include "domwalk.h"
#include "emit-rtl.h"
/* This pass does simple forward propagation and simplification when an
operand of an insn can only come from a single def. This pass uses
df.c, so it is global. However, we only do limited analysis of
available expressions.
1) The pass tries to propagate the source of the def into the use,
and checks if the result is independent of the substituted value.
For example, the high word of a (zero_extend:DI (reg:SI M)) is always
zero, independent of the source register.
In particular, we propagate constants into the use site. Sometimes
RTL expansion did not put the constant in the same insn on purpose,
to satisfy a predicate, and the result will fail to be recognized;
but this happens rarely and in this case we can still create a
REG_EQUAL note. For multi-word operations, this
(set (subreg:SI (reg:DI 120) 0) (const_int 0))
(set (subreg:SI (reg:DI 120) 4) (const_int -1))
(set (subreg:SI (reg:DI 122) 0)
(ior:SI (subreg:SI (reg:DI 119) 0) (subreg:SI (reg:DI 120) 0)))
(set (subreg:SI (reg:DI 122) 4)
(ior:SI (subreg:SI (reg:DI 119) 4) (subreg:SI (reg:DI 120) 4)))
can be simplified to the much simpler
(set (subreg:SI (reg:DI 122) 0) (subreg:SI (reg:DI 119)))
(set (subreg:SI (reg:DI 122) 4) (const_int -1))
This particular propagation is also effective at putting together
complex addressing modes. We are more aggressive inside MEMs, in
that all definitions are propagated if the use is in a MEM; if the
result is a valid memory address we check address_cost to decide
whether the substitution is worthwhile.
2) The pass propagates register copies. This is not as effective as
the copy propagation done by CSE's canon_reg, which works by walking
the instruction chain, it can help the other transformations.
We should consider removing this optimization, and instead reorder the
RTL passes, because GCSE does this transformation too. With some luck,
the CSE pass at the end of rest_of_handle_gcse could also go away.
3) The pass looks for paradoxical subregs that are actually unnecessary.
Things like this:
(set (reg:QI 120) (subreg:QI (reg:SI 118) 0))
(set (reg:QI 121) (subreg:QI (reg:SI 119) 0))
(set (reg:SI 122) (plus:SI (subreg:SI (reg:QI 120) 0)
(subreg:SI (reg:QI 121) 0)))
are very common on machines that can only do word-sized operations.
For each use of a paradoxical subreg (subreg:WIDER (reg:NARROW N) 0),
if it has a single def and it is (subreg:NARROW (reg:WIDE M) 0),
we can replace the paradoxical subreg with simply (reg:WIDE M). The
above will simplify this to
(set (reg:QI 120) (subreg:QI (reg:SI 118) 0))
(set (reg:QI 121) (subreg:QI (reg:SI 119) 0))
(set (reg:SI 122) (plus:SI (reg:SI 118) (reg:SI 119)))
where the first two insns are now dead.
We used to use reaching definitions to find which uses have a
single reaching definition (sounds obvious...), but this is too
complex a problem in nasty testcases like PR33928. Now we use the
multiple definitions problem in df-problems.c. The similarity
between that problem and SSA form creation is taken further, in
that fwprop does a dominator walk to create its chains; however,
instead of creating a PHI function where multiple definitions meet
I just punt and record only singleton use-def chains, which is
all that is needed by fwprop. */
static int num_changes;
DEF_VEC_P(df_ref);
DEF_VEC_ALLOC_P(df_ref,heap);
static VEC(df_ref,heap) *use_def_ref;
static VEC(df_ref,heap) *reg_defs;
static VEC(df_ref,heap) *reg_defs_stack;
/* The MD bitmaps are trimmed to include only live registers to cut
memory usage on testcases like insn-recog.c. Track live registers
in the basic block and do not perform forward propagation if the
destination is a dead pseudo occurring in a note. */
static bitmap local_md;
static bitmap local_lr;
/* Return the only def in USE's use-def chain, or NULL if there is
more than one def in the chain. */
static inline df_ref
get_def_for_use (df_ref use)
{
return VEC_index (df_ref, use_def_ref, DF_REF_ID (use));
}
/* Update the reg_defs vector with non-partial definitions in DEF_REC.
TOP_FLAG says which artificials uses should be used, when DEF_REC
is an artificial def vector. LOCAL_MD is modified as after a
df_md_simulate_* function; we do more or less the same processing
done there, so we do not use those functions. */
#define DF_MD_GEN_FLAGS \
(DF_REF_PARTIAL | DF_REF_CONDITIONAL | DF_REF_MAY_CLOBBER)
static void
process_defs (df_ref *def_rec, int top_flag)
{
df_ref def;
while ((def = *def_rec++) != NULL)
{
df_ref curr_def = VEC_index (df_ref, reg_defs, DF_REF_REGNO (def));
unsigned int dregno;
if ((DF_REF_FLAGS (def) & DF_REF_AT_TOP) != top_flag)
continue;
dregno = DF_REF_REGNO (def);
if (curr_def)
VEC_safe_push (df_ref, heap, reg_defs_stack, curr_def);
else
{
/* Do not store anything if "transitioning" from NULL to NULL. But
otherwise, push a special entry on the stack to tell the
leave_block callback that the entry in reg_defs was NULL. */
if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS)
;
else
VEC_safe_push (df_ref, heap, reg_defs_stack, def);
}
if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS)
{
bitmap_set_bit (local_md, dregno);
VEC_replace (df_ref, reg_defs, dregno, NULL);
}
else
{
bitmap_clear_bit (local_md, dregno);
VEC_replace (df_ref, reg_defs, dregno, def);
}
}
}
/* Fill the use_def_ref vector with values for the uses in USE_REC,
taking reaching definitions info from LOCAL_MD and REG_DEFS.
TOP_FLAG says which artificials uses should be used, when USE_REC
is an artificial use vector. */
static void
process_uses (df_ref *use_rec, int top_flag)
{
df_ref use;
while ((use = *use_rec++) != NULL)
if ((DF_REF_FLAGS (use) & DF_REF_AT_TOP) == top_flag)
{
unsigned int uregno = DF_REF_REGNO (use);
if (VEC_index (df_ref, reg_defs, uregno)
&& !bitmap_bit_p (local_md, uregno)
&& bitmap_bit_p (local_lr, uregno))
VEC_replace (df_ref, use_def_ref, DF_REF_ID (use),
VEC_index (df_ref, reg_defs, uregno));
}
}
static void
single_def_use_enter_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED,
basic_block bb)
{
int bb_index = bb->index;
struct df_md_bb_info *md_bb_info = df_md_get_bb_info (bb_index);
struct df_lr_bb_info *lr_bb_info = df_lr_get_bb_info (bb_index);
rtx insn;
bitmap_copy (local_md, md_bb_info->in);
bitmap_copy (local_lr, lr_bb_info->in);
/* Push a marker for the leave_block callback. */
VEC_safe_push (df_ref, heap, reg_defs_stack, NULL);
process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP);
process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP);
/* We don't call df_simulate_initialize_forwards, as it may overestimate
the live registers if there are unused artificial defs. We prefer
liveness to be underestimated. */
FOR_BB_INSNS (bb, insn)
if (INSN_P (insn))
{
unsigned int uid = INSN_UID (insn);
process_uses (DF_INSN_UID_USES (uid), 0);
process_uses (DF_INSN_UID_EQ_USES (uid), 0);
process_defs (DF_INSN_UID_DEFS (uid), 0);
df_simulate_one_insn_forwards (bb, insn, local_lr);
}
process_uses (df_get_artificial_uses (bb_index), 0);
process_defs (df_get_artificial_defs (bb_index), 0);
}
/* Pop the definitions created in this basic block when leaving its
dominated parts. */
static void
single_def_use_leave_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED,
basic_block bb ATTRIBUTE_UNUSED)
{
df_ref saved_def;
while ((saved_def = VEC_pop (df_ref, reg_defs_stack)) != NULL)
{
unsigned int dregno = DF_REF_REGNO (saved_def);
/* See also process_defs. */
if (saved_def == VEC_index (df_ref, reg_defs, dregno))
VEC_replace (df_ref, reg_defs, dregno, NULL);
else
VEC_replace (df_ref, reg_defs, dregno, saved_def);
}
}
/* Build a vector holding the reaching definitions of uses reached by a
single dominating definition. */
static void
build_single_def_use_links (void)
{
struct dom_walk_data walk_data;
/* We use the multiple definitions problem to compute our restricted
use-def chains. */
df_set_flags (DF_EQ_NOTES);
df_md_add_problem ();
df_note_add_problem ();
df_analyze ();
df_maybe_reorganize_use_refs (DF_REF_ORDER_BY_INSN_WITH_NOTES);
use_def_ref = VEC_alloc (df_ref, heap, DF_USES_TABLE_SIZE ());
VEC_safe_grow_cleared (df_ref, heap, use_def_ref, DF_USES_TABLE_SIZE ());
reg_defs = VEC_alloc (df_ref, heap, max_reg_num ());
VEC_safe_grow_cleared (df_ref, heap, reg_defs, max_reg_num ());
reg_defs_stack = VEC_alloc (df_ref, heap, n_basic_blocks * 10);
local_md = BITMAP_ALLOC (NULL);
local_lr = BITMAP_ALLOC (NULL);
/* Walk the dominator tree looking for single reaching definitions
dominating the uses. This is similar to how SSA form is built. */
walk_data.dom_direction = CDI_DOMINATORS;
walk_data.initialize_block_local_data = NULL;
walk_data.before_dom_children = single_def_use_enter_block;
walk_data.after_dom_children = single_def_use_leave_block;
init_walk_dominator_tree (&walk_data);
walk_dominator_tree (&walk_data, ENTRY_BLOCK_PTR);
fini_walk_dominator_tree (&walk_data);
BITMAP_FREE (local_lr);
BITMAP_FREE (local_md);
VEC_free (df_ref, heap, reg_defs);
VEC_free (df_ref, heap, reg_defs_stack);
}
/* Do not try to replace constant addresses or addresses of local and
argument slots. These MEM expressions are made only once and inserted
in many instructions, as well as being used to control symbol table
output. It is not safe to clobber them.
There are some uncommon cases where the address is already in a register
for some reason, but we cannot take advantage of that because we have
no easy way to unshare the MEM. In addition, looking up all stack
addresses is costly. */
static bool
can_simplify_addr (rtx addr)
{
rtx reg;
if (CONSTANT_ADDRESS_P (addr))
return false;
if (GET_CODE (addr) == PLUS)
reg = XEXP (addr, 0);
else
reg = addr;
return (!REG_P (reg)
|| (REGNO (reg) != FRAME_POINTER_REGNUM
&& REGNO (reg) != HARD_FRAME_POINTER_REGNUM
&& REGNO (reg) != ARG_POINTER_REGNUM));
}
/* Returns a canonical version of X for the address, from the point of view,
that all multiplications are represented as MULT instead of the multiply
by a power of 2 being represented as ASHIFT.
Every ASHIFT we find has been made by simplify_gen_binary and was not
there before, so it is not shared. So we can do this in place. */
static void
canonicalize_address (rtx x)
{
for (;;)
switch (GET_CODE (x))
{
case ASHIFT:
if (CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x))
&& INTVAL (XEXP (x, 1)) >= 0)
{
HOST_WIDE_INT shift = INTVAL (XEXP (x, 1));
PUT_CODE (x, MULT);
XEXP (x, 1) = gen_int_mode ((HOST_WIDE_INT) 1 << shift,
GET_MODE (x));
}
x = XEXP (x, 0);
break;
case PLUS:
if (GET_CODE (XEXP (x, 0)) == PLUS
|| GET_CODE (XEXP (x, 0)) == ASHIFT
|| GET_CODE (XEXP (x, 0)) == CONST)
canonicalize_address (XEXP (x, 0));
x = XEXP (x, 1);
break;
case CONST:
x = XEXP (x, 0);
break;
default:
return;
}
}
/* OLD is a memory address. Return whether it is good to use NEW instead,
for a memory access in the given MODE. */
static bool
should_replace_address (rtx old_rtx, rtx new_rtx, enum machine_mode mode,
addr_space_t as, bool speed)
{
int gain;
if (rtx_equal_p (old_rtx, new_rtx)
|| !memory_address_addr_space_p (mode, new_rtx, as))
return false;
/* Copy propagation is always ok. */
if (REG_P (old_rtx) && REG_P (new_rtx))
return true;
/* Prefer the new address if it is less expensive. */
gain = (address_cost (old_rtx, mode, as, speed)
- address_cost (new_rtx, mode, as, speed));
/* If the addresses have equivalent cost, prefer the new address
if it has the highest `rtx_cost'. That has the potential of
eliminating the most insns without additional costs, and it
is the same that cse.c used to do. */
if (gain == 0)
gain = rtx_cost (new_rtx, SET, speed) - rtx_cost (old_rtx, SET, speed);
return (gain > 0);
}
/* Flags for the last parameter of propagate_rtx_1. */
enum {
/* If PR_CAN_APPEAR is true, propagate_rtx_1 always returns true;
if it is false, propagate_rtx_1 returns false if, for at least
one occurrence OLD, it failed to collapse the result to a constant.
For example, (mult:M (reg:M A) (minus:M (reg:M B) (reg:M A))) may
collapse to zero if replacing (reg:M B) with (reg:M A).
PR_CAN_APPEAR is disregarded inside MEMs: in that case,
propagate_rtx_1 just tries to make cheaper and valid memory
addresses. */
PR_CAN_APPEAR = 1,
/* If PR_HANDLE_MEM is not set, propagate_rtx_1 won't attempt any replacement
outside memory addresses. This is needed because propagate_rtx_1 does
not do any analysis on memory; thus it is very conservative and in general
it will fail if non-read-only MEMs are found in the source expression.
PR_HANDLE_MEM is set when the source of the propagation was not
another MEM. Then, it is safe not to treat non-read-only MEMs as
``opaque'' objects. */
PR_HANDLE_MEM = 2,
/* Set when costs should be optimized for speed. */
PR_OPTIMIZE_FOR_SPEED = 4
};
/* Replace all occurrences of OLD in *PX with NEW and try to simplify the
resulting expression. Replace *PX with a new RTL expression if an
occurrence of OLD was found.
This is only a wrapper around simplify-rtx.c: do not add any pattern
matching code here. (The sole exception is the handling of LO_SUM, but
that is because there is no simplify_gen_* function for LO_SUM). */
static bool
propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags)
{
rtx x = *px, tem = NULL_RTX, op0, op1, op2;
enum rtx_code code = GET_CODE (x);
enum machine_mode mode = GET_MODE (x);
enum machine_mode op_mode;
bool can_appear = (flags & PR_CAN_APPEAR) != 0;
bool valid_ops = true;
if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x))
{
/* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether
they have side effects or not). */
*px = (side_effects_p (x)
? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)
: gen_rtx_SCRATCH (GET_MODE (x)));
return false;
}
/* If X is OLD_RTX, return NEW_RTX. But not if replacing only within an
address, and we are *not* inside one. */
if (x == old_rtx)
{
*px = new_rtx;
return can_appear;
}
/* If this is an expression, try recursive substitution. */
switch (GET_RTX_CLASS (code))
{
case RTX_UNARY:
op0 = XEXP (x, 0);
op_mode = GET_MODE (op0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0))
return true;
tem = simplify_gen_unary (code, mode, op0, op_mode);
break;
case RTX_BIN_ARITH:
case RTX_COMM_ARITH:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
tem = simplify_gen_binary (code, mode, op0, op1);
break;
case RTX_COMPARE:
case RTX_COMM_COMPARE:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
tem = simplify_gen_relational (code, mode, op_mode, op0, op1);
break;
case RTX_TERNARY:
case RTX_BITFIELD_OPS:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
op2 = XEXP (x, 2);
op_mode = GET_MODE (op0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2))
return true;
if (op_mode == VOIDmode)
op_mode = GET_MODE (op0);
tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2);
break;
case RTX_EXTRA:
/* The only case we try to handle is a SUBREG. */
if (code == SUBREG)
{
op0 = XEXP (x, 0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0))
return true;
tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)),
SUBREG_BYTE (x));
}
break;
case RTX_OBJ:
if (code == MEM && x != new_rtx)
{
rtx new_op0;
op0 = XEXP (x, 0);
/* There are some addresses that we cannot work on. */
if (!can_simplify_addr (op0))
return true;
op0 = new_op0 = targetm.delegitimize_address (op0);
valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx,
flags | PR_CAN_APPEAR);
/* Dismiss transformation that we do not want to carry on. */
if (!valid_ops
|| new_op0 == op0
|| !(GET_MODE (new_op0) == GET_MODE (op0)
|| GET_MODE (new_op0) == VOIDmode))
return true;
canonicalize_address (new_op0);
/* Copy propagations are always ok. Otherwise check the costs. */
if (!(REG_P (old_rtx) && REG_P (new_rtx))
&& !should_replace_address (op0, new_op0, GET_MODE (x),
MEM_ADDR_SPACE (x),
flags & PR_OPTIMIZE_FOR_SPEED))
return true;
tem = replace_equiv_address_nv (x, new_op0);
}
else if (code == LO_SUM)
{
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
/* The only simplification we do attempts to remove references to op0
or make it constant -- in both cases, op0's invalidity will not
make the result invalid. */
propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
/* (lo_sum (high x) x) -> x */
if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))
tem = op1;
else
tem = gen_rtx_LO_SUM (mode, op0, op1);
/* OP1 is likely not a legitimate address, otherwise there would have
been no LO_SUM. We want it to disappear if it is invalid, return
false in that case. */
return memory_address_p (mode, tem);
}
else if (code == REG)
{
if (rtx_equal_p (x, old_rtx))
{
*px = new_rtx;
return can_appear;
}
}
break;
default:
break;
}
/* No change, no trouble. */
if (tem == NULL_RTX)
return true;
*px = tem;
/* The replacement we made so far is valid, if all of the recursive
replacements were valid, or we could simplify everything to
a constant. */
return valid_ops || can_appear || CONSTANT_P (tem);
}
/* for_each_rtx traversal function that returns 1 if BODY points to
a non-constant mem. */
static int
varying_mem_p (rtx *body, void *data ATTRIBUTE_UNUSED)
{
rtx x = *body;
return MEM_P (x) && !MEM_READONLY_P (x);
}
/* Replace all occurrences of OLD in X with NEW and try to simplify the
resulting expression (in mode MODE). Return a new expression if it is
a constant, otherwise X.
Simplifications where occurrences of NEW collapse to a constant are always
accepted. All simplifications are accepted if NEW is a pseudo too.
Otherwise, we accept simplifications that have a lower or equal cost. */
static rtx
propagate_rtx (rtx x, enum machine_mode mode, rtx old_rtx, rtx new_rtx,
bool speed)
{
rtx tem;
bool collapsed;
int flags;
if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER)
return NULL_RTX;
flags = 0;
if (REG_P (new_rtx) || CONSTANT_P (new_rtx))
flags |= PR_CAN_APPEAR;
if (!for_each_rtx (&new_rtx, varying_mem_p, NULL))
flags |= PR_HANDLE_MEM;
if (speed)
flags |= PR_OPTIMIZE_FOR_SPEED;
tem = x;
collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags);
if (tem == x || !collapsed)
return NULL_RTX;
/* gen_lowpart_common will not be able to process VOIDmode entities other
than CONST_INTs. */
if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem))
return NULL_RTX;
if (GET_MODE (tem) == VOIDmode)
tem = rtl_hooks.gen_lowpart_no_emit (mode, tem);
else
gcc_assert (GET_MODE (tem) == mode);
return tem;
}
/* Return true if the register from reference REF is killed
between FROM to (but not including) TO. */
static bool
local_ref_killed_between_p (df_ref ref, rtx from, rtx to)
{
rtx insn;
for (insn = from; insn != to; insn = NEXT_INSN (insn))
{
df_ref *def_rec;
if (!INSN_P (insn))
continue;
for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
{
df_ref def = *def_rec;
if (DF_REF_REGNO (ref) == DF_REF_REGNO (def))
return true;
}
}
return false;
}
/* Check if the given DEF is available in INSN. This would require full
computation of available expressions; we check only restricted conditions:
- if DEF is the sole definition of its register, go ahead;
- in the same basic block, we check for no definitions killing the
definition of DEF_INSN;
- if USE's basic block has DEF's basic block as the sole predecessor,
we check if the definition is killed after DEF_INSN or before
TARGET_INSN insn, in their respective basic blocks. */
static bool
use_killed_between (df_ref use, rtx def_insn, rtx target_insn)
{
basic_block def_bb = BLOCK_FOR_INSN (def_insn);
basic_block target_bb = BLOCK_FOR_INSN (target_insn);
int regno;
df_ref def;
/* We used to have a def reaching a use that is _before_ the def,
with the def not dominating the use even though the use and def
are in the same basic block, when a register may be used
uninitialized in a loop. This should not happen anymore since
we do not use reaching definitions, but still we test for such
cases and assume that DEF is not available. */
if (def_bb == target_bb
? DF_INSN_LUID (def_insn) >= DF_INSN_LUID (target_insn)
: !dominated_by_p (CDI_DOMINATORS, target_bb, def_bb))
return true;
/* Check if the reg in USE has only one definition. We already
know that this definition reaches use, or we wouldn't be here.
However, this is invalid for hard registers because if they are
live at the beginning of the function it does not mean that we
have an uninitialized access. */
regno = DF_REF_REGNO (use);
def = DF_REG_DEF_CHAIN (regno);
if (def
&& DF_REF_NEXT_REG (def) == NULL
&& regno >= FIRST_PSEUDO_REGISTER)
return false;
/* Check locally if we are in the same basic block. */
if (def_bb == target_bb)
return local_ref_killed_between_p (use, def_insn, target_insn);
/* Finally, if DEF_BB is the sole predecessor of TARGET_BB. */
if (single_pred_p (target_bb)
&& single_pred (target_bb) == def_bb)
{
df_ref x;
/* See if USE is killed between DEF_INSN and the last insn in the
basic block containing DEF_INSN. */
x = df_bb_regno_last_def_find (def_bb, regno);
if (x && DF_INSN_LUID (DF_REF_INSN (x)) >= DF_INSN_LUID (def_insn))
return true;
/* See if USE is killed between TARGET_INSN and the first insn in the
basic block containing TARGET_INSN. */
x = df_bb_regno_first_def_find (target_bb, regno);
if (x && DF_INSN_LUID (DF_REF_INSN (x)) < DF_INSN_LUID (target_insn))
return true;
return false;
}
/* Otherwise assume the worst case. */
return true;
}
/* Check if all uses in DEF_INSN can be used in TARGET_INSN. This
would require full computation of available expressions;
we check only restricted conditions, see use_killed_between. */
static bool
all_uses_available_at (rtx def_insn, rtx target_insn)
{
df_ref *use_rec;
struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn);
rtx def_set = single_set (def_insn);
gcc_assert (def_set);
/* If target_insn comes right after def_insn, which is very common
for addresses, we can use a quicker test. */
if (NEXT_INSN (def_insn) == target_insn
&& REG_P (SET_DEST (def_set)))
{
rtx def_reg = SET_DEST (def_set);
/* If the insn uses the reg that it defines, the substitution is
invalid. */
for (use_rec = DF_INSN_INFO_USES (insn_info); *use_rec; use_rec++)
{
df_ref use = *use_rec;
if (rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
}
for (use_rec = DF_INSN_INFO_EQ_USES (insn_info); *use_rec; use_rec++)
{
df_ref use = *use_rec;
if (rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
}
}
else
{
rtx def_reg = REG_P (SET_DEST (def_set)) ? SET_DEST (def_set) : NULL_RTX;
/* Look at all the uses of DEF_INSN, and see if they are not
killed between DEF_INSN and TARGET_INSN. */
for (use_rec = DF_INSN_INFO_USES (insn_info); *use_rec; use_rec++)
{
df_ref use = *use_rec;
if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
if (use_killed_between (use, def_insn, target_insn))
return false;
}
for (use_rec = DF_INSN_INFO_EQ_USES (insn_info); *use_rec; use_rec++)
{
df_ref use = *use_rec;
if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
if (use_killed_between (use, def_insn, target_insn))
return false;
}
}
return true;
}
struct find_occurrence_data
{
rtx find;
rtx *retval;
};
/* Callback for for_each_rtx, used in find_occurrence.
See if PX is the rtx we have to find. Return 1 to stop for_each_rtx
if successful, or 0 to continue traversing otherwise. */
static int
find_occurrence_callback (rtx *px, void *data)
{
struct find_occurrence_data *fod = (struct find_occurrence_data *) data;
rtx x = *px;
rtx find = fod->find;
if (x == find)
{
fod->retval = px;
return 1;
}
return 0;
}
/* Return a pointer to one of the occurrences of register FIND in *PX. */
static rtx *
find_occurrence (rtx *px, rtx find)
{
struct find_occurrence_data data;
gcc_assert (REG_P (find)
|| (GET_CODE (find) == SUBREG
&& REG_P (SUBREG_REG (find))));
data.find = find;
data.retval = NULL;
for_each_rtx (px, find_occurrence_callback, &data);
return data.retval;
}
/* Inside INSN, the expression rooted at *LOC has been changed, moving some
uses from USE_VEC. Find those that are present, and create new items
in the data flow object of the pass. Mark any new uses as having the
given TYPE. */
static void
update_df (rtx insn, rtx *loc, df_ref *use_rec, enum df_ref_type type,
int new_flags)
{
bool changed = false;
/* Add a use for the registers that were propagated. */
while (*use_rec)
{
df_ref use = *use_rec;
df_ref orig_use = use, new_use;
int width = -1;
int offset = -1;
enum machine_mode mode = VOIDmode;
rtx *new_loc = find_occurrence (loc, DF_REF_REG (orig_use));
use_rec++;
if (!new_loc)
continue;
if (DF_REF_FLAGS_IS_SET (orig_use, DF_REF_SIGN_EXTRACT | DF_REF_ZERO_EXTRACT))
{
width = DF_REF_EXTRACT_WIDTH (orig_use);
offset = DF_REF_EXTRACT_OFFSET (orig_use);
mode = DF_REF_EXTRACT_MODE (orig_use);
}
/* Add a new insn use. Use the original type, because it says if the
use was within a MEM. */
new_use = df_ref_create (DF_REF_REG (orig_use), new_loc,
insn, BLOCK_FOR_INSN (insn),
type, DF_REF_FLAGS (orig_use) | new_flags,
width, offset, mode);
/* Set up the use-def chain. */
gcc_assert (DF_REF_ID (new_use) == (int) VEC_length (df_ref, use_def_ref));
VEC_safe_push (df_ref, heap, use_def_ref, get_def_for_use (orig_use));
changed = true;
}
if (changed)
df_insn_rescan (insn);
}
/* Try substituting NEW into LOC, which originated from forward propagation
of USE's value from DEF_INSN. SET_REG_EQUAL says whether we are
substituting the whole SET_SRC, so we can set a REG_EQUAL note if the
new insn is not recognized. Return whether the substitution was
performed. */
static bool
try_fwprop_subst (df_ref use, rtx *loc, rtx new_rtx, rtx def_insn, bool set_reg_equal)
{
rtx insn = DF_REF_INSN (use);
enum df_ref_type type = DF_REF_TYPE (use);
int flags = DF_REF_FLAGS (use);
rtx set = single_set (insn);
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
int old_cost = 0;
bool ok;
/* forward_propagate_subreg may be operating on an instruction with
multiple sets. If so, assume the cost of the new instruction is
not greater than the old one. */
if (set)
old_cost = rtx_cost (SET_SRC (set), SET, speed);
if (dump_file)
{
fprintf (dump_file, "\nIn insn %d, replacing\n ", INSN_UID (insn));
print_inline_rtx (dump_file, *loc, 2);
fprintf (dump_file, "\n with ");
print_inline_rtx (dump_file, new_rtx, 2);
fprintf (dump_file, "\n");
}
validate_unshare_change (insn, loc, new_rtx, true);
if (!verify_changes (0))
{
if (dump_file)
fprintf (dump_file, "Changes to insn %d not recognized\n",
INSN_UID (insn));
ok = false;
}
else if (DF_REF_TYPE (use) == DF_REF_REG_USE
&& set
&& rtx_cost (SET_SRC (set), SET, speed) > old_cost)
{
if (dump_file)
fprintf (dump_file, "Changes to insn %d not profitable\n",
INSN_UID (insn));
ok = false;
}
else
{
if (dump_file)
fprintf (dump_file, "Changed insn %d\n", INSN_UID (insn));
ok = true;
}
if (ok)
{
confirm_change_group ();
num_changes++;
df_ref_remove (use);
if (!CONSTANT_P (new_rtx))
{
struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn);
update_df (insn, loc, DF_INSN_INFO_USES (insn_info), type, flags);
update_df (insn, loc, DF_INSN_INFO_EQ_USES (insn_info), type, flags);
}
}
else
{
cancel_changes (0);
/* Can also record a simplified value in a REG_EQUAL note,
making a new one if one does not already exist. */
if (set_reg_equal)
{
if (dump_file)
fprintf (dump_file, " Setting REG_EQUAL note\n");
set_unique_reg_note (insn, REG_EQUAL, copy_rtx (new_rtx));
/* ??? Is this still necessary if we add the note through
set_unique_reg_note? */
if (!CONSTANT_P (new_rtx))
{
struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn);
update_df (insn, loc, DF_INSN_INFO_USES (insn_info),
type, DF_REF_IN_NOTE);
update_df (insn, loc, DF_INSN_INFO_EQ_USES (insn_info),
type, DF_REF_IN_NOTE);
}
}
}
return ok;
}
/* For the given single_set INSN, containing SRC known to be a
ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN
is redundant due to the register being set by a LOAD_EXTEND_OP
load from memory. */
static bool
free_load_extend (rtx src, rtx insn)
{
rtx reg;
df_ref *use_vec;
df_ref use = 0, def;
reg = XEXP (src, 0);
#ifdef LOAD_EXTEND_OP
if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src))
#endif
return false;
for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
{
use = *use_vec;
if (!DF_REF_IS_ARTIFICIAL (use)
&& DF_REF_TYPE (use) == DF_REF_REG_USE
&& DF_REF_REG (use) == reg)
break;
}
if (!use)
return false;
def = get_def_for_use (use);
if (!def)
return false;
if (DF_REF_IS_ARTIFICIAL (def))
return false;
if (NONJUMP_INSN_P (DF_REF_INSN (def)))
{
rtx patt = PATTERN (DF_REF_INSN (def));
if (GET_CODE (patt) == SET
&& GET_CODE (SET_SRC (patt)) == MEM
&& rtx_equal_p (SET_DEST (patt), reg))
return true;
}
return false;
}
/* If USE is a subreg, see if it can be replaced by a pseudo. */
static bool
forward_propagate_subreg (df_ref use, rtx def_insn, rtx def_set)
{
rtx use_reg = DF_REF_REG (use);
rtx use_insn, src;
/* Only consider subregs... */
enum machine_mode use_mode = GET_MODE (use_reg);
if (GET_CODE (use_reg) != SUBREG
|| !REG_P (SET_DEST (def_set)))
return false;
/* If this is a paradoxical SUBREG... */
if (GET_MODE_SIZE (use_mode)
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (use_reg))))
{
/* If this is a paradoxical SUBREG, we have no idea what value the
extra bits would have. However, if the operand is equivalent to
a SUBREG whose operand is the same as our mode, and all the modes
are within a word, we can just use the inner operand because
these SUBREGs just say how to treat the register. */
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
if (GET_CODE (src) == SUBREG
&& REG_P (SUBREG_REG (src))
&& GET_MODE (SUBREG_REG (src)) == use_mode
&& subreg_lowpart_p (src)
&& all_uses_available_at (def_insn, use_insn))
return try_fwprop_subst (use, DF_REF_LOC (use), SUBREG_REG (src),
def_insn, false);
}
/* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG
is the low part of the reg being extended then just use the inner
operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will
be removed due to it matching a LOAD_EXTEND_OP load from memory. */
else if (subreg_lowpart_p (use_reg))
{
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
if ((GET_CODE (src) == ZERO_EXTEND
|| GET_CODE (src) == SIGN_EXTEND)
&& REG_P (XEXP (src, 0))
&& GET_MODE (XEXP (src, 0)) == use_mode
&& !free_load_extend (src, def_insn)
&& all_uses_available_at (def_insn, use_insn))
return try_fwprop_subst (use, DF_REF_LOC (use), XEXP (src, 0),
def_insn, false);
}
return false;
}
/* Try to replace USE with SRC (defined in DEF_INSN) in __asm. */
static bool
forward_propagate_asm (df_ref use, rtx def_insn, rtx def_set, rtx reg)
{
rtx use_insn = DF_REF_INSN (use), src, use_pat, asm_operands, new_rtx, *loc;
int speed_p, i;
df_ref *use_vec;
gcc_assert ((DF_REF_FLAGS (use) & DF_REF_IN_NOTE) == 0);
src = SET_SRC (def_set);
use_pat = PATTERN (use_insn);
/* In __asm don't replace if src might need more registers than
reg, as that could increase register pressure on the __asm. */
use_vec = DF_INSN_USES (def_insn);
if (use_vec[0] && use_vec[1])
return false;
speed_p = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
asm_operands = NULL_RTX;
switch (GET_CODE (use_pat))
{
case ASM_OPERANDS:
asm_operands = use_pat;
break;
case SET:
if (MEM_P (SET_DEST (use_pat)))
{
loc = &SET_DEST (use_pat);
new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p);
if (new_rtx)
validate_unshare_change (use_insn, loc, new_rtx, true);
}
asm_operands = SET_SRC (use_pat);
break;
case PARALLEL:
for (i = 0; i < XVECLEN (use_pat, 0); i++)
if (GET_CODE (XVECEXP (use_pat, 0, i)) == SET)
{
if (MEM_P (SET_DEST (XVECEXP (use_pat, 0, i))))
{
loc = &SET_DEST (XVECEXP (use_pat, 0, i));
new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg,
src, speed_p);
if (new_rtx)
validate_unshare_change (use_insn, loc, new_rtx, true);
}
asm_operands = SET_SRC (XVECEXP (use_pat, 0, i));
}
else if (GET_CODE (XVECEXP (use_pat, 0, i)) == ASM_OPERANDS)
asm_operands = XVECEXP (use_pat, 0, i);
break;
default:
gcc_unreachable ();
}
gcc_assert (asm_operands && GET_CODE (asm_operands) == ASM_OPERANDS);
for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (asm_operands); i++)
{
loc = &ASM_OPERANDS_INPUT (asm_operands, i);
new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p);
if (new_rtx)
validate_unshare_change (use_insn, loc, new_rtx, true);
}
if (num_changes_pending () == 0 || !apply_change_group ())
return false;
num_changes++;
return true;
}
/* Try to replace USE with SRC (defined in DEF_INSN) and simplify the
result. */
static bool
forward_propagate_and_simplify (df_ref use, rtx def_insn, rtx def_set)
{
rtx use_insn = DF_REF_INSN (use);
rtx use_set = single_set (use_insn);
rtx src, reg, new_rtx, *loc;
bool set_reg_equal;
enum machine_mode mode;
int asm_use = -1;
if (INSN_CODE (use_insn) < 0)
asm_use = asm_noperands (PATTERN (use_insn));
if (!use_set && asm_use < 0 && !DEBUG_INSN_P (use_insn))
return false;
/* Do not propagate into PC, CC0, etc. */
if (use_set && GET_MODE (SET_DEST (use_set)) == VOIDmode)
return false;
/* If def and use are subreg, check if they match. */
reg = DF_REF_REG (use);
if (GET_CODE (reg) == SUBREG
&& GET_CODE (SET_DEST (def_set)) == SUBREG
&& (SUBREG_BYTE (SET_DEST (def_set)) != SUBREG_BYTE (reg)
|| GET_MODE (SET_DEST (def_set)) != GET_MODE (reg)))
return false;
/* Check if the def had a subreg, but the use has the whole reg. */
if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG)
return false;
/* Check if the use has a subreg, but the def had the whole reg. Unlike the
previous case, the optimization is possible and often useful indeed. */
if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set)))
reg = SUBREG_REG (reg);
/* Check if the substitution is valid (last, because it's the most
expensive check!). */
src = SET_SRC (def_set);
if (!CONSTANT_P (src) && !all_uses_available_at (def_insn, use_insn))
return false;
/* Check if the def is loading something from the constant pool; in this
case we would undo optimization such as compress_float_constant.
Still, we can set a REG_EQUAL note. */
if (MEM_P (src) && MEM_READONLY_P (src))
{
rtx x = avoid_constant_pool_reference (src);
if (x != src && use_set)
{
rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX);
rtx old_rtx = note ? XEXP (note, 0) : SET_SRC (use_set);
rtx new_rtx = simplify_replace_rtx (old_rtx, src, x);
if (old_rtx != new_rtx)
set_unique_reg_note (use_insn, REG_EQUAL, copy_rtx (new_rtx));
}
return false;
}
if (asm_use >= 0)
return forward_propagate_asm (use, def_insn, def_set, reg);
/* Else try simplifying. */
if (DF_REF_TYPE (use) == DF_REF_REG_MEM_STORE)
{
loc = &SET_DEST (use_set);
set_reg_equal = false;
}
else if (!use_set)
{
loc = &INSN_VAR_LOCATION_LOC (use_insn);
set_reg_equal = false;
}
else
{
rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX);
if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE)
loc = &XEXP (note, 0);
else
loc = &SET_SRC (use_set);
/* Do not replace an existing REG_EQUAL note if the insn is not
recognized. Either we're already replacing in the note, or
we'll separately try plugging the definition in the note and
simplifying. */
set_reg_equal = (note == NULL_RTX);
}
if (GET_MODE (*loc) == VOIDmode)
mode = GET_MODE (SET_DEST (use_set));
else
mode = GET_MODE (*loc);
new_rtx = propagate_rtx (*loc, mode, reg, src,
optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)));
if (!new_rtx)
return false;
return try_fwprop_subst (use, loc, new_rtx, def_insn, set_reg_equal);
}
/* Given a use USE of an insn, if it has a single reaching
definition, try to forward propagate it into that insn. */
static void
forward_propagate_into (df_ref use)
{
df_ref def;
rtx def_insn, def_set, use_insn;
rtx parent;
if (DF_REF_FLAGS (use) & DF_REF_READ_WRITE)
return;
if (DF_REF_IS_ARTIFICIAL (use))
return;
/* Only consider uses that have a single definition. */
def = get_def_for_use (use);
if (!def)
return;
if (DF_REF_FLAGS (def) & DF_REF_READ_WRITE)
return;
if (DF_REF_IS_ARTIFICIAL (def))
return;
/* Do not propagate loop invariant definitions inside the loop. */
if (DF_REF_BB (def)->loop_father != DF_REF_BB (use)->loop_father)
return;
/* Check if the use is still present in the insn! */
use_insn = DF_REF_INSN (use);
if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE)
parent = find_reg_note (use_insn, REG_EQUAL, NULL_RTX);
else
parent = PATTERN (use_insn);
if (!reg_mentioned_p (DF_REF_REG (use), parent))
return;
def_insn = DF_REF_INSN (def);
if (multiple_sets (def_insn))
return;
def_set = single_set (def_insn);
if (!def_set)
return;
/* Only try one kind of propagation. If two are possible, we'll
do it on the following iterations. */
if (!forward_propagate_and_simplify (use, def_insn, def_set))
forward_propagate_subreg (use, def_insn, def_set);
}
static void
fwprop_init (void)
{
num_changes = 0;
calculate_dominance_info (CDI_DOMINATORS);
/* We do not always want to propagate into loops, so we have to find
loops and be careful about them. But we have to call flow_loops_find
before df_analyze, because flow_loops_find may introduce new jump
insns (sadly) if we are not working in cfglayout mode. */
loop_optimizer_init (0);
build_single_def_use_links ();
df_set_flags (DF_DEFER_INSN_RESCAN);
}
static void
fwprop_done (void)
{
loop_optimizer_finalize ();
VEC_free (df_ref, heap, use_def_ref);
free_dominance_info (CDI_DOMINATORS);
cleanup_cfg (0);
delete_trivially_dead_insns (get_insns (), max_reg_num ());
if (dump_file)
fprintf (dump_file,
"\nNumber of successful forward propagations: %d\n\n",
num_changes);
}
/* Main entry point. */
static bool
gate_fwprop (void)
{
return optimize > 0 && flag_forward_propagate;
}
static unsigned int
fwprop (void)
{
unsigned i;
fwprop_init ();
/* Go through all the uses. update_df will create new ones at the
end, and we'll go through them as well.
Do not forward propagate addresses into loops until after unrolling.
CSE did so because it was able to fix its own mess, but we are not. */
for (i = 0; i < DF_USES_TABLE_SIZE (); i++)
{
df_ref use = DF_USES_GET (i);
if (use)
if (DF_REF_TYPE (use) == DF_REF_REG_USE
|| DF_REF_BB (use)->loop_father == NULL
/* The outer most loop is not really a loop. */
|| loop_outer (DF_REF_BB (use)->loop_father) == NULL)
forward_propagate_into (use);
}
fwprop_done ();
return 0;
}
struct rtl_opt_pass pass_rtl_fwprop =
{
{
RTL_PASS,
"fwprop1", /* name */
gate_fwprop, /* gate */
fwprop, /* execute */
NULL, /* sub */
NULL, /* next */
0, /* static_pass_number */
TV_FWPROP, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish | TODO_verify_rtl_sharing |
TODO_dump_func /* todo_flags_finish */
}
};
static unsigned int
fwprop_addr (void)
{
unsigned i;
fwprop_init ();
/* Go through all the uses. update_df will create new ones at the
end, and we'll go through them as well. */
for (i = 0; i < DF_USES_TABLE_SIZE (); i++)
{
df_ref use = DF_USES_GET (i);
if (use)
if (DF_REF_TYPE (use) != DF_REF_REG_USE
&& DF_REF_BB (use)->loop_father != NULL
/* The outer most loop is not really a loop. */
&& loop_outer (DF_REF_BB (use)->loop_father) != NULL)
forward_propagate_into (use);
}
fwprop_done ();
return 0;
}
struct rtl_opt_pass pass_rtl_fwprop_addr =
{
{
RTL_PASS,
"fwprop2", /* name */
gate_fwprop, /* gate */
fwprop_addr, /* execute */
NULL, /* sub */
NULL, /* next */
0, /* static_pass_number */
TV_FWPROP, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish | TODO_verify_rtl_sharing |
TODO_dump_func /* todo_flags_finish */
}
};
|