1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664
6665
6666
6667
6668
6669
6670
6671
6672
6673
6674
6675
6676
6677
6678
6679
6680
6681
6682
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695
6696
6697
6698
6699
|
/* Subroutines used for code generation for RISC-V.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target for GNU compiler.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#define INCLUDE_STRING
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "target.h"
#include "tm.h"
#include "rtl.h"
#include "regs.h"
#include "insn-config.h"
#include "insn-attr.h"
#include "recog.h"
#include "output.h"
#include "alias.h"
#include "tree.h"
#include "stringpool.h"
#include "attribs.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "function.h"
#include "explow.h"
#include "memmodel.h"
#include "emit-rtl.h"
#include "reload.h"
#include "tm_p.h"
#include "basic-block.h"
#include "expr.h"
#include "optabs.h"
#include "bitmap.h"
#include "df.h"
#include "diagnostic.h"
#include "builtins.h"
#include "predict.h"
#include "tree-pass.h"
#include "opts.h"
#include "tm-constrs.h"
#include "rtl-iter.h"
/* This file should be included last. */
#include "target-def.h"
/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
&& XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
&& XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
/* Extract the symbol or label from UNSPEC wrapper X. */
#define UNSPEC_ADDRESS(X) \
XVECEXP (X, 0, 0)
/* Extract the symbol type from UNSPEC wrapper X. */
#define UNSPEC_ADDRESS_TYPE(X) \
((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
/* True if bit BIT is set in VALUE. */
#define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
/* Classifies an address.
ADDRESS_REG
A natural register + offset address. The register satisfies
riscv_valid_base_register_p and the offset is a const_arith_operand.
ADDRESS_LO_SUM
A LO_SUM rtx. The first operand is a valid base register and
the second operand is a symbolic address.
ADDRESS_CONST_INT
A signed 16-bit constant address.
ADDRESS_SYMBOLIC:
A constant symbolic address. */
enum riscv_address_type {
ADDRESS_REG,
ADDRESS_LO_SUM,
ADDRESS_CONST_INT,
ADDRESS_SYMBOLIC
};
/* Information about a function's frame layout. */
struct GTY(()) riscv_frame_info {
/* The size of the frame in bytes. */
poly_int64 total_size;
/* Bit X is set if the function saves or restores GPR X. */
unsigned int mask;
/* Likewise FPR X. */
unsigned int fmask;
/* How much the GPR save/restore routines adjust sp (or 0 if unused). */
unsigned save_libcall_adjustment;
/* Offsets of fixed-point and floating-point save areas from frame bottom */
poly_int64 gp_sp_offset;
poly_int64 fp_sp_offset;
/* Offset of virtual frame pointer from stack pointer/frame bottom */
poly_int64 frame_pointer_offset;
/* Offset of hard frame pointer from stack pointer/frame bottom */
poly_int64 hard_frame_pointer_offset;
/* The offset of arg_pointer_rtx from the bottom of the frame. */
poly_int64 arg_pointer_offset;
/* Reset this struct, clean all field to zero. */
void reset(void);
};
enum riscv_privilege_levels {
UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE
};
struct GTY(()) machine_function {
/* The number of extra stack bytes taken up by register varargs.
This area is allocated by the callee at the very top of the frame. */
int varargs_size;
/* True if current function is a naked function. */
bool naked_p;
/* True if current function is an interrupt function. */
bool interrupt_handler_p;
/* For an interrupt handler, indicates the privilege level. */
enum riscv_privilege_levels interrupt_mode;
/* True if attributes on current function have been checked. */
bool attributes_checked_p;
/* The current frame information, calculated by riscv_compute_frame_info. */
struct riscv_frame_info frame;
};
/* Information about a single argument. */
struct riscv_arg_info {
/* True if the argument is at least partially passed on the stack. */
bool stack_p;
/* The number of integer registers allocated to this argument. */
unsigned int num_gprs;
/* The offset of the first register used, provided num_gprs is nonzero.
If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
unsigned int gpr_offset;
/* The number of floating-point registers allocated to this argument. */
unsigned int num_fprs;
/* The offset of the first register used, provided num_fprs is nonzero. */
unsigned int fpr_offset;
};
/* Information about an address described by riscv_address_type.
ADDRESS_CONST_INT
No fields are used.
ADDRESS_REG
REG is the base register and OFFSET is the constant offset.
ADDRESS_LO_SUM
REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
is the type of symbol it references.
ADDRESS_SYMBOLIC
SYMBOL_TYPE is the type of symbol that the address references. */
struct riscv_address_info {
enum riscv_address_type type;
rtx reg;
rtx offset;
enum riscv_symbol_type symbol_type;
};
/* One stage in a constant building sequence. These sequences have
the form:
A = VALUE[0]
A = A CODE[1] VALUE[1]
A = A CODE[2] VALUE[2]
...
where A is an accumulator, each CODE[i] is a binary rtl operation
and each VALUE[i] is a constant integer. CODE[0] is undefined. */
struct riscv_integer_op {
enum rtx_code code;
unsigned HOST_WIDE_INT value;
};
/* The largest number of operations needed to load an integer constant.
The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
#define RISCV_MAX_INTEGER_OPS 8
/* Costs of various operations on the different architectures. */
struct riscv_tune_param
{
unsigned short fp_add[2];
unsigned short fp_mul[2];
unsigned short fp_div[2];
unsigned short int_mul[2];
unsigned short int_div[2];
unsigned short issue_rate;
unsigned short branch_cost;
unsigned short memory_cost;
unsigned short fmv_cost;
bool slow_unaligned_access;
};
/* Information about one micro-arch we know about. */
struct riscv_tune_info {
/* This micro-arch canonical name. */
const char *name;
/* Which automaton to use for tuning. */
enum riscv_microarchitecture_type microarchitecture;
/* Tuning parameters for this micro-arch. */
const struct riscv_tune_param *tune_param;
};
/* Global variables for machine-dependent things. */
/* Whether unaligned accesses execute very slowly. */
bool riscv_slow_unaligned_access_p;
/* Stack alignment to assume/maintain. */
unsigned riscv_stack_boundary;
/* If non-zero, this is an offset to be added to SP to redefine the CFA
when restoring the FP register from the stack. Only valid when generating
the epilogue. */
static int epilogue_cfa_sp_offset;
/* Which tuning parameters to use. */
static const struct riscv_tune_param *tune_param;
/* Which automaton to use for tuning. */
enum riscv_microarchitecture_type riscv_microarchitecture;
/* The number of chunks in a single vector register. */
poly_uint16 riscv_vector_chunks;
/* The number of bytes in a vector chunk. */
unsigned riscv_bytes_per_vector_chunk;
/* Index R is the smallest register class that contains register R. */
const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
GR_REGS, GR_REGS, GR_REGS, GR_REGS,
GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS,
JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS,
SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FRAME_REGS, FRAME_REGS, VL_REGS, VTYPE_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
NO_REGS, NO_REGS, NO_REGS, NO_REGS,
VM_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
VD_REGS, VD_REGS, VD_REGS, VD_REGS,
};
/* Costs to use when optimizing for rocket. */
static const struct riscv_tune_param rocket_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
{COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
{COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
{COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
1, /* issue_rate */
3, /* branch_cost */
5, /* memory_cost */
8, /* fmv_cost */
true, /* slow_unaligned_access */
};
/* Costs to use when optimizing for Sifive 7 Series. */
static const struct riscv_tune_param sifive_7_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
{COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
{COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
{COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
2, /* issue_rate */
4, /* branch_cost */
3, /* memory_cost */
8, /* fmv_cost */
true, /* slow_unaligned_access */
};
/* Costs to use when optimizing for T-HEAD c906. */
static const struct riscv_tune_param thead_c906_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
{COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
{COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
{COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
1, /* issue_rate */
3, /* branch_cost */
5, /* memory_cost */
8, /* fmv_cost */
false, /* slow_unaligned_access */
};
/* Costs to use when optimizing for size. */
static const struct riscv_tune_param optimize_size_tune_info = {
{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
{COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
1, /* issue_rate */
1, /* branch_cost */
2, /* memory_cost */
8, /* fmv_cost */
false, /* slow_unaligned_access */
};
static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
/* Defining target-specific uses of __attribute__. */
static const struct attribute_spec riscv_attribute_table[] =
{
/* Syntax: { name, min_len, max_len, decl_required, type_required,
function_type_required, affects_type_identity, handler,
exclude } */
/* The attribute telling no prologue/epilogue. */
{ "naked", 0, 0, true, false, false, false,
riscv_handle_fndecl_attribute, NULL },
/* This attribute generates prologue/epilogue for interrupt handlers. */
{ "interrupt", 0, 1, false, true, true, false,
riscv_handle_type_attribute, NULL },
/* The following two are used for the built-in properties of the Vector type
and are not used externally */
{"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
{"RVV type", 0, 0, false, true, false, true, NULL, NULL},
/* The last attribute spec is set to be NULL. */
{ NULL, 0, 0, false, false, false, false, NULL, NULL }
};
/* Order for the CLOBBERs/USEs of gpr_save. */
static const unsigned gpr_save_reg_order[] = {
INVALID_REGNUM, T0_REGNUM, T1_REGNUM, RETURN_ADDR_REGNUM,
S0_REGNUM, S1_REGNUM, S2_REGNUM, S3_REGNUM, S4_REGNUM,
S5_REGNUM, S6_REGNUM, S7_REGNUM, S8_REGNUM, S9_REGNUM,
S10_REGNUM, S11_REGNUM
};
/* A table describing all the processors GCC knows about. */
static const struct riscv_tune_info riscv_tune_info_table[] = {
#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
{ TUNE_NAME, PIPELINE_MODEL, & TUNE_INFO},
#include "riscv-cores.def"
};
void riscv_frame_info::reset(void)
{
total_size = 0;
mask = 0;
fmask = 0;
save_libcall_adjustment = 0;
gp_sp_offset = 0;
fp_sp_offset = 0;
frame_pointer_offset = 0;
hard_frame_pointer_offset = 0;
arg_pointer_offset = 0;
}
/* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
static unsigned int
riscv_min_arithmetic_precision (void)
{
return 32;
}
/* Return the riscv_tune_info entry for the given name string. */
static const struct riscv_tune_info *
riscv_parse_tune (const char *tune_string)
{
const riscv_cpu_info *cpu = riscv_find_cpu (tune_string);
if (cpu)
tune_string = cpu->tune;
for (unsigned i = 0; i < ARRAY_SIZE (riscv_tune_info_table); i++)
if (strcmp (riscv_tune_info_table[i].name, tune_string) == 0)
return riscv_tune_info_table + i;
error ("unknown cpu %qs for %<-mtune%>", tune_string);
return riscv_tune_info_table;
}
/* Helper function for riscv_build_integer; arguments are as for
riscv_build_integer. */
static int
riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
HOST_WIDE_INT value, machine_mode mode)
{
HOST_WIDE_INT low_part = CONST_LOW_PART (value);
int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost;
struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
if (SMALL_OPERAND (value) || LUI_OPERAND (value))
{
/* Simply ADDI or LUI. */
codes[0].code = UNKNOWN;
codes[0].value = value;
return 1;
}
if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
{
/* Simply BSETI. */
codes[0].code = UNKNOWN;
codes[0].value = value;
/* RISC-V sign-extends all 32bit values that live in a 32bit
register. To avoid paradoxes, we thus need to use the
sign-extended (negative) representation (-1 << 31) for the
value, if we want to build (1 << 31) in SImode. This will
then expand to an LUI instruction. */
if (TARGET_64BIT && mode == SImode && value == (HOST_WIDE_INT_1U << 31))
codes[0].value = (HOST_WIDE_INT_M1U << 31);
return 1;
}
/* End with ADDI. When constructing HImode constants, do not generate any
intermediate value that is not itself a valid HImode constant. The
XORI case below will handle those remaining HImode constants. */
if (low_part != 0
&& (mode != HImode
|| value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1)))
{
HOST_WIDE_INT upper_part = value - low_part;
if (mode != VOIDmode)
upper_part = trunc_int_for_mode (value - low_part, mode);
alt_cost = 1 + riscv_build_integer_1 (alt_codes, upper_part, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = PLUS;
alt_codes[alt_cost-1].value = low_part;
memcpy (codes, alt_codes, sizeof (alt_codes));
cost = alt_cost;
}
}
/* End with XORI. */
if (cost > 2 && (low_part < 0 || mode == HImode))
{
alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = XOR;
alt_codes[alt_cost-1].value = low_part;
memcpy (codes, alt_codes, sizeof (alt_codes));
cost = alt_cost;
}
}
/* Eliminate trailing zeros and end with SLLI. */
if (cost > 2 && (value & 1) == 0)
{
int shift = ctz_hwi (value);
unsigned HOST_WIDE_INT x = value;
x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift);
/* Don't eliminate the lower 12 bits if LUI might apply. */
if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS))
shift -= IMM_BITS, x <<= IMM_BITS;
alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = ASHIFT;
alt_codes[alt_cost-1].value = shift;
memcpy (codes, alt_codes, sizeof (alt_codes));
cost = alt_cost;
}
}
if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
{
int leading_ones = clz_hwi (~value);
int trailing_ones = ctz_hwi (~value);
/* If all bits are one except a few that are zero, and the zero bits
are within a range of 11 bits, and at least one of the upper 32-bits
is a zero, then we can generate a constant by loading a small
negative constant and rotating. */
if (leading_ones < 32
&& ((64 - leading_ones - trailing_ones) < 12))
{
codes[0].code = UNKNOWN;
/* The sign-bit might be zero, so just rotate to be safe. */
codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones)
| (value << (64 - trailing_ones)));
codes[1].code = ROTATERT;
codes[1].value = 64 - trailing_ones;
cost = 2;
}
/* Handle the case where the 11 bit range of zero bits wraps around. */
else
{
int upper_trailing_ones = ctz_hwi (~value >> 32);
int lower_leading_ones = clz_hwi (~value << 32);
if (upper_trailing_ones < 32 && lower_leading_ones < 32
&& ((64 - upper_trailing_ones - lower_leading_ones) < 12))
{
codes[0].code = UNKNOWN;
/* The sign-bit might be zero, so just rotate to be safe. */
codes[0].value = ((value << (32 - upper_trailing_ones))
| ((unsigned HOST_WIDE_INT) value
>> (32 + upper_trailing_ones)));
codes[1].code = ROTATERT;
codes[1].value = 32 - upper_trailing_ones;
cost = 2;
}
}
}
gcc_assert (cost <= RISCV_MAX_INTEGER_OPS);
return cost;
}
/* Fill CODES with a sequence of rtl operations to load VALUE.
Return the number of operations needed. */
static int
riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value,
machine_mode mode)
{
int cost = riscv_build_integer_1 (codes, value, mode);
/* Eliminate leading zeros and end with SRLI. */
if (value > 0 && cost > 2)
{
struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS];
int alt_cost, shift = clz_hwi (value);
HOST_WIDE_INT shifted_val;
/* Try filling trailing bits with 1s. */
shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1);
alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = LSHIFTRT;
alt_codes[alt_cost-1].value = shift;
memcpy (codes, alt_codes, sizeof (alt_codes));
cost = alt_cost;
}
/* Try filling trailing bits with 0s. */
shifted_val = value << shift;
alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode);
if (alt_cost < cost)
{
alt_codes[alt_cost-1].code = LSHIFTRT;
alt_codes[alt_cost-1].value = shift;
memcpy (codes, alt_codes, sizeof (alt_codes));
cost = alt_cost;
}
}
return cost;
}
/* Return the cost of constructing VAL in the event that a scratch
register is available. */
static int
riscv_split_integer_cost (HOST_WIDE_INT val)
{
int cost;
unsigned HOST_WIDE_INT loval = sext_hwi (val, 32);
unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
cost = 2 + riscv_build_integer (codes, loval, VOIDmode);
if (loval != hival)
cost += riscv_build_integer (codes, hival, VOIDmode);
return cost;
}
/* Return the cost of constructing the integer constant VAL. */
static int
riscv_integer_cost (HOST_WIDE_INT val)
{
struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
return MIN (riscv_build_integer (codes, val, VOIDmode),
riscv_split_integer_cost (val));
}
/* Try to split a 64b integer into 32b parts, then reassemble. */
static rtx
riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)
{
unsigned HOST_WIDE_INT loval = sext_hwi (val, 32);
unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32);
rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode);
riscv_move_integer (hi, hi, hival, mode, FALSE);
riscv_move_integer (lo, lo, loval, mode, FALSE);
hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32));
hi = force_reg (mode, hi);
return gen_rtx_fmt_ee (PLUS, mode, hi, lo);
}
/* Return true if X is a thread-local symbol. */
static bool
riscv_tls_symbol_p (const_rtx x)
{
return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0;
}
/* Return true if symbol X binds locally. */
static bool
riscv_symbol_binds_local_p (const_rtx x)
{
if (SYMBOL_REF_P (x))
return (SYMBOL_REF_DECL (x)
? targetm.binds_local_p (SYMBOL_REF_DECL (x))
: SYMBOL_REF_LOCAL_P (x));
else
return false;
}
/* Return the method that should be used to access SYMBOL_REF or
LABEL_REF X. */
static enum riscv_symbol_type
riscv_classify_symbol (const_rtx x)
{
if (riscv_tls_symbol_p (x))
return SYMBOL_TLS;
if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x))
return SYMBOL_GOT_DISP;
return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL;
}
/* Classify the base of symbolic expression X. */
enum riscv_symbol_type
riscv_classify_symbolic_expression (rtx x)
{
rtx offset;
split_const (x, &x, &offset);
if (UNSPEC_ADDRESS_P (x))
return UNSPEC_ADDRESS_TYPE (x);
return riscv_classify_symbol (x);
}
/* Return true if X is a symbolic constant. If it is, store the type of
the symbol in *SYMBOL_TYPE. */
bool
riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type)
{
rtx offset;
split_const (x, &x, &offset);
if (UNSPEC_ADDRESS_P (x))
{
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
x = UNSPEC_ADDRESS (x);
}
else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
*symbol_type = riscv_classify_symbol (x);
else
return false;
if (offset == const0_rtx)
return true;
/* Nonzero offsets are only valid for references that don't use the GOT. */
switch (*symbol_type)
{
case SYMBOL_ABSOLUTE:
case SYMBOL_PCREL:
case SYMBOL_TLS_LE:
/* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
return sext_hwi (INTVAL (offset), 32) == INTVAL (offset);
default:
return false;
}
}
/* Returns the number of instructions necessary to reference a symbol. */
static int riscv_symbol_insns (enum riscv_symbol_type type)
{
switch (type)
{
case SYMBOL_TLS: return 0; /* Depends on the TLS model. */
case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference. */
case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */
case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */
case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */
default: gcc_unreachable ();
}
}
/* Implement TARGET_LEGITIMATE_CONSTANT_P. */
static bool
riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
return riscv_const_insns (x) > 0;
}
/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
static bool
riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
enum riscv_symbol_type type;
rtx base, offset;
/* There's no way to calculate VL-based values using relocations. */
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
if (GET_CODE (*iter) == CONST_POLY_INT)
return true;
/* There is no assembler syntax for expressing an address-sized
high part. */
if (GET_CODE (x) == HIGH)
return true;
split_const (x, &base, &offset);
if (riscv_symbolic_constant_p (base, &type))
{
/* As an optimization, don't spill symbolic constants that are as
cheap to rematerialize as to access in the constant pool. */
if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0)
return true;
/* As an optimization, avoid needlessly generate dynamic relocations. */
if (flag_pic)
return true;
}
/* TLS symbols must be computed by riscv_legitimize_move. */
if (tls_referenced_p (x))
return true;
return false;
}
/* Return true if register REGNO is a valid base register for mode MODE.
STRICT_P is true if REG_OK_STRICT is in effect. */
int
riscv_regno_mode_ok_for_base_p (int regno,
machine_mode mode ATTRIBUTE_UNUSED,
bool strict_p)
{
if (!HARD_REGISTER_NUM_P (regno))
{
if (!strict_p)
return true;
regno = reg_renumber[regno];
}
/* These fake registers will be eliminated to either the stack or
hard frame pointer, both of which are usually valid base registers.
Reload deals with the cases where the eliminated form isn't valid. */
if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
return true;
return GP_REG_P (regno);
}
/* Return true if X is a valid base register for mode MODE.
STRICT_P is true if REG_OK_STRICT is in effect. */
static bool
riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
{
if (!strict_p && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
return (REG_P (x)
&& riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
}
/* Return true if, for every base register BASE_REG, (plus BASE_REG X)
can address a value of mode MODE. */
static bool
riscv_valid_offset_p (rtx x, machine_mode mode)
{
/* Check that X is a signed 12-bit number. */
if (!const_arith_operand (x, Pmode))
return false;
/* We may need to split multiword moves, so make sure that every word
is accessible. */
if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD
&& !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode).to_constant () - UNITS_PER_WORD))
return false;
return true;
}
/* Should a symbol of type SYMBOL_TYPE should be split in two? */
bool
riscv_split_symbol_type (enum riscv_symbol_type symbol_type)
{
if (symbol_type == SYMBOL_TLS_LE)
return true;
if (!TARGET_EXPLICIT_RELOCS)
return false;
return symbol_type == SYMBOL_ABSOLUTE || symbol_type == SYMBOL_PCREL;
}
/* Return true if a LO_SUM can address a value of mode MODE when the
LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
is used when the mode is BLKmode. */
static bool
riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode,
rtx x)
{
int align, size;
/* Check that symbols of type SYMBOL_TYPE can be used to access values
of mode MODE. */
if (riscv_symbol_insns (sym_type) == 0)
return false;
/* Check that there is a known low-part relocation. */
if (!riscv_split_symbol_type (sym_type))
return false;
/* We can't tell size or alignment when we have BLKmode, so try extracing a
decl from the symbol if possible. */
if (mode == BLKmode)
{
rtx offset;
/* Extract the symbol from the LO_SUM operand, if any. */
split_const (x, &x, &offset);
/* Might be a CODE_LABEL. We can compute align but not size for that,
so don't bother trying to handle it. */
if (!SYMBOL_REF_P (x))
return false;
/* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
align = (SYMBOL_REF_DECL (x)
? DECL_ALIGN (SYMBOL_REF_DECL (x))
: 1);
size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x))
? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x)))
: 2*BITS_PER_WORD);
}
else
{
align = GET_MODE_ALIGNMENT (mode);
size = GET_MODE_BITSIZE (mode).to_constant ();
}
/* We may need to split multiword moves, so make sure that each word
can be accessed without inducing a carry. */
if (size > BITS_PER_WORD
&& (!TARGET_STRICT_ALIGN || size > align))
return false;
return true;
}
/* Return true if mode is the RVV enabled mode.
For example: 'VNx1DI' mode is disabled if MIN_VLEN == 32.
'VNx1SI' mode is enabled if MIN_VLEN == 32. */
bool
riscv_v_ext_vector_mode_p (machine_mode mode)
{
#define ENTRY(MODE, REQUIREMENT) \
case MODE##mode: \
return REQUIREMENT;
switch (mode)
{
#include "riscv-vector-switch.def"
default:
return false;
}
return false;
}
/* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
NUNITS size for corresponding machine_mode. */
poly_int64
riscv_v_adjust_nunits (machine_mode mode, int scale)
{
if (riscv_v_ext_vector_mode_p (mode))
return riscv_vector_chunks * scale;
return scale;
}
/* Return true if X is a valid address for machine mode MODE. If it is,
fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
effect. */
static bool
riscv_classify_address (struct riscv_address_info *info, rtx x,
machine_mode mode, bool strict_p)
{
switch (GET_CODE (x))
{
case REG:
case SUBREG:
info->type = ADDRESS_REG;
info->reg = x;
info->offset = const0_rtx;
return riscv_valid_base_register_p (info->reg, mode, strict_p);
case PLUS:
/* RVV load/store disallow any offset. */
if (riscv_v_ext_vector_mode_p (mode))
return false;
info->type = ADDRESS_REG;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
return (riscv_valid_base_register_p (info->reg, mode, strict_p)
&& riscv_valid_offset_p (info->offset, mode));
case LO_SUM:
/* RVV load/store disallow LO_SUM. */
if (riscv_v_ext_vector_mode_p (mode))
return false;
info->type = ADDRESS_LO_SUM;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
/* We have to trust the creator of the LO_SUM to do something vaguely
sane. Target-independent code that creates a LO_SUM should also
create and verify the matching HIGH. Target-independent code that
adds an offset to a LO_SUM must prove that the offset will not
induce a carry. Failure to do either of these things would be
a bug, and we are not required to check for it here. The RISC-V
backend itself should only create LO_SUMs for valid symbolic
constants, with the high part being either a HIGH or a copy
of _gp. */
info->symbol_type
= riscv_classify_symbolic_expression (info->offset);
return (riscv_valid_base_register_p (info->reg, mode, strict_p)
&& riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset));
case CONST_INT:
/* RVV load/store disallow CONST_INT. */
if (riscv_v_ext_vector_mode_p (mode))
return false;
/* Small-integer addresses don't occur very often, but they
are legitimate if x0 is a valid base register. */
info->type = ADDRESS_CONST_INT;
return SMALL_OPERAND (INTVAL (x));
default:
return false;
}
}
/* Implement TARGET_LEGITIMATE_ADDRESS_P. */
static bool
riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
{
struct riscv_address_info addr;
return riscv_classify_address (&addr, x, mode, strict_p);
}
/* Return true if hard reg REGNO can be used in compressed instructions. */
static bool
riscv_compressed_reg_p (int regno)
{
/* x8-x15/f8-f15 are compressible registers. */
return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
|| IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
}
/* Return true if x is an unsigned 5-bit immediate scaled by 4. */
static bool
riscv_compressed_lw_offset_p (rtx x)
{
return (CONST_INT_P (x)
&& (INTVAL (x) & 3) == 0
&& IN_RANGE (INTVAL (x), 0, CSW_MAX_OFFSET));
}
/* Return true if load/store from/to address x can be compressed. */
static bool
riscv_compressed_lw_address_p (rtx x)
{
struct riscv_address_info addr;
bool result = riscv_classify_address (&addr, x, GET_MODE (x),
reload_completed);
/* Return false if address is not compressed_reg + small_offset. */
if (!result
|| addr.type != ADDRESS_REG
/* Before reload, assume all registers are OK. */
|| (reload_completed
&& !riscv_compressed_reg_p (REGNO (addr.reg))
&& addr.reg != stack_pointer_rtx)
|| !riscv_compressed_lw_offset_p (addr.offset))
return false;
return result;
}
/* Return the number of instructions needed to load or store a value
of mode MODE at address X. Return 0 if X isn't valid for MODE.
Assume that multiword moves may need to be split into word moves
if MIGHT_SPLIT_P, otherwise assume that a single load or store is
enough. */
int
riscv_address_insns (rtx x, machine_mode mode, bool might_split_p)
{
struct riscv_address_info addr = {};
int n = 1;
if (!riscv_classify_address (&addr, x, mode, false))
{
/* This could be a pattern from the pic.md file. In which case we want
this address to always have a cost of 3 to make it as expensive as the
most expensive symbol. This prevents constant propagation from
preferring symbols over register plus offset. */
return 3;
}
/* BLKmode is used for single unaligned loads and stores and should
not count as a multiword mode. */
if (!riscv_v_ext_vector_mode_p (mode) && mode != BLKmode && might_split_p)
n += (GET_MODE_SIZE (mode).to_constant () + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
if (addr.type == ADDRESS_LO_SUM)
n += riscv_symbol_insns (addr.symbol_type) - 1;
return n;
}
/* Return the number of instructions needed to load constant X.
Return 0 if X isn't a valid constant. */
int
riscv_const_insns (rtx x)
{
enum riscv_symbol_type symbol_type;
rtx offset;
switch (GET_CODE (x))
{
case HIGH:
if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type)
|| !riscv_split_symbol_type (symbol_type))
return 0;
/* This is simply an LUI. */
return 1;
case CONST_INT:
{
int cost = riscv_integer_cost (INTVAL (x));
/* Force complicated constants to memory. */
return cost < 4 ? cost : 0;
}
case CONST_DOUBLE:
case CONST_VECTOR:
/* We can use x0 to load floating-point zero. */
return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
case CONST:
/* See if we can refer to X directly. */
if (riscv_symbolic_constant_p (x, &symbol_type))
return riscv_symbol_insns (symbol_type);
/* Otherwise try splitting the constant into a base and offset. */
split_const (x, &x, &offset);
if (offset != 0)
{
int n = riscv_const_insns (x);
if (n != 0)
return n + riscv_integer_cost (INTVAL (offset));
}
return 0;
case SYMBOL_REF:
case LABEL_REF:
return riscv_symbol_insns (riscv_classify_symbol (x));
/* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
instruction and several scalar shift or mult instructions,
it is so far unknown. We set it to 4 temporarily. */
case CONST_POLY_INT:
return 4;
default:
return 0;
}
}
/* X is a doubleword constant that can be handled by splitting it into
two words and loading each word separately. Return the number of
instructions required to do this. */
int
riscv_split_const_insns (rtx x)
{
unsigned int low, high;
low = riscv_const_insns (riscv_subword (x, false));
high = riscv_const_insns (riscv_subword (x, true));
gcc_assert (low > 0 && high > 0);
return low + high;
}
/* Return the number of instructions needed to implement INSN,
given that it loads from or stores to MEM. */
int
riscv_load_store_insns (rtx mem, rtx_insn *insn)
{
machine_mode mode;
bool might_split_p;
rtx set;
gcc_assert (MEM_P (mem));
mode = GET_MODE (mem);
/* Try to prove that INSN does not need to be split. */
might_split_p = true;
if (GET_MODE_BITSIZE (mode).to_constant () <= 32)
might_split_p = false;
else if (GET_MODE_BITSIZE (mode).to_constant () == 64)
{
set = single_set (insn);
if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
might_split_p = false;
}
return riscv_address_insns (XEXP (mem, 0), mode, might_split_p);
}
/* Emit a move from SRC to DEST. Assume that the move expanders can
handle all moves if !can_create_pseudo_p (). The distinction is
important because, unlike emit_move_insn, the move expanders know
how to force Pmode objects into the constant pool even when the
constant pool address is not itself legitimate. */
rtx
riscv_emit_move (rtx dest, rtx src)
{
return (can_create_pseudo_p ()
? emit_move_insn (dest, src)
: emit_move_insn_1 (dest, src));
}
/* Emit an instruction of the form (set TARGET SRC). */
static rtx
riscv_emit_set (rtx target, rtx src)
{
emit_insn (gen_rtx_SET (target, src));
return target;
}
/* Emit an instruction of the form (set DEST (CODE X Y)). */
static rtx
riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y)
{
return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y));
}
/* Compute (CODE X Y) and store the result in a new register
of mode MODE. Return that new register. */
static rtx
riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y)
{
return riscv_emit_binary (code, gen_reg_rtx (mode), x, y);
}
static rtx
riscv_swap_instruction (rtx inst)
{
gcc_assert (GET_MODE (inst) == SImode);
if (BYTES_BIG_ENDIAN)
inst = expand_unop (SImode, bswap_optab, inst, gen_reg_rtx (SImode), 1);
return inst;
}
/* Copy VALUE to a register and return that register. If new pseudos
are allowed, copy it into a new register, otherwise use DEST. */
static rtx
riscv_force_temporary (rtx dest, rtx value, bool in_splitter)
{
/* We can't call gen_reg_rtx from a splitter, because this might realloc
the regno_reg_rtx array, which would invalidate reg rtx pointers in the
combine undo buffer. */
if (can_create_pseudo_p () && !in_splitter)
return force_reg (Pmode, value);
else
{
riscv_emit_move (dest, value);
return dest;
}
}
/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
then add CONST_INT OFFSET to the result. */
static rtx
riscv_unspec_address_offset (rtx base, rtx offset,
enum riscv_symbol_type symbol_type)
{
base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
UNSPEC_ADDRESS_FIRST + symbol_type);
if (offset != const0_rtx)
base = gen_rtx_PLUS (Pmode, base, offset);
return gen_rtx_CONST (Pmode, base);
}
/* Return an UNSPEC address with underlying address ADDRESS and symbol
type SYMBOL_TYPE. */
rtx
riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type)
{
rtx base, offset;
split_const (address, &base, &offset);
return riscv_unspec_address_offset (base, offset, symbol_type);
}
/* If OP is an UNSPEC address, return the address to which it refers,
otherwise return OP itself. */
static rtx
riscv_strip_unspec_address (rtx op)
{
rtx base, offset;
split_const (op, &base, &offset);
if (UNSPEC_ADDRESS_P (base))
op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
return op;
}
/* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
high part to BASE and return the result. Just return BASE otherwise.
TEMP is as for riscv_force_temporary.
The returned expression can be used as the first operand to a LO_SUM. */
static rtx
riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type)
{
addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type));
return riscv_force_temporary (temp, addr, FALSE);
}
/* Load an entry from the GOT for a TLS GD access. */
static rtx riscv_got_load_tls_gd (rtx dest, rtx sym)
{
if (Pmode == DImode)
return gen_got_load_tls_gddi (dest, sym);
else
return gen_got_load_tls_gdsi (dest, sym);
}
/* Load an entry from the GOT for a TLS IE access. */
static rtx riscv_got_load_tls_ie (rtx dest, rtx sym)
{
if (Pmode == DImode)
return gen_got_load_tls_iedi (dest, sym);
else
return gen_got_load_tls_iesi (dest, sym);
}
/* Add in the thread pointer for a TLS LE access. */
static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym)
{
rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
if (Pmode == DImode)
return gen_tls_add_tp_ledi (dest, base, tp, sym);
else
return gen_tls_add_tp_lesi (dest, base, tp, sym);
}
/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
it appears in a MEM of that mode. Return true if ADDR is a legitimate
constant in that context and can be split into high and low parts.
If so, and if LOW_OUT is nonnull, emit the high part and store the
low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
TEMP is as for riscv_force_temporary and is used to load the high
part into a register.
When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
a legitimize SET_SRC for an .md pattern, otherwise the low part
is guaranteed to be a legitimate address for mode MODE. */
bool
riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out,
bool in_splitter)
{
enum riscv_symbol_type symbol_type;
if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE)
|| !riscv_symbolic_constant_p (addr, &symbol_type)
|| riscv_symbol_insns (symbol_type) == 0
|| !riscv_split_symbol_type (symbol_type))
return false;
if (low_out)
switch (symbol_type)
{
case SYMBOL_ABSOLUTE:
{
rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
high = riscv_force_temporary (temp, high, in_splitter);
*low_out = gen_rtx_LO_SUM (Pmode, high, addr);
}
break;
case SYMBOL_PCREL:
{
static unsigned seqno;
char buf[32];
rtx label;
ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno);
gcc_assert ((size_t) bytes < sizeof (buf));
label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL;
/* ??? Ugly hack to make weak symbols work. May need to change the
RTL for the auipc and/or low patterns to get a better fix for
this. */
if (! nonzero_address_p (addr))
SYMBOL_REF_WEAK (label) = 1;
if (temp == NULL)
temp = gen_reg_rtx (Pmode);
if (Pmode == DImode)
emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno)));
else
emit_insn (gen_auipcsi (temp, copy_rtx (addr), GEN_INT (seqno)));
*low_out = gen_rtx_LO_SUM (Pmode, temp, label);
seqno++;
}
break;
default:
gcc_unreachable ();
}
return true;
}
/* Return a legitimate address for REG + OFFSET. TEMP is as for
riscv_force_temporary; it is only needed when OFFSET is not a
SMALL_OPERAND. */
static rtx
riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
{
if (!SMALL_OPERAND (offset))
{
rtx high;
/* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
The addition inside the macro CONST_HIGH_PART may cause an
overflow, so we need to force a sign-extension check. */
high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
offset = CONST_LOW_PART (offset);
high = riscv_force_temporary (temp, high, FALSE);
reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg),
FALSE);
}
return plus_constant (Pmode, reg, offset);
}
/* The __tls_get_attr symbol. */
static GTY(()) rtx riscv_tls_symbol;
/* Return an instruction sequence that calls __tls_get_addr. SYM is
the TLS symbol we are referencing and TYPE is the symbol type to use
(either global dynamic or local dynamic). RESULT is an RTX for the
return value location. */
static rtx_insn *
riscv_call_tls_get_addr (rtx sym, rtx result)
{
rtx a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST), func;
rtx_insn *insn;
if (!riscv_tls_symbol)
riscv_tls_symbol = init_one_libfunc ("__tls_get_addr");
func = gen_rtx_MEM (FUNCTION_MODE, riscv_tls_symbol);
start_sequence ();
emit_insn (riscv_got_load_tls_gd (a0, sym));
insn = emit_call_insn (gen_call_value (result, func, const0_rtx, NULL));
RTL_CONST_CALL_P (insn) = 1;
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
insn = get_insns ();
end_sequence ();
return insn;
}
/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
its address. The return value will be both a valid address and a valid
SET_SRC (either a REG or a LO_SUM). */
static rtx
riscv_legitimize_tls_address (rtx loc)
{
rtx dest, tp, tmp;
enum tls_model model = SYMBOL_REF_TLS_MODEL (loc);
#if 0
/* TLS copy relocs are now deprecated and should not be used. */
/* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
if (!flag_pic)
model = TLS_MODEL_LOCAL_EXEC;
#endif
switch (model)
{
case TLS_MODEL_LOCAL_DYNAMIC:
/* Rely on section anchors for the optimization that LDM TLS
provides. The anchor's address is loaded with GD TLS. */
case TLS_MODEL_GLOBAL_DYNAMIC:
tmp = gen_rtx_REG (Pmode, GP_RETURN);
dest = gen_reg_rtx (Pmode);
emit_libcall_block (riscv_call_tls_get_addr (loc, tmp), dest, tmp, loc);
break;
case TLS_MODEL_INITIAL_EXEC:
/* la.tls.ie; tp-relative add */
tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
tmp = gen_reg_rtx (Pmode);
emit_insn (riscv_got_load_tls_ie (tmp, loc));
dest = gen_reg_rtx (Pmode);
emit_insn (gen_add3_insn (dest, tmp, tp));
break;
case TLS_MODEL_LOCAL_EXEC:
tmp = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE);
dest = gen_reg_rtx (Pmode);
emit_insn (riscv_tls_add_tp_le (dest, tmp, loc));
dest = gen_rtx_LO_SUM (Pmode, dest,
riscv_unspec_address (loc, SYMBOL_TLS_LE));
break;
default:
gcc_unreachable ();
}
return dest;
}
/* If X is not a valid address for mode MODE, force it into a register. */
static rtx
riscv_force_address (rtx x, machine_mode mode)
{
if (!riscv_legitimate_address_p (mode, x, false))
x = force_reg (Pmode, x);
return x;
}
/* Modify base + offset so that offset fits within a compressed load/store insn
and the excess is added to base. */
static rtx
riscv_shorten_lw_offset (rtx base, HOST_WIDE_INT offset)
{
rtx addr, high;
/* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
into HIGH. */
high = GEN_INT (offset & ~CSW_MAX_OFFSET);
offset &= CSW_MAX_OFFSET;
if (!SMALL_OPERAND (INTVAL (high)))
high = force_reg (Pmode, high);
base = force_reg (Pmode, gen_rtx_PLUS (Pmode, high, base));
addr = plus_constant (Pmode, base, offset);
return addr;
}
/* This function is used to implement LEGITIMIZE_ADDRESS. If X can
be legitimized in a way that the generic machinery might not expect,
return a new address, otherwise return NULL. MODE is the mode of
the memory being accessed. */
static rtx
riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
machine_mode mode)
{
rtx addr;
if (riscv_tls_symbol_p (x))
return riscv_legitimize_tls_address (x);
/* See if the address can split into a high part and a LO_SUM. */
if (riscv_split_symbol (NULL, x, mode, &addr, FALSE))
return riscv_force_address (addr, mode);
/* Handle BASE + OFFSET. */
if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) != 0)
{
rtx base = XEXP (x, 0);
HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
if (!riscv_valid_base_register_p (base, mode, false))
base = copy_to_mode_reg (Pmode, base);
if (optimize_function_for_size_p (cfun)
&& (strcmp (current_pass->name, "shorten_memrefs") == 0)
&& mode == SImode)
/* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
possible compressed load/store. */
addr = riscv_shorten_lw_offset (base, offset);
else
addr = riscv_add_offset (NULL, base, offset);
return riscv_force_address (addr, mode);
}
return x;
}
/* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
is the original src mode before promotion. */
void
riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,
machine_mode orig_mode, bool in_splitter)
{
struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];
machine_mode mode;
int i, num_ops;
rtx x;
/* We can't call gen_reg_rtx from a splitter, because this might realloc
the regno_reg_rtx array, which would invalidate reg rtx pointers in the
combine undo buffer. */
bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter;
mode = GET_MODE (dest);
/* We use the original mode for the riscv_build_integer call, because HImode
values are given special treatment. */
num_ops = riscv_build_integer (codes, value, orig_mode);
if (can_create_pseudo && num_ops > 2 /* not a simple constant */
&& num_ops >= riscv_split_integer_cost (value))
x = riscv_split_integer (value, mode);
else
{
codes[0].value = trunc_int_for_mode (codes[0].value, mode);
/* Apply each binary operation to X. */
x = GEN_INT (codes[0].value);
for (i = 1; i < num_ops; i++)
{
if (!can_create_pseudo)
x = riscv_emit_set (temp, x);
else
x = force_reg (mode, x);
codes[i].value = trunc_int_for_mode (codes[i].value, mode);
x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
}
}
riscv_emit_set (dest, x);
}
/* Subroutine of riscv_legitimize_move. Move constant SRC into register
DEST given that SRC satisfies immediate_operand but doesn't satisfy
move_operand. */
static void
riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
{
rtx base, offset;
/* Split moves of big integers into smaller pieces. */
if (splittable_const_int_operand (src, mode))
{
riscv_move_integer (dest, dest, INTVAL (src), mode, FALSE);
return;
}
/* Split moves of symbolic constants into high/low pairs. */
if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE))
{
riscv_emit_set (dest, src);
return;
}
/* Generate the appropriate access sequences for TLS symbols. */
if (riscv_tls_symbol_p (src))
{
riscv_emit_move (dest, riscv_legitimize_tls_address (src));
return;
}
/* If we have (const (plus symbol offset)), and that expression cannot
be forced into memory, load the symbol first and add in the offset. Also
prefer to do this even if the constant _can_ be forced into memory, as it
usually produces better code. */
split_const (src, &base, &offset);
if (offset != const0_rtx
&& (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ()))
{
base = riscv_force_temporary (dest, base, FALSE);
riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset)));
return;
}
src = force_const_mem (mode, src);
/* When using explicit relocs, constant pool references are sometimes
not legitimate addresses. */
riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE);
riscv_emit_move (dest, src);
}
/* Report when we try to do something that requires vector when vector is
disabled. This is an error of last resort and isn't very high-quality. It
usually involves attempts to measure the vector length in some way. */
static void
riscv_report_v_required (void)
{
static bool reported_p = false;
/* Avoid reporting a slew of messages for a single oversight. */
if (reported_p)
return;
error ("this operation requires the RVV ISA extension");
inform (input_location, "you can enable RVV using the command-line"
" option %<-march%>, or by using the %<target%>"
" attribute or pragma");
reported_p = true;
}
/* Helper function to operation for rtx_code CODE. */
static void
riscv_expand_op (enum rtx_code code, machine_mode mode, rtx op0, rtx op1,
rtx op2)
{
if (can_create_pseudo_p ())
{
rtx result;
if (GET_RTX_CLASS (code) == RTX_UNARY)
result = expand_simple_unop (mode, code, op1, NULL_RTX, false);
else
result = expand_simple_binop (mode, code, op1, op2, NULL_RTX, false,
OPTAB_DIRECT);
riscv_emit_move (op0, result);
}
else
{
rtx pat;
/* The following implementation is for prologue and epilogue.
Because prologue and epilogue can not use pseudo register.
We can't using expand_simple_binop or expand_simple_unop. */
if (GET_RTX_CLASS (code) == RTX_UNARY)
pat = gen_rtx_fmt_e (code, mode, op1);
else
pat = gen_rtx_fmt_ee (code, mode, op1, op2);
emit_insn (gen_rtx_SET (op0, pat));
}
}
/* Expand mult operation with constant integer, multiplicand also used as a
* temporary register. */
static void
riscv_expand_mult_with_const_int (machine_mode mode, rtx dest, rtx multiplicand,
int multiplier)
{
if (multiplier == 0)
{
riscv_emit_move (dest, GEN_INT (0));
return;
}
bool neg_p = multiplier < 0;
int multiplier_abs = abs (multiplier);
if (multiplier_abs == 1)
{
if (neg_p)
riscv_expand_op (NEG, mode, dest, multiplicand, NULL_RTX);
else
riscv_emit_move (dest, multiplicand);
}
else
{
if (pow2p_hwi (multiplier_abs))
{
/*
multiplicand = [BYTES_PER_RISCV_VECTOR].
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 8].
Sequence:
csrr a5, vlenb
slli a5, a5, 3
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 8].
Sequence:
csrr a5, vlenb
slli a5, a5, 3
neg a5, a5
*/
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
gen_int_mode (exact_log2 (multiplier_abs), QImode));
if (neg_p)
riscv_expand_op (NEG, mode, dest, dest, NULL_RTX);
}
else if (pow2p_hwi (multiplier_abs + 1))
{
/*
multiplicand = [BYTES_PER_RISCV_VECTOR].
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 7].
Sequence:
csrr a5, vlenb
slli a4, a5, 3
sub a5, a4, a5
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 7].
Sequence:
csrr a5, vlenb
slli a4, a5, 3
sub a5, a4, a5 + neg a5, a5 => sub a5, a5, a4
*/
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
gen_int_mode (exact_log2 (multiplier_abs + 1),
QImode));
if (neg_p)
riscv_expand_op (MINUS, mode, dest, multiplicand, dest);
else
riscv_expand_op (MINUS, mode, dest, dest, multiplicand);
}
else if (pow2p_hwi (multiplier - 1))
{
/*
multiplicand = [BYTES_PER_RISCV_VECTOR].
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 9].
Sequence:
csrr a5, vlenb
slli a4, a5, 3
add a5, a4, a5
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 9].
Sequence:
csrr a5, vlenb
slli a4, a5, 3
add a5, a4, a5
neg a5, a5
*/
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
gen_int_mode (exact_log2 (multiplier_abs - 1),
QImode));
riscv_expand_op (PLUS, mode, dest, dest, multiplicand);
if (neg_p)
riscv_expand_op (NEG, mode, dest, dest, NULL_RTX);
}
else
{
/* We use multiplication for remaining cases. */
gcc_assert (
TARGET_MUL
&& "M-extension must be enabled to calculate the poly_int "
"size/offset.");
riscv_emit_move (dest, gen_int_mode (multiplier, mode));
riscv_expand_op (MULT, mode, dest, dest, multiplicand);
}
}
}
/* Analyze src and emit const_poly_int mov sequence. */
static void
riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
{
poly_int64 value = rtx_to_poly_int64 (src);
int offset = value.coeffs[0];
int factor = value.coeffs[1];
int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1];
int div_factor = 0;
/* Calculate (const_poly_int:MODE [m, n]) using scalar instructions.
For any (const_poly_int:MODE [m, n]), the calculation formula is as
follows.
constant = m - n.
When minimum VLEN = 32, poly of VLENB = (4, 4).
base = vlenb(4, 4) or vlenb/2(2, 2) or vlenb/4(1, 1).
When minimum VLEN > 32, poly of VLENB = (8, 8).
base = vlenb(8, 8) or vlenb/2(4, 4) or vlenb/4(2, 2) or vlenb/8(1, 1).
magn = (n, n) / base.
(m, n) = base * magn + constant.
This calculation doesn't need div operation. */
emit_move_insn (tmp, gen_int_mode (BYTES_PER_RISCV_VECTOR, mode));
if (BYTES_PER_RISCV_VECTOR.is_constant ())
{
gcc_assert (value.is_constant ());
riscv_emit_move (dest, GEN_INT (value.to_constant ()));
return;
}
else if ((factor % vlenb) == 0)
div_factor = 1;
else if ((factor % (vlenb / 2)) == 0)
div_factor = 2;
else if ((factor % (vlenb / 4)) == 0)
div_factor = 4;
else if ((factor % (vlenb / 8)) == 0)
div_factor = 8;
else
gcc_unreachable ();
if (div_factor != 1)
riscv_expand_op (LSHIFTRT, mode, tmp, tmp,
gen_int_mode (exact_log2 (div_factor), QImode));
riscv_expand_mult_with_const_int (mode, dest, tmp,
factor / (vlenb / div_factor));
HOST_WIDE_INT constant = offset - factor;
if (constant == 0)
return;
else if (SMALL_OPERAND (constant))
riscv_expand_op (PLUS, mode, dest, dest, gen_int_mode (constant, mode));
else
{
/* Handle the constant value is not a 12-bit value. */
rtx high;
/* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
The addition inside the macro CONST_HIGH_PART may cause an
overflow, so we need to force a sign-extension check. */
high = gen_int_mode (CONST_HIGH_PART (constant), mode);
constant = CONST_LOW_PART (constant);
riscv_emit_move (tmp, high);
riscv_expand_op (PLUS, mode, dest, tmp, dest);
riscv_expand_op (PLUS, mode, dest, dest, gen_int_mode (constant, mode));
}
}
/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
sequence that is valid. */
bool
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
{
if (CONST_POLY_INT_P (src))
{
/*
Handle:
(insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
(const_int 96 [0x60])) [0 S1 A8])
(const_poly_int:QI [8, 8]))
"../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
*/
if (MEM_P (dest))
{
emit_move_insn (dest, force_reg (mode, src));
return true;
}
poly_int64 value = rtx_to_poly_int64 (src);
if (!value.is_constant () && !TARGET_VECTOR)
{
riscv_report_v_required ();
return false;
}
if (satisfies_constraint_vp (src))
return false;
if (GET_MODE_SIZE (mode).to_constant () < GET_MODE_SIZE (Pmode))
{
/* In RV32 system, handle (const_poly_int:QI [m, n])
(const_poly_int:HI [m, n]).
In RV64 system, handle (const_poly_int:QI [m, n])
(const_poly_int:HI [m, n])
(const_poly_int:SI [m, n]). */
rtx tmp = gen_reg_rtx (Pmode);
riscv_legitimize_poly_move (Pmode, gen_lowpart (Pmode, dest), tmp,
src);
}
else
{
/* In RV32 system, handle (const_poly_int:SI [m, n])
(const_poly_int:DI [m, n]).
In RV64 system, handle (const_poly_int:DI [m, n]).
FIXME: Maybe we could gen SImode in RV32 and then sign-extend to DImode,
the offset should not exceed 4GiB in general. */
rtx tmp = gen_reg_rtx (mode);
riscv_legitimize_poly_move (mode, dest, tmp, src);
}
return true;
}
/* Expand
(set (reg:QI target) (mem:QI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
with auto-sign/zero extend. */
if (GET_MODE_CLASS (mode) == MODE_INT
&& GET_MODE_SIZE (mode).to_constant () < UNITS_PER_WORD
&& can_create_pseudo_p ()
&& MEM_P (src))
{
rtx temp_reg;
int zero_extend_p;
temp_reg = gen_reg_rtx (word_mode);
zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
zero_extend_p));
riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
return true;
}
if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
{
rtx reg;
if (GET_CODE (src) == CONST_INT)
{
/* Apply the equivalent of PROMOTE_MODE here for constants to
improve cse. */
machine_mode promoted_mode = mode;
if (GET_MODE_CLASS (mode) == MODE_INT
&& GET_MODE_SIZE (mode).to_constant () < UNITS_PER_WORD)
promoted_mode = word_mode;
if (splittable_const_int_operand (src, mode))
{
reg = gen_reg_rtx (promoted_mode);
riscv_move_integer (reg, reg, INTVAL (src), mode, FALSE);
}
else
reg = force_reg (promoted_mode, src);
if (promoted_mode != mode)
reg = gen_lowpart (mode, reg);
}
else
reg = force_reg (mode, src);
riscv_emit_move (dest, reg);
return true;
}
/* We need to deal with constants that would be legitimate
immediate_operands but aren't legitimate move_operands. */
if (CONSTANT_P (src) && !move_operand (src, mode))
{
riscv_legitimize_const_move (mode, dest, src);
set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
return true;
}
/* RISC-V GCC may generate non-legitimate address due to we provide some
pattern for optimize access PIC local symbol and it's make GCC generate
unrecognizable instruction during optmizing. */
if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0),
reload_completed))
{
XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode);
}
if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0),
reload_completed))
{
XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode);
}
return false;
}
/* Return true if there is an instruction that implements CODE and accepts
X as an immediate operand. */
static int
riscv_immediate_operand_p (int code, HOST_WIDE_INT x)
{
switch (code)
{
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
/* All shift counts are truncated to a valid constant. */
return true;
case AND:
case IOR:
case XOR:
case PLUS:
case LT:
case LTU:
/* These instructions take 12-bit signed immediates. */
return SMALL_OPERAND (x);
case LE:
/* We add 1 to the immediate and use SLT. */
return SMALL_OPERAND (x + 1);
case LEU:
/* Likewise SLTU, but reject the always-true case. */
return SMALL_OPERAND (x + 1) && x + 1 != 0;
case GE:
case GEU:
/* We can emulate an immediate of 1 by using GT/GTU against x0. */
return x == 1;
default:
/* By default assume that x0 can be used for 0. */
return x == 0;
}
}
/* Return the cost of binary operation X, given that the instruction
sequence for a word-sized or smaller operation takes SIGNLE_INSNS
instructions and that the sequence of a double-word operation takes
DOUBLE_INSNS instructions. */
static int
riscv_binary_cost (rtx x, int single_insns, int double_insns)
{
if (!riscv_v_ext_vector_mode_p (GET_MODE (x))
&& GET_MODE_SIZE (GET_MODE (x)).to_constant () == UNITS_PER_WORD * 2)
return COSTS_N_INSNS (double_insns);
return COSTS_N_INSNS (single_insns);
}
/* Return the cost of sign- or zero-extending OP. */
static int
riscv_extend_cost (rtx op, bool unsigned_p)
{
if (MEM_P (op))
return 0;
if (unsigned_p && GET_MODE (op) == QImode)
/* We can use ANDI. */
return COSTS_N_INSNS (1);
/* ZBA provide zext.w. */
if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
return COSTS_N_INSNS (1);
/* ZBB provide zext.h, sext.b and sext.h. */
if (TARGET_ZBB)
{
if (!unsigned_p && GET_MODE (op) == QImode)
return COSTS_N_INSNS (1);
if (GET_MODE (op) == HImode)
return COSTS_N_INSNS (1);
}
if (!unsigned_p && GET_MODE (op) == SImode)
/* We can use SEXT.W. */
return COSTS_N_INSNS (1);
/* We need to use a shift left and a shift right. */
return COSTS_N_INSNS (2);
}
/* Implement TARGET_RTX_COSTS. */
#define SINGLE_SHIFT_COST 1
static bool
riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED,
int *total, bool speed)
{
/* TODO: We set RVV instruction cost as 1 by default.
Cost Model need to be well analyzed and supported in the future. */
if (riscv_v_ext_vector_mode_p (mode))
{
*total = COSTS_N_INSNS (1);
return true;
}
bool float_mode_p = FLOAT_MODE_P (mode);
int cost;
switch (GET_CODE (x))
{
case CONST_INT:
if (riscv_immediate_operand_p (outer_code, INTVAL (x)))
{
*total = 0;
return true;
}
/* Fall through. */
case SYMBOL_REF:
case LABEL_REF:
case CONST_DOUBLE:
/* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
rtl object. Weird recheck due to switch-case fall through above. */
if (GET_CODE (x) == CONST_DOUBLE)
gcc_assert (GET_MODE (x) != VOIDmode);
/* Fall through. */
case CONST:
if ((cost = riscv_const_insns (x)) > 0)
{
/* If the constant is likely to be stored in a GPR, SETs of
single-insn constants are as cheap as register sets; we
never want to CSE them. */
if (cost == 1 && outer_code == SET)
*total = 0;
/* When we load a constant more than once, it usually is better
to duplicate the last operation in the sequence than to CSE
the constant itself. */
else if (outer_code == SET || GET_MODE (x) == VOIDmode)
*total = COSTS_N_INSNS (1);
}
else /* The instruction will be fetched from the constant pool. */
*total = COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE));
return true;
case MEM:
/* If the address is legitimate, return the number of
instructions it needs. */
if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0)
{
/* When optimizing for size, make uncompressible 32-bit addresses
more expensive so that compressible 32-bit addresses are
preferred. */
if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
&& !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
*total = COSTS_N_INSNS (cost + tune_param->memory_cost);
return true;
}
/* Otherwise use the default handling. */
return false;
case IF_THEN_ELSE:
if (TARGET_SFB_ALU
&& register_operand (XEXP (x, 1), mode)
&& sfb_alu_operand (XEXP (x, 2), mode)
&& comparison_operator (XEXP (x, 0), VOIDmode))
{
/* For predicated conditional-move operations we assume the cost
of a single instruction even though there are actually two. */
*total = COSTS_N_INSNS (1);
return true;
}
else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
{
if (equality_operator (XEXP (x, 0), mode)
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTRACT)
{
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST + 1);
return true;
}
if (order_operator (XEXP (x, 0), mode))
{
*total = COSTS_N_INSNS (1);
return true;
}
}
return false;
case NOT:
*total = COSTS_N_INSNS (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD ? 2 : 1);
return false;
case AND:
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
{
rtx and_rhs = XEXP (x, 1);
rtx ashift_lhs = XEXP (XEXP (x, 0), 0);
rtx ashift_rhs = XEXP (XEXP (x, 0), 1);
if (REG_P (ashift_lhs)
&& CONST_INT_P (ashift_rhs)
&& CONST_INT_P (and_rhs)
&& ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
*total = COSTS_N_INSNS (1);
return true;
}
/* bclri pattern for zbs. */
if (TARGET_ZBS
&& not_single_bit_mask_operand (XEXP (x, 1), VOIDmode))
{
*total = COSTS_N_INSNS (1);
return true;
}
/* bclr pattern for zbs. */
if (TARGET_ZBS
&& REG_P (XEXP (x, 1))
&& GET_CODE (XEXP (x, 0)) == ROTATE
&& CONST_INT_P (XEXP ((XEXP (x, 0)), 0))
&& INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2)
{
*total = COSTS_N_INSNS (1);
return true;
}
gcc_fallthrough ();
case IOR:
case XOR:
/* orn, andn and xorn pattern for zbb. */
if (TARGET_ZBB
&& GET_CODE (XEXP (x, 0)) == NOT)
{
*total = riscv_binary_cost (x, 1, 2);
return true;
}
/* bset[i] and binv[i] pattern for zbs. */
if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR)
&& TARGET_ZBS
&& ((GET_CODE (XEXP (x, 0)) == ASHIFT
&& CONST_INT_P (XEXP (XEXP (x, 0), 0)))
|| single_bit_mask_operand (XEXP (x, 1), VOIDmode)))
{
*total = COSTS_N_INSNS (1);
return true;
}
/* Double-word operations use two single-word operations. */
*total = riscv_binary_cost (x, 1, 2);
return false;
case ZERO_EXTRACT:
/* This is an SImode shift. */
if (outer_code == SET
&& CONST_INT_P (XEXP (x, 1))
&& CONST_INT_P (XEXP (x, 2))
&& (INTVAL (XEXP (x, 2)) > 0)
&& (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32))
{
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
/* bext pattern for zbs. */
if (TARGET_ZBS && outer_code == SET
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& INTVAL (XEXP (x, 1)) == 1)
{
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
return false;
case ASHIFT:
/* bset pattern for zbs. */
if (TARGET_ZBS
&& CONST_INT_P (XEXP (x, 0))
&& INTVAL (XEXP (x, 0)) == 1)
{
*total = COSTS_N_INSNS (1);
return true;
}
gcc_fallthrough ();
case ASHIFTRT:
case LSHIFTRT:
*total = riscv_binary_cost (x, SINGLE_SHIFT_COST,
CONSTANT_P (XEXP (x, 1)) ? 4 : 9);
return false;
case ABS:
*total = COSTS_N_INSNS (float_mode_p ? 1 : 3);
return false;
case LO_SUM:
*total = set_src_cost (XEXP (x, 0), mode, speed);
return true;
case LT:
/* This is an SImode shift. */
if (outer_code == SET && GET_MODE (x) == DImode
&& GET_MODE (XEXP (x, 0)) == SImode)
{
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
/* Fall through. */
case LTU:
case LE:
case LEU:
case GT:
case GTU:
case GE:
case GEU:
case EQ:
case NE:
/* Branch comparisons have VOIDmode, so use the first operand's
mode instead. */
mode = GET_MODE (XEXP (x, 0));
if (float_mode_p)
*total = tune_param->fp_add[mode == DFmode];
else
*total = riscv_binary_cost (x, 1, 3);
return false;
case UNORDERED:
case ORDERED:
/* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
mode = GET_MODE (XEXP (x, 0));
*total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2);
return false;
case UNEQ:
/* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
mode = GET_MODE (XEXP (x, 0));
*total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (3);
return false;
case LTGT:
/* (FLT(A, A) || FGT(B, B)). */
mode = GET_MODE (XEXP (x, 0));
*total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (2);
return false;
case UNGE:
case UNGT:
case UNLE:
case UNLT:
/* FLT or FLE, but guarded by an FFLAGS read and write. */
mode = GET_MODE (XEXP (x, 0));
*total = tune_param->fp_add[mode == DFmode] + COSTS_N_INSNS (4);
return false;
case MINUS:
case PLUS:
/* add.uw pattern for zba. */
if (TARGET_ZBA
&& (TARGET_64BIT && (mode == DImode))
&& GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
&& REG_P (XEXP (XEXP (x, 0), 0))
&& GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
{
*total = COSTS_N_INSNS (1);
return true;
}
/* shNadd pattern for zba. */
if (TARGET_ZBA
&& ((!TARGET_64BIT && (mode == SImode)) ||
(TARGET_64BIT && (mode == DImode)))
&& (GET_CODE (XEXP (x, 0)) == ASHIFT)
&& REG_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)), 1, 3))
{
*total = COSTS_N_INSNS (1);
return true;
}
/* shNadd.uw pattern for zba.
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI
(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "I"))
(match_operand 3 "immediate_operand" ""))
(match_operand:DI 4 "register_operand" "r")))]
"TARGET_64BIT && TARGET_ZBA
&& (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
&& (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
*/
if (TARGET_ZBA
&& (TARGET_64BIT && (mode == DImode))
&& (GET_CODE (XEXP (x, 0)) == AND)
&& (REG_P (XEXP (x, 1))))
{
do {
rtx and_lhs = XEXP (XEXP (x, 0), 0);
rtx and_rhs = XEXP (XEXP (x, 0), 1);
if (GET_CODE (and_lhs) != ASHIFT)
break;
if (!CONST_INT_P (and_rhs))
break;
rtx ashift_rhs = XEXP (and_lhs, 1);
if (!CONST_INT_P (ashift_rhs)
|| !IN_RANGE (INTVAL (ashift_rhs), 1, 3))
break;
if (CONST_INT_P (and_rhs)
&& ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))
{
*total = COSTS_N_INSNS (1);
return true;
}
} while (false);
}
if (float_mode_p)
*total = tune_param->fp_add[mode == DFmode];
else
*total = riscv_binary_cost (x, 1, 4);
return false;
case NEG:
{
rtx op = XEXP (x, 0);
if (GET_CODE (op) == FMA && !HONOR_SIGNED_ZEROS (mode))
{
*total = (tune_param->fp_mul[mode == DFmode]
+ set_src_cost (XEXP (op, 0), mode, speed)
+ set_src_cost (XEXP (op, 1), mode, speed)
+ set_src_cost (XEXP (op, 2), mode, speed));
return true;
}
}
if (float_mode_p)
*total = tune_param->fp_add[mode == DFmode];
else
*total = COSTS_N_INSNS (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD ? 4 : 1);
return false;
case MULT:
if (float_mode_p)
*total = tune_param->fp_mul[mode == DFmode];
else if (!TARGET_MUL)
/* Estimate the cost of a library call. */
*total = COSTS_N_INSNS (speed ? 32 : 6);
else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
*total = 3 * tune_param->int_mul[0] + COSTS_N_INSNS (2);
else if (!speed)
*total = COSTS_N_INSNS (1);
else
*total = tune_param->int_mul[mode == DImode];
return false;
case DIV:
case SQRT:
case MOD:
if (float_mode_p)
{
*total = tune_param->fp_div[mode == DFmode];
return false;
}
/* Fall through. */
case UDIV:
case UMOD:
if (!TARGET_DIV)
/* Estimate the cost of a library call. */
*total = COSTS_N_INSNS (speed ? 32 : 6);
else if (speed)
*total = tune_param->int_div[mode == DImode];
else
*total = COSTS_N_INSNS (1);
return false;
case ZERO_EXTEND:
/* This is an SImode shift. */
if (GET_CODE (XEXP (x, 0)) == LSHIFTRT)
{
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
/* Fall through. */
case SIGN_EXTEND:
*total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
return false;
case FLOAT:
case UNSIGNED_FLOAT:
case FIX:
case FLOAT_EXTEND:
case FLOAT_TRUNCATE:
*total = tune_param->fp_add[mode == DFmode];
return false;
case FMA:
*total = (tune_param->fp_mul[mode == DFmode]
+ set_src_cost (XEXP (x, 0), mode, speed)
+ set_src_cost (XEXP (x, 1), mode, speed)
+ set_src_cost (XEXP (x, 2), mode, speed));
return true;
case UNSPEC:
if (XINT (x, 1) == UNSPEC_AUIPC)
{
/* Make AUIPC cheap to avoid spilling its result to the stack. */
*total = 1;
return true;
}
return false;
default:
return false;
}
}
/* Implement TARGET_ADDRESS_COST. */
static int
riscv_address_cost (rtx addr, machine_mode mode,
addr_space_t as ATTRIBUTE_UNUSED,
bool speed ATTRIBUTE_UNUSED)
{
/* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred. */
if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
&& !riscv_compressed_lw_address_p (addr))
return riscv_address_insns (addr, mode, false) + 1;
return riscv_address_insns (addr, mode, false);
}
/* Return one word of double-word value OP. HIGH_P is true to select the
high part or false to select the low part. */
rtx
riscv_subword (rtx op, bool high_p)
{
unsigned int byte = (high_p != BYTES_BIG_ENDIAN) ? UNITS_PER_WORD : 0;
machine_mode mode = GET_MODE (op);
if (mode == VOIDmode)
mode = TARGET_64BIT ? TImode : DImode;
if (MEM_P (op))
return adjust_address (op, word_mode, byte);
if (REG_P (op))
gcc_assert (!FP_REG_RTX_P (op));
return simplify_gen_subreg (word_mode, op, mode, byte);
}
/* Return true if a 64-bit move from SRC to DEST should be split into two. */
bool
riscv_split_64bit_move_p (rtx dest, rtx src)
{
if (TARGET_64BIT)
return false;
/* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
of zeroing an FPR with FCVT.D.W. */
if (TARGET_DOUBLE_FLOAT
&& ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
|| (FP_REG_RTX_P (dest) && MEM_P (src))
|| (FP_REG_RTX_P (src) && MEM_P (dest))
|| (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src)))))
return false;
return true;
}
/* Split a doubleword move from SRC to DEST. On 32-bit targets,
this function handles 64-bit moves for which riscv_split_64bit_move_p
holds. For 64-bit targets, this function handles 128-bit moves. */
void
riscv_split_doubleword_move (rtx dest, rtx src)
{
rtx low_dest;
/* The operation can be split into two normal moves. Decide in
which order to do them. */
low_dest = riscv_subword (dest, false);
if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
{
riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true));
riscv_emit_move (low_dest, riscv_subword (src, false));
}
else
{
riscv_emit_move (low_dest, riscv_subword (src, false));
riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true));
}
}
/* Return the appropriate instructions to move SRC into DEST. Assume
that SRC is operand 1 and DEST is operand 0. */
const char *
riscv_output_move (rtx dest, rtx src)
{
enum rtx_code dest_code, src_code;
machine_mode mode;
bool dbl_p;
unsigned width;
dest_code = GET_CODE (dest);
src_code = GET_CODE (src);
mode = GET_MODE (dest);
dbl_p = (GET_MODE_SIZE (mode).to_constant () == 8);
width = GET_MODE_SIZE (mode).to_constant ();
if (dbl_p && riscv_split_64bit_move_p (dest, src))
return "#";
if (dest_code == REG && GP_REG_P (REGNO (dest)))
{
if (src_code == REG && FP_REG_P (REGNO (src)))
switch (width)
{
case 2:
if (TARGET_ZFHMIN)
return "fmv.x.h\t%0,%1";
/* Using fmv.x.s + sign-extend to emulate fmv.x.h. */
return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16";
case 4:
return "fmv.x.s\t%0,%1";
case 8:
return "fmv.x.d\t%0,%1";
}
if (src_code == MEM)
switch (width)
{
case 1: return "lbu\t%0,%1";
case 2: return "lhu\t%0,%1";
case 4: return "lw\t%0,%1";
case 8: return "ld\t%0,%1";
}
if (src_code == CONST_INT)
{
if (SMALL_OPERAND (INTVAL (src)) || LUI_OPERAND (INTVAL (src)))
return "li\t%0,%1";
if (TARGET_ZBS
&& SINGLE_BIT_MASK_OPERAND (INTVAL (src)))
return "bseti\t%0,zero,%S1";
/* Should never reach here. */
abort ();
}
if (src_code == HIGH)
return "lui\t%0,%h1";
if (symbolic_operand (src, VOIDmode))
switch (riscv_classify_symbolic_expression (src))
{
case SYMBOL_GOT_DISP: return "la\t%0,%1";
case SYMBOL_ABSOLUTE: return "lla\t%0,%1";
case SYMBOL_PCREL: return "lla\t%0,%1";
default: gcc_unreachable ();
}
}
if ((src_code == REG && GP_REG_P (REGNO (src)))
|| (src == CONST0_RTX (mode)))
{
if (dest_code == REG)
{
if (GP_REG_P (REGNO (dest)))
return "mv\t%0,%z1";
if (FP_REG_P (REGNO (dest)))
switch (width)
{
case 2:
if (TARGET_ZFHMIN)
return "fmv.h.x\t%0,%z1";
/* High 16 bits should be all-1, otherwise HW will treated
as a n-bit canonical NaN, but isn't matter for softfloat. */
return "fmv.s.x\t%0,%1";
case 4:
return "fmv.s.x\t%0,%z1";
case 8:
if (TARGET_64BIT)
return "fmv.d.x\t%0,%z1";
/* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
gcc_assert (src == CONST0_RTX (mode));
return "fcvt.d.w\t%0,x0";
}
}
if (dest_code == MEM)
switch (width)
{
case 1: return "sb\t%z1,%0";
case 2: return "sh\t%z1,%0";
case 4: return "sw\t%z1,%0";
case 8: return "sd\t%z1,%0";
}
}
if (src_code == REG && FP_REG_P (REGNO (src)))
{
if (dest_code == REG && FP_REG_P (REGNO (dest)))
switch (width)
{
case 2:
if (TARGET_ZFH)
return "fmv.h\t%0,%1";
return "fmv.s\t%0,%1";
case 4:
return "fmv.s\t%0,%1";
case 8:
return "fmv.d\t%0,%1";
}
if (dest_code == MEM)
switch (width)
{
case 2:
return "fsh\t%1,%0";
case 4:
return "fsw\t%1,%0";
case 8:
return "fsd\t%1,%0";
}
}
if (dest_code == REG && FP_REG_P (REGNO (dest)))
{
if (src_code == MEM)
switch (width)
{
case 2:
return "flh\t%0,%1";
case 4:
return "flw\t%0,%1";
case 8:
return "fld\t%0,%1";
}
}
if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == CONST_POLY_INT)
{
/* We only want a single full vector register VLEN read after reload. */
gcc_assert (known_eq (rtx_to_poly_int64 (src), BYTES_PER_RISCV_VECTOR));
return "csrr\t%0,vlenb";
}
gcc_unreachable ();
}
const char *
riscv_output_return ()
{
if (cfun->machine->naked_p)
return "";
return "ret";
}
/* Return true if CMP1 is a suitable second operand for integer ordering
test CODE. See also the *sCC patterns in riscv.md. */
static bool
riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
{
switch (code)
{
case GT:
case GTU:
return reg_or_0_operand (cmp1, VOIDmode);
case GE:
case GEU:
return cmp1 == const1_rtx;
case LT:
case LTU:
return arith_operand (cmp1, VOIDmode);
case LE:
return sle_operand (cmp1, VOIDmode);
case LEU:
return sleu_operand (cmp1, VOIDmode);
default:
gcc_unreachable ();
}
}
/* Return true if *CMP1 (of mode MODE) is a valid second operand for
integer ordering test *CODE, or if an equivalent combination can
be formed by adjusting *CODE and *CMP1. When returning true, update
*CODE and *CMP1 with the chosen code and operand, otherwise leave
them alone. */
static bool
riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
machine_mode mode)
{
HOST_WIDE_INT plus_one;
if (riscv_int_order_operand_ok_p (*code, *cmp1))
return true;
if (CONST_INT_P (*cmp1))
switch (*code)
{
case LE:
plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
if (INTVAL (*cmp1) < plus_one)
{
*code = LT;
*cmp1 = force_reg (mode, GEN_INT (plus_one));
return true;
}
break;
case LEU:
plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
if (plus_one != 0)
{
*code = LTU;
*cmp1 = force_reg (mode, GEN_INT (plus_one));
return true;
}
break;
default:
break;
}
return false;
}
/* Compare CMP0 and CMP1 using ordering test CODE and store the result
in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
is nonnull, it's OK to set TARGET to the inverse of the result and
flip *INVERT_PTR instead. */
static void
riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
rtx target, rtx cmp0, rtx cmp1)
{
machine_mode mode;
/* First see if there is a RISCV instruction that can do this operation.
If not, try doing the same for the inverse operation. If that also
fails, force CMP1 into a register and try again. */
mode = GET_MODE (cmp0);
if (riscv_canonicalize_int_order_test (&code, &cmp1, mode))
riscv_emit_binary (code, target, cmp0, cmp1);
else
{
enum rtx_code inv_code = reverse_condition (code);
if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode))
{
cmp1 = force_reg (mode, cmp1);
riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
}
else if (invert_ptr == 0)
{
rtx inv_target = riscv_force_binary (GET_MODE (target),
inv_code, cmp0, cmp1);
riscv_emit_binary (XOR, target, inv_target, const1_rtx);
}
else
{
*invert_ptr = !*invert_ptr;
riscv_emit_binary (inv_code, target, cmp0, cmp1);
}
}
}
/* Return a register that is zero iff CMP0 and CMP1 are equal.
The register will have the same mode as CMP0. */
static rtx
riscv_zero_if_equal (rtx cmp0, rtx cmp1)
{
if (cmp1 == const0_rtx)
return cmp0;
return expand_binop (GET_MODE (cmp0), sub_optab,
cmp0, cmp1, 0, 0, OPTAB_DIRECT);
}
/* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
static void
riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
{
/* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0)).to_constant ())
{
/* It is more profitable to zero-extend QImode values. But not if the
first operand has already been sign-extended, and the second one is
is a constant or has already been sign-extended also. */
if (unsigned_condition (code) == code
&& (GET_MODE (*op0) == QImode
&& ! (GET_CODE (*op0) == SUBREG
&& SUBREG_PROMOTED_VAR_P (*op0)
&& SUBREG_PROMOTED_SIGNED_P (*op0)
&& (CONST_INT_P (*op1)
|| (GET_CODE (*op1) == SUBREG
&& SUBREG_PROMOTED_VAR_P (*op1)
&& SUBREG_PROMOTED_SIGNED_P (*op1))))))
{
*op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0);
if (CONST_INT_P (*op1))
*op1 = GEN_INT ((uint8_t) INTVAL (*op1));
else
*op1 = gen_rtx_ZERO_EXTEND (word_mode, *op1);
}
else
{
*op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0);
if (*op1 != const0_rtx)
*op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1);
}
}
}
/* Convert a comparison into something that can be used in a branch. On
entry, *OP0 and *OP1 are the values being compared and *CODE is the code
used to compare them. Update them to describe the final comparison. */
static void
riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1)
{
if (splittable_const_int_operand (*op1, VOIDmode))
{
HOST_WIDE_INT rhs = INTVAL (*op1);
if (*code == EQ || *code == NE)
{
/* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
if (SMALL_OPERAND (-rhs))
{
*op0 = riscv_force_binary (GET_MODE (*op0), PLUS, *op0,
GEN_INT (-rhs));
*op1 = const0_rtx;
}
}
else
{
static const enum rtx_code mag_comparisons[][2] = {
{LEU, LTU}, {GTU, GEU}, {LE, LT}, {GT, GE}
};
/* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
for (size_t i = 0; i < ARRAY_SIZE (mag_comparisons); i++)
{
HOST_WIDE_INT new_rhs;
bool increment = *code == mag_comparisons[i][0];
bool decrement = *code == mag_comparisons[i][1];
if (!increment && !decrement)
continue;
new_rhs = rhs + (increment ? 1 : -1);
new_rhs = trunc_int_for_mode (new_rhs, GET_MODE (*op0));
if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs)
&& (rhs < 0) == (new_rhs < 0))
{
*op1 = GEN_INT (new_rhs);
*code = mag_comparisons[i][increment];
}
break;
}
}
}
riscv_extend_comparands (*code, op0, op1);
*op0 = force_reg (word_mode, *op0);
if (*op1 != const0_rtx)
*op1 = force_reg (word_mode, *op1);
}
/* Like riscv_emit_int_compare, but for floating-point comparisons. */
static void
riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
{
rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1;
enum rtx_code fp_code = *code;
*code = NE;
switch (fp_code)
{
case UNORDERED:
*code = EQ;
/* Fall through. */
case ORDERED:
/* a == a && b == b */
tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0);
tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1);
*op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1);
*op1 = const0_rtx;
break;
case UNEQ:
/* ordered(a, b) > (a == b) */
*code = EQ;
tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0);
tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1);
*op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1);
*op1 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1);
break;
#define UNORDERED_COMPARISON(CODE, CMP) \
case CODE: \
*code = EQ; \
*op0 = gen_reg_rtx (word_mode); \
if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
else if (GET_MODE (cmp_op0) == SFmode) \
emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
else if (GET_MODE (cmp_op0) == DFmode) \
emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
else if (GET_MODE (cmp_op0) == HFmode && TARGET_64BIT) \
emit_insn (gen_f##CMP##_quiethfdi4 (*op0, cmp_op0, cmp_op1)); \
else if (GET_MODE (cmp_op0) == HFmode) \
emit_insn (gen_f##CMP##_quiethfsi4 (*op0, cmp_op0, cmp_op1)); \
else \
gcc_unreachable (); \
*op1 = const0_rtx; \
break;
case UNLT:
std::swap (cmp_op0, cmp_op1);
gcc_fallthrough ();
UNORDERED_COMPARISON(UNGT, le)
case UNLE:
std::swap (cmp_op0, cmp_op1);
gcc_fallthrough ();
UNORDERED_COMPARISON(UNGE, lt)
#undef UNORDERED_COMPARISON
case NE:
fp_code = EQ;
*code = EQ;
/* Fall through. */
case EQ:
case LE:
case LT:
case GE:
case GT:
/* We have instructions for these cases. */
*op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);
*op1 = const0_rtx;
break;
case LTGT:
/* (a < b) | (a > b) */
tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1);
tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1);
*op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1);
*op1 = const0_rtx;
break;
default:
gcc_unreachable ();
}
}
/* CODE-compare OP0 and OP1. Store the result in TARGET. */
void
riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
{
riscv_extend_comparands (code, &op0, &op1);
op0 = force_reg (word_mode, op0);
if (code == EQ || code == NE)
{
rtx zie = riscv_zero_if_equal (op0, op1);
riscv_emit_binary (code, target, zie, const0_rtx);
}
else
riscv_emit_int_order_test (code, 0, target, op0, op1);
}
/* Like riscv_expand_int_scc, but for floating-point comparisons. */
void
riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
{
riscv_emit_float_compare (&code, &op0, &op1);
rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode));
}
/* Jump to LABEL if (CODE OP0 OP1) holds. */
void
riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1)
{
if (FLOAT_MODE_P (GET_MODE (op1)))
riscv_emit_float_compare (&code, &op0, &op1);
else
riscv_emit_int_compare (&code, &op0, &op1);
rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
emit_jump_insn (gen_condjump (condition, label));
}
/* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
void
riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code,
rtx op0, rtx op1)
{
riscv_emit_int_compare (&code, &op0, &op1);
rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond,
cons, alt)));
}
/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
least PARM_BOUNDARY bits of alignment, but will be given anything up
to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
static unsigned int
riscv_function_arg_boundary (machine_mode mode, const_tree type)
{
unsigned int alignment;
/* Use natural alignment if the type is not aggregate data. */
if (type && !AGGREGATE_TYPE_P (type))
alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type));
else
alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment));
}
/* If MODE represents an argument that can be passed or returned in
floating-point registers, return the number of registers, else 0. */
static unsigned
riscv_pass_mode_in_fpr_p (machine_mode mode)
{
if (GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FP_ARG)
{
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
return 1;
if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
return 2;
}
return 0;
}
typedef struct {
const_tree type;
HOST_WIDE_INT offset;
} riscv_aggregate_field;
/* Identify subfields of aggregates that are candidates for passing in
floating-point registers. */
static int
riscv_flatten_aggregate_field (const_tree type,
riscv_aggregate_field fields[2],
int n, HOST_WIDE_INT offset,
bool ignore_zero_width_bit_field_p)
{
switch (TREE_CODE (type))
{
case RECORD_TYPE:
/* Can't handle incomplete types nor sizes that are not fixed. */
if (!COMPLETE_TYPE_P (type)
|| TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
|| !tree_fits_uhwi_p (TYPE_SIZE (type)))
return -1;
for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
if (TREE_CODE (f) == FIELD_DECL)
{
if (!TYPE_P (TREE_TYPE (f)))
return -1;
/* The C++ front end strips zero-length bit-fields from structs.
So we need to ignore them in the C front end to make C code
compatible with C++ code. */
if (ignore_zero_width_bit_field_p
&& DECL_BIT_FIELD (f)
&& (DECL_SIZE (f) == NULL_TREE
|| integer_zerop (DECL_SIZE (f))))
;
else
{
HOST_WIDE_INT pos = offset + int_byte_position (f);
n = riscv_flatten_aggregate_field (TREE_TYPE (f),
fields, n, pos,
ignore_zero_width_bit_field_p);
}
if (n < 0)
return -1;
}
return n;
case ARRAY_TYPE:
{
HOST_WIDE_INT n_elts;
riscv_aggregate_field subfields[2];
tree index = TYPE_DOMAIN (type);
tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type));
int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type),
subfields, 0, offset,
ignore_zero_width_bit_field_p);
/* Can't handle incomplete types nor sizes that are not fixed. */
if (n_subfields <= 0
|| !COMPLETE_TYPE_P (type)
|| TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST
|| !index
|| !TYPE_MAX_VALUE (index)
|| !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
|| !TYPE_MIN_VALUE (index)
|| !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
|| !tree_fits_uhwi_p (elt_size))
return -1;
n_elts = 1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
- tree_to_uhwi (TYPE_MIN_VALUE (index));
gcc_assert (n_elts >= 0);
for (HOST_WIDE_INT i = 0; i < n_elts; i++)
for (int j = 0; j < n_subfields; j++)
{
if (n >= 2)
return -1;
fields[n] = subfields[j];
fields[n++].offset += i * tree_to_uhwi (elt_size);
}
return n;
}
case COMPLEX_TYPE:
{
/* Complex type need consume 2 field, so n must be 0. */
if (n != 0)
return -1;
HOST_WIDE_INT elt_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type))).to_constant ();
if (elt_size <= UNITS_PER_FP_ARG)
{
fields[0].type = TREE_TYPE (type);
fields[0].offset = offset;
fields[1].type = TREE_TYPE (type);
fields[1].offset = offset + elt_size;
return 2;
}
return -1;
}
default:
if (n < 2
&& ((SCALAR_FLOAT_TYPE_P (type)
&& GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_FP_ARG)
|| (INTEGRAL_TYPE_P (type)
&& GET_MODE_SIZE (TYPE_MODE (type)).to_constant () <= UNITS_PER_WORD)))
{
fields[n].type = type;
fields[n].offset = offset;
return n + 1;
}
else
return -1;
}
}
/* Identify candidate aggregates for passing in floating-point registers.
Candidates have at most two fields after flattening. */
static int
riscv_flatten_aggregate_argument (const_tree type,
riscv_aggregate_field fields[2],
bool ignore_zero_width_bit_field_p)
{
if (!type || TREE_CODE (type) != RECORD_TYPE)
return -1;
return riscv_flatten_aggregate_field (type, fields, 0, 0,
ignore_zero_width_bit_field_p);
}
/* See whether TYPE is a record whose fields should be returned in one or
two floating-point registers. If so, populate FIELDS accordingly. */
static unsigned
riscv_pass_aggregate_in_fpr_pair_p (const_tree type,
riscv_aggregate_field fields[2])
{
static int warned = 0;
/* This is the old ABI, which differs for C++ and C. */
int n_old = riscv_flatten_aggregate_argument (type, fields, false);
for (int i = 0; i < n_old; i++)
if (!SCALAR_FLOAT_TYPE_P (fields[i].type))
{
n_old = -1;
break;
}
/* This is the new ABI, which is the same for C++ and C. */
int n_new = riscv_flatten_aggregate_argument (type, fields, true);
for (int i = 0; i < n_new; i++)
if (!SCALAR_FLOAT_TYPE_P (fields[i].type))
{
n_new = -1;
break;
}
if ((n_old != n_new) && (warned == 0))
{
warning (OPT_Wpsabi, "ABI for flattened struct with zero-length "
"bit-fields changed in GCC 10");
warned = 1;
}
return n_new > 0 ? n_new : 0;
}
/* See whether TYPE is a record whose fields should be returned in one or
floating-point register and one integer register. If so, populate
FIELDS accordingly. */
static bool
riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type,
riscv_aggregate_field fields[2])
{
static int warned = 0;
/* This is the old ABI, which differs for C++ and C. */
unsigned num_int_old = 0, num_float_old = 0;
int n_old = riscv_flatten_aggregate_argument (type, fields, false);
for (int i = 0; i < n_old; i++)
{
num_float_old += SCALAR_FLOAT_TYPE_P (fields[i].type);
num_int_old += INTEGRAL_TYPE_P (fields[i].type);
}
/* This is the new ABI, which is the same for C++ and C. */
unsigned num_int_new = 0, num_float_new = 0;
int n_new = riscv_flatten_aggregate_argument (type, fields, true);
for (int i = 0; i < n_new; i++)
{
num_float_new += SCALAR_FLOAT_TYPE_P (fields[i].type);
num_int_new += INTEGRAL_TYPE_P (fields[i].type);
}
if (((num_int_old == 1 && num_float_old == 1
&& (num_int_old != num_int_new || num_float_old != num_float_new))
|| (num_int_new == 1 && num_float_new == 1
&& (num_int_old != num_int_new || num_float_old != num_float_new)))
&& (warned == 0))
{
warning (OPT_Wpsabi, "ABI for flattened struct with zero-length "
"bit-fields changed in GCC 10");
warned = 1;
}
return num_int_new == 1 && num_float_new == 1;
}
/* Return the representation of an argument passed or returned in an FPR
when the value has mode VALUE_MODE and the type has TYPE_MODE. The
two modes may be different for structures like:
struct __attribute__((packed)) foo { float f; }
where the SFmode value "f" is passed in REGNO but the struct itself
has mode BLKmode. */
static rtx
riscv_pass_fpr_single (machine_mode type_mode, unsigned regno,
machine_mode value_mode,
HOST_WIDE_INT offset)
{
rtx x = gen_rtx_REG (value_mode, regno);
if (type_mode != value_mode)
{
x = gen_rtx_EXPR_LIST (VOIDmode, x, GEN_INT (offset));
x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
}
return x;
}
/* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
byte offset for the first value, likewise MODE2 and OFFSET2 for the
second value. */
static rtx
riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
machine_mode mode1, HOST_WIDE_INT offset1,
unsigned regno2, machine_mode mode2,
HOST_WIDE_INT offset2)
{
return gen_rtx_PARALLEL
(mode,
gen_rtvec (2,
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode1, regno1),
GEN_INT (offset1)),
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode2, regno2),
GEN_INT (offset2))));
}
/* Fill INFO with information about a single argument, and return an
RTL pattern to pass or return the argument. CUM is the cumulative
state for earlier arguments. MODE is the mode of this argument and
TYPE is its type (if known). NAMED is true if this is a named
(fixed) argument rather than a variable one. RETURN_P is true if
returning the argument, or false if passing the argument. */
static rtx
riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
machine_mode mode, const_tree type, bool named,
bool return_p)
{
unsigned num_bytes, num_words;
unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST;
unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST;
unsigned alignment = riscv_function_arg_boundary (mode, type);
memset (info, 0, sizeof (*info));
info->gpr_offset = cum->num_gprs;
info->fpr_offset = cum->num_fprs;
if (named)
{
riscv_aggregate_field fields[2];
unsigned fregno = fpr_base + info->fpr_offset;
unsigned gregno = gpr_base + info->gpr_offset;
/* Pass one- or two-element floating-point aggregates in FPRs. */
if ((info->num_fprs = riscv_pass_aggregate_in_fpr_pair_p (type, fields))
&& info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS)
switch (info->num_fprs)
{
case 1:
return riscv_pass_fpr_single (mode, fregno,
TYPE_MODE (fields[0].type),
fields[0].offset);
case 2:
return riscv_pass_fpr_pair (mode, fregno,
TYPE_MODE (fields[0].type),
fields[0].offset,
fregno + 1,
TYPE_MODE (fields[1].type),
fields[1].offset);
default:
gcc_unreachable ();
}
/* Pass real and complex floating-point numbers in FPRs. */
if ((info->num_fprs = riscv_pass_mode_in_fpr_p (mode))
&& info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS)
switch (GET_MODE_CLASS (mode))
{
case MODE_FLOAT:
return gen_rtx_REG (mode, fregno);
case MODE_COMPLEX_FLOAT:
return riscv_pass_fpr_pair (mode, fregno, GET_MODE_INNER (mode), 0,
fregno + 1, GET_MODE_INNER (mode),
GET_MODE_UNIT_SIZE (mode));
default:
gcc_unreachable ();
}
/* Pass structs with one float and one integer in an FPR and a GPR. */
if (riscv_pass_aggregate_in_fpr_and_gpr_p (type, fields)
&& info->gpr_offset < MAX_ARGS_IN_REGISTERS
&& info->fpr_offset < MAX_ARGS_IN_REGISTERS)
{
info->num_gprs = 1;
info->num_fprs = 1;
if (!SCALAR_FLOAT_TYPE_P (fields[0].type))
std::swap (fregno, gregno);
return riscv_pass_fpr_pair (mode, fregno, TYPE_MODE (fields[0].type),
fields[0].offset,
gregno, TYPE_MODE (fields[1].type),
fields[1].offset);
}
}
/* Work out the size of the argument. */
num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
/* Doubleword-aligned varargs start on an even register boundary. */
if (!named && num_bytes != 0 && alignment > BITS_PER_WORD)
info->gpr_offset += info->gpr_offset & 1;
/* Partition the argument between registers and stack. */
info->num_fprs = 0;
info->num_gprs = MIN (num_words, MAX_ARGS_IN_REGISTERS - info->gpr_offset);
info->stack_p = (num_words - info->num_gprs) != 0;
if (info->num_gprs || return_p)
return gen_rtx_REG (mode, gpr_base + info->gpr_offset);
return NULL_RTX;
}
/* Implement TARGET_FUNCTION_ARG. */
static rtx
riscv_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
struct riscv_arg_info info;
if (arg.end_marker_p ())
return NULL;
return riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
}
/* Implement TARGET_FUNCTION_ARG_ADVANCE. */
static void
riscv_function_arg_advance (cumulative_args_t cum_v,
const function_arg_info &arg)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
struct riscv_arg_info info;
riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
/* Advance the register count. This has the effect of setting
num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
argument required us to skip the final GPR and pass the whole
argument on the stack. */
cum->num_fprs = info.fpr_offset + info.num_fprs;
cum->num_gprs = info.gpr_offset + info.num_gprs;
}
/* Implement TARGET_ARG_PARTIAL_BYTES. */
static int
riscv_arg_partial_bytes (cumulative_args_t cum,
const function_arg_info &generic_arg)
{
struct riscv_arg_info arg;
riscv_get_arg_info (&arg, get_cumulative_args (cum), generic_arg.mode,
generic_arg.type, generic_arg.named, false);
return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : 0;
}
/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
VALTYPE is the return type and MODE is VOIDmode. For libcalls,
VALTYPE is null and MODE is the mode of the return value. */
rtx
riscv_function_value (const_tree type, const_tree func, machine_mode mode)
{
struct riscv_arg_info info;
CUMULATIVE_ARGS args;
if (type)
{
int unsigned_p = TYPE_UNSIGNED (type);
mode = TYPE_MODE (type);
/* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
return values, promote the mode here too. */
mode = promote_function_mode (type, mode, &unsigned_p, func, 1);
}
memset (&args, 0, sizeof args);
return riscv_get_arg_info (&info, &args, mode, type, true, true);
}
/* Implement TARGET_PASS_BY_REFERENCE. */
static bool
riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)
{
HOST_WIDE_INT size = arg.type_size_in_bytes ().to_constant ();;
struct riscv_arg_info info;
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
/* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
never pass variadic arguments in floating-point registers, so we can
avoid the call to riscv_get_arg_info in this case. */
if (cum != NULL)
{
/* Don't pass by reference if we can use a floating-point register. */
riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false);
if (info.num_fprs)
return false;
}
/* Pass by reference if the data do not fit in two integer registers. */
return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD);
}
/* Implement TARGET_RETURN_IN_MEMORY. */
static bool
riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
{
CUMULATIVE_ARGS args;
cumulative_args_t cum = pack_cumulative_args (&args);
/* The rules for returning in memory are the same as for passing the
first named argument by reference. */
memset (&args, 0, sizeof args);
function_arg_info arg (const_cast<tree> (type), /*named=*/true);
return riscv_pass_by_reference (cum, arg);
}
/* Implement TARGET_SETUP_INCOMING_VARARGS. */
static void
riscv_setup_incoming_varargs (cumulative_args_t cum,
const function_arg_info &arg,
int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
{
CUMULATIVE_ARGS local_cum;
int gp_saved;
/* The caller has advanced CUM up to, but not beyond, the last named
argument. Advance a local copy of CUM past the last "real" named
argument, to find out how many registers are left over. */
local_cum = *get_cumulative_args (cum);
riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg);
/* Found out how many registers we need to save. */
gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
if (!no_rtl && gp_saved > 0)
{
rtx ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
REG_PARM_STACK_SPACE (cfun->decl)
- gp_saved * UNITS_PER_WORD);
rtx mem = gen_frame_mem (BLKmode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
mem, gp_saved);
}
if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD;
}
/* Handle an attribute requiring a FUNCTION_DECL;
arguments as in struct attribute_spec.handler. */
static tree
riscv_handle_fndecl_attribute (tree *node, tree name,
tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
warning (OPT_Wattributes, "%qE attribute only applies to functions",
name);
*no_add_attrs = true;
}
return NULL_TREE;
}
/* Verify type based attributes. NODE is the what the attribute is being
applied to. NAME is the attribute name. ARGS are the attribute args.
FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
the attribute should be ignored. */
static tree
riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
{
/* Check for an argument. */
if (is_attribute_p ("interrupt", name))
{
if (args)
{
tree cst = TREE_VALUE (args);
const char *string;
if (TREE_CODE (cst) != STRING_CST)
{
warning (OPT_Wattributes,
"%qE attribute requires a string argument",
name);
*no_add_attrs = true;
return NULL_TREE;
}
string = TREE_STRING_POINTER (cst);
if (strcmp (string, "user") && strcmp (string, "supervisor")
&& strcmp (string, "machine"))
{
warning (OPT_Wattributes,
"argument to %qE attribute is not %<\"user\"%>, %<\"supervisor\"%>, "
"or %<\"machine\"%>", name);
*no_add_attrs = true;
}
}
}
return NULL_TREE;
}
/* Return true if function TYPE is an interrupt function. */
static bool
riscv_interrupt_type_p (tree type)
{
return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
}
/* Return true if FUNC is a naked function. */
static bool
riscv_naked_function_p (tree func)
{
tree func_decl = func;
if (func == NULL_TREE)
func_decl = current_function_decl;
return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl));
}
/* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
static bool
riscv_allocate_stack_slots_for_args ()
{
/* Naked functions should not allocate stack slots for arguments. */
return !riscv_naked_function_p (current_function_decl);
}
/* Implement TARGET_WARN_FUNC_RETURN. */
static bool
riscv_warn_func_return (tree decl)
{
/* Naked functions are implemented entirely in assembly, including the
return sequence, so suppress warnings about this. */
return !riscv_naked_function_p (decl);
}
/* Implement TARGET_EXPAND_BUILTIN_VA_START. */
static void
riscv_va_start (tree valist, rtx nextarg)
{
nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
std_expand_builtin_va_start (valist, nextarg);
}
/* Make ADDR suitable for use as a call or sibcall target. */
rtx
riscv_legitimize_call_address (rtx addr)
{
if (!call_insn_operand (addr, VOIDmode))
{
rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode);
riscv_emit_move (reg, addr);
return reg;
}
return addr;
}
/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
Assume that the areas do not overlap. */
static void
riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length)
{
unsigned HOST_WIDE_INT offset, delta;
unsigned HOST_WIDE_INT bits;
int i;
enum machine_mode mode;
rtx *regs;
bits = MAX (BITS_PER_UNIT,
MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest))));
mode = mode_for_size (bits, MODE_INT, 0).require ();
delta = bits / BITS_PER_UNIT;
/* Allocate a buffer for the temporary registers. */
regs = XALLOCAVEC (rtx, length / delta);
/* Load as many BITS-sized chunks as possible. Use a normal load if
the source has enough alignment, otherwise use left/right pairs. */
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
{
regs[i] = gen_reg_rtx (mode);
riscv_emit_move (regs[i], adjust_address (src, mode, offset));
}
/* Copy the chunks to the destination. */
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
riscv_emit_move (adjust_address (dest, mode, offset), regs[i]);
/* Mop up any left-over bytes. */
if (offset < length)
{
src = adjust_address (src, BLKmode, offset);
dest = adjust_address (dest, BLKmode, offset);
move_by_pieces (dest, src, length - offset,
MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN);
}
}
/* Helper function for doing a loop-based block operation on memory
reference MEM. Each iteration of the loop will operate on LENGTH
bytes of MEM.
Create a new base register for use within the loop and point it to
the start of MEM. Create a new memory reference that uses this
register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
static void
riscv_adjust_block_mem (rtx mem, unsigned HOST_WIDE_INT length,
rtx *loop_reg, rtx *loop_mem)
{
*loop_reg = copy_addr_to_reg (XEXP (mem, 0));
/* Although the new mem does not refer to a known location,
it does keep up to LENGTH bytes of alignment. */
*loop_mem = change_address (mem, BLKmode, *loop_reg);
set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
}
/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
the memory regions do not overlap. */
static void
riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
unsigned HOST_WIDE_INT bytes_per_iter)
{
rtx label, src_reg, dest_reg, final_src, test;
unsigned HOST_WIDE_INT leftover;
leftover = length % bytes_per_iter;
length -= leftover;
/* Create registers and memory references for use within the loop. */
riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
/* Calculate the value that SRC_REG should have after the last iteration
of the loop. */
final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
0, 0, OPTAB_WIDEN);
/* Emit the start of the loop. */
label = gen_label_rtx ();
emit_label (label);
/* Emit the loop body. */
riscv_block_move_straight (dest, src, bytes_per_iter);
/* Move on to the next block. */
riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
/* Emit the loop condition. */
test = gen_rtx_NE (VOIDmode, src_reg, final_src);
emit_jump_insn (gen_cbranch4 (Pmode, test, src_reg, final_src, label));
/* Mop up any left-over bytes. */
if (leftover)
riscv_block_move_straight (dest, src, leftover);
else
emit_insn(gen_nop ());
}
/* Expand a cpymemsi instruction, which copies LENGTH bytes from
memory reference SRC to memory reference DEST. */
bool
riscv_expand_block_move (rtx dest, rtx src, rtx length)
{
if (CONST_INT_P (length))
{
unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
unsigned HOST_WIDE_INT factor, align;
align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
factor = BITS_PER_WORD / align;
if (optimize_function_for_size_p (cfun)
&& hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO (false))
return false;
if (hwi_length <= (RISCV_MAX_MOVE_BYTES_STRAIGHT / factor))
{
riscv_block_move_straight (dest, src, INTVAL (length));
return true;
}
else if (optimize && align >= BITS_PER_WORD)
{
unsigned min_iter_words
= RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD;
unsigned iter_words = min_iter_words;
unsigned HOST_WIDE_INT bytes = hwi_length;
unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD;
/* Lengthen the loop body if it shortens the tail. */
for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++)
{
unsigned cur_cost = iter_words + words % iter_words;
unsigned new_cost = i + words % i;
if (new_cost <= cur_cost)
iter_words = i;
}
riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD);
return true;
}
}
return false;
}
/* Print symbolic operand OP, which is part of a HIGH or LO_SUM
in context CONTEXT. HI_RELOC indicates a high-part reloc. */
static void
riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
{
const char *reloc;
switch (riscv_classify_symbolic_expression (op))
{
case SYMBOL_ABSOLUTE:
reloc = hi_reloc ? "%hi" : "%lo";
break;
case SYMBOL_PCREL:
reloc = hi_reloc ? "%pcrel_hi" : "%pcrel_lo";
break;
case SYMBOL_TLS_LE:
reloc = hi_reloc ? "%tprel_hi" : "%tprel_lo";
break;
default:
output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R');
return;
}
fprintf (file, "%s(", reloc);
output_addr_const (file, riscv_strip_unspec_address (op));
fputc (')', file);
}
/* Return true if the .AQ suffix should be added to an AMO to implement the
acquire portion of memory model MODEL. */
static bool
riscv_memmodel_needs_amo_acquire (enum memmodel model)
{
switch (model)
{
case MEMMODEL_ACQ_REL:
case MEMMODEL_SEQ_CST:
case MEMMODEL_SYNC_SEQ_CST:
case MEMMODEL_ACQUIRE:
case MEMMODEL_CONSUME:
case MEMMODEL_SYNC_ACQUIRE:
return true;
case MEMMODEL_RELEASE:
case MEMMODEL_SYNC_RELEASE:
case MEMMODEL_RELAXED:
return false;
default:
gcc_unreachable ();
}
}
/* Return true if a FENCE should be emitted to before a memory access to
implement the release portion of memory model MODEL. */
static bool
riscv_memmodel_needs_release_fence (enum memmodel model)
{
switch (model)
{
case MEMMODEL_ACQ_REL:
case MEMMODEL_SEQ_CST:
case MEMMODEL_SYNC_SEQ_CST:
case MEMMODEL_RELEASE:
case MEMMODEL_SYNC_RELEASE:
return true;
case MEMMODEL_ACQUIRE:
case MEMMODEL_CONSUME:
case MEMMODEL_SYNC_ACQUIRE:
case MEMMODEL_RELAXED:
return false;
default:
gcc_unreachable ();
}
}
/* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
'h' Print the high-part relocation associated with OP, after stripping
any outermost HIGH.
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
'T' Print shift-index of inverted single-bit mask OP.
'~' Print w if TARGET_64BIT is true; otherwise not print anything.
Note please keep this list and the list in riscv.md in sync. */
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
/* `~` does not take an operand so op will be null
Check for before accessing op.
*/
if (letter == '~')
{
if (TARGET_64BIT)
fputc('w', file);
return;
}
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
switch (letter)
{
case 'm': {
if (riscv_v_ext_vector_mode_p (mode))
{
/* Calculate lmul according to mode and print the value. */
poly_int64 size = GET_MODE_SIZE (mode);
unsigned int lmul;
if (known_lt (size, BYTES_PER_RISCV_VECTOR))
lmul = 1;
else
lmul = exact_div (size, BYTES_PER_RISCV_VECTOR).to_constant ();
asm_fprintf (file, "%d", lmul);
}
else if (code == CONST_INT)
{
/* The value in the operand is the unsigned int value
converted from (enum machine_mode).
This RTX is generated as follows:
machine_mode mode = XXXmode;
operand = gen_int_mode ((unsigned int)mode, Pmode);
So we convert it back into machine_mode and then calculate
the LMUL according to GET_MODE_SIZE. */
machine_mode rvv_mode = (machine_mode) UINTVAL (op);
/* For rvv mask modes, we can not calculate LMUL simpily according
to BYTES_PER_RISCV_VECTOR. When rvv_mode = VNx4BImode.
Set SEW = 8, LMUL = 1 by default if TARGET_MIN_VLEN == 32.
Set SEW = 8, LMUL = 1 / 2 by default if TARGET_MIN_VLEN > 32. */
bool bool_p = GET_MODE_CLASS (rvv_mode) == MODE_VECTOR_BOOL;
poly_int64 m1_size = BYTES_PER_RISCV_VECTOR;
poly_int64 rvv_size
= bool_p ? GET_MODE_NUNITS (rvv_mode) : GET_MODE_SIZE (rvv_mode);
bool fractional_p = known_lt (rvv_size, BYTES_PER_RISCV_VECTOR);
unsigned int factor
= fractional_p ? exact_div (m1_size, rvv_size).to_constant ()
: exact_div (rvv_size, m1_size).to_constant ();
asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor);
}
else
output_operand_lossage ("invalid vector constant");
break;
}
case 'p': {
if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
{
/* Print for RVV mask operand.
If op is reg, print ",v0.t".
Otherwise, don't print anything. */
if (code == REG)
fprintf (file, ",%s.t", reg_names[REGNO (op)]);
}
else if (code == CONST_INT)
{
/* Tail && Mask policy. */
bool agnostic_p = UINTVAL (op) & 0x1;
asm_fprintf (file, "%s", agnostic_p ? "a" : "u");
}
else
output_operand_lossage ("invalid vector constant");
break;
}
case 'h':
if (code == HIGH)
op = XEXP (op, 0);
riscv_print_operand_reloc (file, op, true);
break;
case 'R':
riscv_print_operand_reloc (file, op, false);
break;
case 'C':
/* The RTL names match the instruction names. */
fputs (GET_RTX_NAME (code), file);
break;
case 'A':
if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
fputs (".aq", file);
break;
case 'F':
if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
fputs ("fence iorw,ow; ", file);
break;
case 'i':
if (code != REG)
fputs ("i", file);
break;
case 'S':
{
rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
output_addr_const (file, newop);
break;
}
case 'T':
{
rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
output_addr_const (file, newop);
break;
}
default:
switch (code)
{
case REG:
if (letter && letter != 'z')
output_operand_lossage ("invalid use of '%%%c'", letter);
fprintf (file, "%s", reg_names[REGNO (op)]);
break;
case MEM:
if (letter && letter != 'z')
output_operand_lossage ("invalid use of '%%%c'", letter);
else
output_address (mode, XEXP (op, 0));
break;
default:
if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
fputs (reg_names[GP_REG_FIRST], file);
else if (letter && letter != 'z')
output_operand_lossage ("invalid use of '%%%c'", letter);
else
output_addr_const (file, riscv_strip_unspec_address (op));
break;
}
}
}
/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */
static bool
riscv_print_operand_punct_valid_p (unsigned char code)
{
return (code == '~');
}
/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
static void
riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
struct riscv_address_info addr;
if (riscv_classify_address (&addr, x, word_mode, true))
switch (addr.type)
{
case ADDRESS_REG:
riscv_print_operand (file, addr.offset, 0);
fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
return;
case ADDRESS_LO_SUM:
riscv_print_operand_reloc (file, addr.offset, false);
fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
return;
case ADDRESS_CONST_INT:
output_addr_const (file, x);
fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
return;
case ADDRESS_SYMBOLIC:
output_addr_const (file, riscv_strip_unspec_address (x));
return;
}
gcc_unreachable ();
}
static bool
riscv_size_ok_for_small_data_p (int size)
{
return g_switch_value && IN_RANGE (size, 1, g_switch_value);
}
/* Return true if EXP should be placed in the small data section. */
static bool
riscv_in_small_data_p (const_tree x)
{
if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL)
return false;
if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x))
{
const char *sec = DECL_SECTION_NAME (x);
return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0;
}
return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x)));
}
/* Switch to the appropriate section for output of DECL. */
static section *
riscv_select_section (tree decl, int reloc,
unsigned HOST_WIDE_INT align)
{
switch (categorize_decl_for_section (decl, reloc))
{
case SECCAT_SRODATA:
return get_named_section (decl, ".srodata", reloc);
default:
return default_elf_select_section (decl, reloc, align);
}
}
/* Switch to the appropriate section for output of DECL. */
static void
riscv_unique_section (tree decl, int reloc)
{
const char *prefix = NULL;
bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
switch (categorize_decl_for_section (decl, reloc))
{
case SECCAT_SRODATA:
prefix = one_only ? ".sr" : ".srodata";
break;
default:
break;
}
if (prefix)
{
const char *name, *linkonce;
char *string;
name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
name = targetm.strip_name_encoding (name);
/* If we're using one_only, then there needs to be a .gnu.linkonce
prefix to the section name. */
linkonce = one_only ? ".gnu.linkonce" : "";
string = ACONCAT ((linkonce, prefix, ".", name, NULL));
set_decl_section_name (decl, string);
return;
}
default_unique_section (decl, reloc);
}
/* Return a section for X, handling small data. */
static section *
riscv_elf_select_rtx_section (machine_mode mode, rtx x,
unsigned HOST_WIDE_INT align)
{
section *s = default_elf_select_rtx_section (mode, x, align);
if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode).to_constant ()))
{
if (startswith (s->named.name, ".rodata.cst"))
{
/* Rename .rodata.cst* to .srodata.cst*. */
char *name = (char *) alloca (strlen (s->named.name) + 2);
sprintf (name, ".s%s", s->named.name + 1);
return get_section (name, s->named.common.flags, NULL);
}
if (s == data_section)
return sdata_section;
}
return s;
}
/* Make the last instruction frame-related and note that it performs
the operation described by FRAME_PATTERN. */
static void
riscv_set_frame_expr (rtx frame_pattern)
{
rtx insn;
insn = get_last_insn ();
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
frame_pattern,
REG_NOTES (insn));
}
/* Return a frame-related rtx that stores REG at MEM.
REG must be a single register. */
static rtx
riscv_frame_set (rtx mem, rtx reg)
{
rtx set = gen_rtx_SET (mem, reg);
RTX_FRAME_RELATED_P (set) = 1;
return set;
}
/* Return true if the current function must save register REGNO. */
static bool
riscv_save_reg_p (unsigned int regno)
{
bool call_saved = !global_regs[regno] && !call_used_or_fixed_reg_p (regno);
bool might_clobber = crtl->saves_all_registers
|| df_regs_ever_live_p (regno);
if (call_saved && might_clobber)
return true;
if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
return true;
if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
return true;
/* If this is an interrupt handler, then must save extra registers. */
if (cfun->machine->interrupt_handler_p)
{
/* zero register is always zero. */
if (regno == GP_REG_FIRST)
return false;
/* The function will return the stack pointer to its original value. */
if (regno == STACK_POINTER_REGNUM)
return false;
/* By convention, we assume that gp and tp are safe. */
if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM)
return false;
/* We must save every register used in this function. If this is not a
leaf function, then we must save all temporary registers. */
if (df_regs_ever_live_p (regno)
|| (!crtl->is_leaf && call_used_or_fixed_reg_p (regno)))
return true;
}
return false;
}
/* Determine whether to call GPR save/restore routines. */
static bool
riscv_use_save_libcall (const struct riscv_frame_info *frame)
{
if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed
|| cfun->machine->interrupt_handler_p)
return false;
return frame->save_libcall_adjustment != 0;
}
/* Determine which GPR save/restore routine to call. */
static unsigned
riscv_save_libcall_count (unsigned mask)
{
for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--)
if (BITSET_P (mask, n))
return CALLEE_SAVED_REG_NUMBER (n) + 1;
abort ();
}
/* Populate the current function's riscv_frame_info structure.
RISC-V stack frames grown downward. High addresses are at the top.
+-------------------------------+
| |
| incoming stack arguments |
| |
+-------------------------------+ <-- incoming stack pointer
| |
| callee-allocated save area |
| for arguments that are |
| split between registers and |
| the stack |
| |
+-------------------------------+ <-- arg_pointer_rtx
| |
| callee-allocated save area |
| for register varargs |
| |
+-------------------------------+ <-- hard_frame_pointer_rtx;
| | stack_pointer_rtx + gp_sp_offset
| GPR save area | + UNITS_PER_WORD
| |
+-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
| | + UNITS_PER_HWVALUE
| FPR save area |
| |
+-------------------------------+ <-- frame_pointer_rtx (virtual)
| |
| local variables |
| |
P +-------------------------------+
| |
| outgoing stack arguments |
| |
+-------------------------------+ <-- stack_pointer_rtx
Dynamic stack allocations such as alloca insert data at point P.
They decrease stack_pointer_rtx but leave frame_pointer_rtx and
hard_frame_pointer_rtx unchanged. */
static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame);
/* Handle stack align for poly_int. */
static poly_int64
riscv_stack_align (poly_int64 value)
{
return aligned_upper_bound (value, PREFERRED_STACK_BOUNDARY / 8);
}
static HOST_WIDE_INT
riscv_stack_align (HOST_WIDE_INT value)
{
return RISCV_STACK_ALIGN (value);
}
static void
riscv_compute_frame_info (void)
{
struct riscv_frame_info *frame;
poly_int64 offset;
bool interrupt_save_prologue_temp = false;
unsigned int regno, i, num_x_saved = 0, num_f_saved = 0;
frame = &cfun->machine->frame;
/* In an interrupt function, if we have a large frame, then we need to
save/restore t0. We check for this before clearing the frame struct. */
if (cfun->machine->interrupt_handler_p)
{
HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1)))
interrupt_save_prologue_temp = true;
}
frame->reset();
if (!cfun->machine->naked_p)
{
/* Find out which GPRs we need to save. */
for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (riscv_save_reg_p (regno)
|| (interrupt_save_prologue_temp
&& (regno == RISCV_PROLOGUE_TEMP_REGNUM)))
frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
/* If this function calls eh_return, we must also save and restore the
EH data registers. */
if (crtl->calls_eh_return)
for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++;
/* Find out which FPRs we need to save. This loop must iterate over
the same space as its companion in riscv_for_each_saved_reg. */
if (TARGET_HARD_FLOAT)
for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
if (riscv_save_reg_p (regno))
frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
}
/* At the bottom of the frame are any outgoing stack arguments. */
offset = riscv_stack_align (crtl->outgoing_args_size);
/* Next are local stack variables. */
offset += riscv_stack_align (get_frame_size ());
/* The virtual frame pointer points above the local variables. */
frame->frame_pointer_offset = offset;
/* Next are the callee-saved FPRs. */
if (frame->fmask)
offset += riscv_stack_align (num_f_saved * UNITS_PER_FP_REG);
frame->fp_sp_offset = offset - UNITS_PER_FP_REG;
/* Next are the callee-saved GPRs. */
if (frame->mask)
{
unsigned x_save_size = riscv_stack_align (num_x_saved * UNITS_PER_WORD);
unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask);
/* Only use save/restore routines if they don't alter the stack size. */
if (riscv_stack_align (num_save_restore * UNITS_PER_WORD) == x_save_size)
{
/* Libcall saves/restores 3 registers at once, so we need to
allocate 12 bytes for callee-saved register. */
if (TARGET_RVE)
x_save_size = 3 * UNITS_PER_WORD;
frame->save_libcall_adjustment = x_save_size;
}
offset += x_save_size;
}
frame->gp_sp_offset = offset - UNITS_PER_WORD;
/* The hard frame pointer points above the callee-saved GPRs. */
frame->hard_frame_pointer_offset = offset;
/* Above the hard frame pointer is the callee-allocated varags save area. */
offset += riscv_stack_align (cfun->machine->varargs_size);
/* Next is the callee-allocated area for pretend stack arguments. */
offset += riscv_stack_align (crtl->args.pretend_args_size);
/* Arg pointer must be below pretend args, but must be above alignment
padding. */
frame->arg_pointer_offset = offset - crtl->args.pretend_args_size;
frame->total_size = offset;
/* Next points the incoming stack pointer and any incoming arguments. */
/* Only use save/restore routines when the GPRs are atop the frame. */
if (known_ne (frame->hard_frame_pointer_offset, frame->total_size))
frame->save_libcall_adjustment = 0;
}
/* Make sure that we're not trying to eliminate to the wrong hard frame
pointer. */
static bool
riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
{
return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
}
/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
or argument pointer. TO is either the stack pointer or hard frame
pointer. */
poly_int64
riscv_initial_elimination_offset (int from, int to)
{
poly_int64 src, dest;
riscv_compute_frame_info ();
if (to == HARD_FRAME_POINTER_REGNUM)
dest = cfun->machine->frame.hard_frame_pointer_offset;
else if (to == STACK_POINTER_REGNUM)
dest = 0; /* The stack pointer is the base of all offsets, hence 0. */
else
gcc_unreachable ();
if (from == FRAME_POINTER_REGNUM)
src = cfun->machine->frame.frame_pointer_offset;
else if (from == ARG_POINTER_REGNUM)
src = cfun->machine->frame.arg_pointer_offset;
else
gcc_unreachable ();
return src - dest;
}
/* Implement RETURN_ADDR_RTX. We do not support moving back to a
previous frame. */
rtx
riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
{
if (count != 0)
return const0_rtx;
return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
}
/* Emit code to change the current function's return address to
ADDRESS. SCRATCH is available as a scratch register, if needed.
ADDRESS and SCRATCH are both word-mode GPRs. */
void
riscv_set_return_address (rtx address, rtx scratch)
{
rtx slot_address;
gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
slot_address = riscv_add_offset (scratch, stack_pointer_rtx,
cfun->machine->frame.gp_sp_offset.to_constant());
riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
}
/* A function to save or store a register. The first argument is the
register and the second is the stack slot. */
typedef void (*riscv_save_restore_fn) (rtx, rtx);
/* Use FN to save or restore register REGNO. MODE is the register's
mode and OFFSET is the offset of its save slot from the current
stack pointer. */
static void
riscv_save_restore_reg (machine_mode mode, int regno,
HOST_WIDE_INT offset, riscv_save_restore_fn fn)
{
rtx mem;
mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset));
fn (gen_rtx_REG (mode, regno), mem);
}
/* Call FN for each register that is saved by the current function.
SP_OFFSET is the offset of the current stack pointer from the start
of the frame. */
static void
riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn,
bool epilogue, bool maybe_eh_return)
{
HOST_WIDE_INT offset;
/* Save the link register and s-registers. */
offset = (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant ();
for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
{
bool handle_reg = TRUE;
/* If this is a normal return in a function that calls the eh_return
builtin, then do not restore the eh return data registers as that
would clobber the return value. But we do still need to save them
in the prologue, and restore them for an exception return, so we
need special handling here. */
if (epilogue && !maybe_eh_return && crtl->calls_eh_return)
{
unsigned int i, regnum;
for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM;
i++)
if (regno == regnum)
{
handle_reg = FALSE;
break;
}
}
if (handle_reg)
riscv_save_restore_reg (word_mode, regno, offset, fn);
offset -= UNITS_PER_WORD;
}
/* This loop must iterate over the same space as its companion in
riscv_compute_frame_info. */
offset = (cfun->machine->frame.fp_sp_offset - sp_offset).to_constant ();
for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
{
machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
riscv_save_restore_reg (mode, regno, offset, fn);
offset -= GET_MODE_SIZE (mode).to_constant ();
}
}
/* Save register REG to MEM. Make the instruction frame-related. */
static void
riscv_save_reg (rtx reg, rtx mem)
{
riscv_emit_move (mem, reg);
riscv_set_frame_expr (riscv_frame_set (mem, reg));
}
/* Restore register REG from MEM. */
static void
riscv_restore_reg (rtx reg, rtx mem)
{
rtx insn = riscv_emit_move (reg, mem);
rtx dwarf = NULL_RTX;
dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM)
{
rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (epilogue_cfa_sp_offset));
dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
}
REG_NOTES (insn) = dwarf;
RTX_FRAME_RELATED_P (insn) = 1;
}
/* For stack frames that can't be allocated with a single ADDI instruction,
compute the best value to initially allocate. It must at a minimum
allocate enough space to spill the callee-saved registers. If TARGET_RVC,
try to pick a value that will allow compression of the register saves
without adding extra instructions. */
static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info *frame)
{
if (SMALL_OPERAND (frame->total_size.to_constant()))
return frame->total_size.to_constant();
HOST_WIDE_INT min_first_step =
RISCV_STACK_ALIGN ((frame->total_size - frame->fp_sp_offset).to_constant());
HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8;
HOST_WIDE_INT min_second_step = frame->total_size.to_constant() - max_first_step;
gcc_assert (min_first_step <= max_first_step);
/* As an optimization, use the least-significant bits of the total frame
size, so that the second adjustment step is just LUI + ADD. */
if (!SMALL_OPERAND (min_second_step)
&& frame->total_size.to_constant() % IMM_REACH < IMM_REACH / 2
&& frame->total_size.to_constant() % IMM_REACH >= min_first_step)
return frame->total_size.to_constant() % IMM_REACH;
if (TARGET_RVC)
{
/* If we need two subtracts, and one is small enough to allow compressed
loads and stores, then put that one first. */
if (IN_RANGE (min_second_step, 0,
(TARGET_64BIT ? SDSP_REACH : SWSP_REACH)))
return MAX (min_second_step, min_first_step);
/* If we need LUI + ADDI + ADD for the second adjustment step, then start
with the minimum first step, so that we can get compressed loads and
stores. */
else if (!SMALL_OPERAND (min_second_step))
return min_first_step;
}
return max_first_step;
}
static rtx
riscv_adjust_libcall_cfi_prologue ()
{
rtx dwarf = NULL_RTX;
rtx adjust_sp_rtx, reg, mem, insn;
int saved_size = cfun->machine->frame.save_libcall_adjustment;
int offset;
for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
{
/* The save order is ra, s0, s1, s2 to s11. */
if (regno == RETURN_ADDR_REGNUM)
offset = saved_size - UNITS_PER_WORD;
else if (regno == S0_REGNUM)
offset = saved_size - UNITS_PER_WORD * 2;
else if (regno == S1_REGNUM)
offset = saved_size - UNITS_PER_WORD * 3;
else
offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD);
reg = gen_rtx_REG (SImode, regno);
mem = gen_frame_mem (SImode, plus_constant (Pmode,
stack_pointer_rtx,
offset));
insn = gen_rtx_SET (mem, reg);
dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf);
}
/* Debug info for adjust sp. */
adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx, GEN_INT (-saved_size));
dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
dwarf);
return dwarf;
}
static void
riscv_emit_stack_tie (void)
{
if (Pmode == SImode)
emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx));
else
emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx));
}
/* Expand the "prologue" pattern. */
void
riscv_expand_prologue (void)
{
struct riscv_frame_info *frame = &cfun->machine->frame;
HOST_WIDE_INT size = frame->total_size.to_constant ();
unsigned mask = frame->mask;
rtx insn;
if (flag_stack_usage_info)
current_function_static_stack_size = size;
if (cfun->machine->naked_p)
return;
/* When optimizing for size, call a subroutine to save the registers. */
if (riscv_use_save_libcall (frame))
{
rtx dwarf = NULL_RTX;
dwarf = riscv_adjust_libcall_cfi_prologue ();
size -= frame->save_libcall_adjustment;
insn = emit_insn (riscv_gen_gpr_save_insn (frame));
frame->mask = 0; /* Temporarily fib that we need not save GPRs. */
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = dwarf;
}
/* Save the registers. */
if ((frame->mask | frame->fmask) != 0)
{
HOST_WIDE_INT step1 = MIN (size, riscv_first_stack_step (frame));
insn = gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-step1));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
size -= step1;
riscv_for_each_saved_reg (size, riscv_save_reg, false, false);
}
frame->mask = mask; /* Undo the above fib. */
/* Set up the frame pointer, if we're using one. */
if (frame_pointer_needed)
{
insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx,
GEN_INT ((frame->hard_frame_pointer_offset - size).to_constant ()));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
riscv_emit_stack_tie ();
}
/* Allocate the rest of the frame. */
if (size > 0)
{
if (SMALL_OPERAND (-size))
{
insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (-size));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
}
else
{
riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size));
emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
RISCV_PROLOGUE_TEMP (Pmode)));
/* Describe the effect of the previous instructions. */
insn = plus_constant (Pmode, stack_pointer_rtx, -size);
insn = gen_rtx_SET (stack_pointer_rtx, insn);
riscv_set_frame_expr (insn);
}
}
}
static rtx
riscv_adjust_libcall_cfi_epilogue ()
{
rtx dwarf = NULL_RTX;
rtx adjust_sp_rtx, reg;
int saved_size = cfun->machine->frame.save_libcall_adjustment;
/* Debug info for adjust sp. */
adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx, GEN_INT (saved_size));
dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
dwarf);
for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
{
reg = gen_rtx_REG (SImode, regno);
dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
}
return dwarf;
}
/* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
style says which. */
void
riscv_expand_epilogue (int style)
{
/* Split the frame into two. STEP1 is the amount of stack we should
deallocate before restoring the registers. STEP2 is the amount we
should deallocate afterwards.
Start off by assuming that no registers need to be restored. */
struct riscv_frame_info *frame = &cfun->machine->frame;
unsigned mask = frame->mask;
HOST_WIDE_INT step1 = frame->total_size.to_constant ();
HOST_WIDE_INT step2 = 0;
bool use_restore_libcall = ((style == NORMAL_RETURN)
&& riscv_use_save_libcall (frame));
rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
rtx insn;
/* We need to add memory barrier to prevent read from deallocated stack. */
bool need_barrier_p = known_ne (get_frame_size ()
+ cfun->machine->frame.arg_pointer_offset, 0);
if (cfun->machine->naked_p)
{
gcc_assert (style == NORMAL_RETURN);
emit_jump_insn (gen_return ());
return;
}
if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ())
{
emit_jump_insn (gen_return ());
return;
}
/* Reset the epilogue cfa info before starting to emit the epilogue. */
epilogue_cfa_sp_offset = 0;
/* Move past any dynamic stack allocations. */
if (cfun->calls_alloca)
{
/* Emit a barrier to prevent loads from a deallocated stack. */
riscv_emit_stack_tie ();
need_barrier_p = false;
rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset.to_constant ());
if (!SMALL_OPERAND (INTVAL (adjust)))
{
riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
adjust = RISCV_PROLOGUE_TEMP (Pmode);
}
insn = emit_insn (
gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx,
adjust));
rtx dwarf = NULL_RTX;
rtx cfa_adjust_value = gen_rtx_PLUS (
Pmode, hard_frame_pointer_rtx,
GEN_INT (-frame->hard_frame_pointer_offset.to_constant ()));
rtx cfa_adjust_rtx = gen_rtx_SET (stack_pointer_rtx, cfa_adjust_value);
dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, cfa_adjust_rtx, dwarf);
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = dwarf;
}
/* If we need to restore registers, deallocate as much stack as
possible in the second step without going out of range. */
if ((frame->mask | frame->fmask) != 0)
{
step2 = riscv_first_stack_step (frame);
step1 -= step2;
}
/* Set TARGET to BASE + STEP1. */
if (known_gt (step1, 0))
{
/* Emit a barrier to prevent loads from a deallocated stack. */
riscv_emit_stack_tie ();
need_barrier_p = false;
/* Get an rtx for STEP1 that we can add to BASE. */
rtx adjust = GEN_INT (step1);
if (!SMALL_OPERAND (step1))
{
riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
adjust = RISCV_PROLOGUE_TEMP (Pmode);
}
insn = emit_insn (
gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
rtx dwarf = NULL_RTX;
rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (step2));
dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = dwarf;
}
else if (frame_pointer_needed)
{
/* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
old value of FP. */
epilogue_cfa_sp_offset = step2;
}
if (use_restore_libcall)
frame->mask = 0; /* Temporarily fib that we need not save GPRs. */
/* Restore the registers. */
riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg,
true, style == EXCEPTION_RETURN);
if (use_restore_libcall)
{
frame->mask = mask; /* Undo the above fib. */
gcc_assert (step2 >= frame->save_libcall_adjustment);
step2 -= frame->save_libcall_adjustment;
}
if (need_barrier_p)
riscv_emit_stack_tie ();
/* Deallocate the final bit of the frame. */
if (step2 > 0)
{
insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (step2)));
rtx dwarf = NULL_RTX;
rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
const0_rtx);
dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = dwarf;
}
if (use_restore_libcall)
{
rtx dwarf = riscv_adjust_libcall_cfi_epilogue ();
insn = emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask))));
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = dwarf;
emit_jump_insn (gen_gpr_restore_return (ra));
return;
}
/* Add in the __builtin_eh_return stack adjustment. */
if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return)
emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
EH_RETURN_STACKADJ_RTX));
/* Return from interrupt. */
if (cfun->machine->interrupt_handler_p)
{
enum riscv_privilege_levels mode = cfun->machine->interrupt_mode;
gcc_assert (mode != UNKNOWN_MODE);
if (mode == MACHINE_MODE)
emit_jump_insn (gen_riscv_mret ());
else if (mode == SUPERVISOR_MODE)
emit_jump_insn (gen_riscv_sret ());
else
emit_jump_insn (gen_riscv_uret ());
}
else if (style != SIBCALL_RETURN)
emit_jump_insn (gen_simple_return_internal (ra));
}
/* Implement EPILOGUE_USES. */
bool
riscv_epilogue_uses (unsigned int regno)
{
if (regno == RETURN_ADDR_REGNUM)
return true;
if (epilogue_completed && cfun->machine->interrupt_handler_p)
{
/* An interrupt function restores temp regs, so we must indicate that
they are live at function end. */
if (df_regs_ever_live_p (regno)
|| (!crtl->is_leaf && call_used_or_fixed_reg_p (regno)))
return true;
}
return false;
}
/* Return nonzero if this function is known to have a null epilogue.
This allows the optimizer to omit jumps to jumps if no stack
was created. */
bool
riscv_can_use_return_insn (void)
{
return (reload_completed && known_eq (cfun->machine->frame.total_size, 0)
&& ! cfun->machine->interrupt_handler_p);
}
/* Given that there exists at least one variable that is set (produced)
by OUT_INSN and read (consumed) by IN_INSN, return true iff
IN_INSN represents one or more memory store operations and none of
the variables set by OUT_INSN is used by IN_INSN as the address of a
store operation. If either IN_INSN or OUT_INSN does not represent
a "single" RTL SET expression (as loosely defined by the
implementation of the single_set function) or a PARALLEL with only
SETs, CLOBBERs, and USEs inside, this function returns false.
Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
conditions that result in assertion failures in the generic
store_data_bypass_p function and returns FALSE in such cases.
This is required to make -msave-restore work with the sifive-7
pipeline description. */
bool
riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
{
rtx out_set, in_set;
rtx out_pat, in_pat;
rtx out_exp, in_exp;
int i, j;
in_set = single_set (in_insn);
if (in_set)
{
if (MEM_P (SET_DEST (in_set)))
{
out_set = single_set (out_insn);
if (!out_set)
{
out_pat = PATTERN (out_insn);
if (GET_CODE (out_pat) == PARALLEL)
{
for (i = 0; i < XVECLEN (out_pat, 0); i++)
{
out_exp = XVECEXP (out_pat, 0, i);
if ((GET_CODE (out_exp) == CLOBBER)
|| (GET_CODE (out_exp) == USE))
continue;
else if (GET_CODE (out_exp) != SET)
return false;
}
}
}
}
}
else
{
in_pat = PATTERN (in_insn);
if (GET_CODE (in_pat) != PARALLEL)
return false;
for (i = 0; i < XVECLEN (in_pat, 0); i++)
{
in_exp = XVECEXP (in_pat, 0, i);
if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
continue;
else if (GET_CODE (in_exp) != SET)
return false;
if (MEM_P (SET_DEST (in_exp)))
{
out_set = single_set (out_insn);
if (!out_set)
{
out_pat = PATTERN (out_insn);
if (GET_CODE (out_pat) != PARALLEL)
return false;
for (j = 0; j < XVECLEN (out_pat, 0); j++)
{
out_exp = XVECEXP (out_pat, 0, j);
if ((GET_CODE (out_exp) == CLOBBER)
|| (GET_CODE (out_exp) == USE))
continue;
else if (GET_CODE (out_exp) != SET)
return false;
}
}
}
}
}
return store_data_bypass_p (out_insn, in_insn);
}
/* Implement TARGET_SECONDARY_MEMORY_NEEDED.
When floating-point registers are wider than integer ones, moves between
them must go through memory. */
static bool
riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,
reg_class_t class2)
{
return (!riscv_v_ext_vector_mode_p (mode)
&& GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD
&& (class1 == FP_REGS) != (class2 == FP_REGS));
}
/* Implement TARGET_REGISTER_MOVE_COST. */
static int
riscv_register_move_cost (machine_mode mode,
reg_class_t from, reg_class_t to)
{
if ((from == FP_REGS && to == GR_REGS) ||
(from == GR_REGS && to == FP_REGS))
return tune_param->fmv_cost;
return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2;
}
/* Implement TARGET_HARD_REGNO_NREGS. */
static unsigned int
riscv_hard_regno_nregs (unsigned int regno, machine_mode mode)
{
if (riscv_v_ext_vector_mode_p (mode))
{
/* Handle fractional LMUL, it only occupy part of vector register but
still need one vector register to hold. */
if (maybe_lt (GET_MODE_SIZE (mode), UNITS_PER_V_REG))
return 1;
return exact_div (GET_MODE_SIZE (mode), UNITS_PER_V_REG).to_constant ();
}
/* mode for VL or VTYPE are just a marker, not holding value,
so it always consume one register. */
if (regno == VTYPE_REGNUM || regno == VL_REGNUM)
return 1;
/* Assume every valid non-vector mode fits in one vector register. */
if (V_REG_P (regno))
return 1;
if (FP_REG_P (regno))
return (GET_MODE_SIZE (mode).to_constant () + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG;
/* All other registers are word-sized. */
return (GET_MODE_SIZE (mode).to_constant () + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
unsigned int nregs = riscv_hard_regno_nregs (regno, mode);
if (GP_REG_P (regno))
{
if (riscv_v_ext_vector_mode_p (mode))
return false;
if (!GP_REG_P (regno + nregs - 1))
return false;
}
else if (FP_REG_P (regno))
{
if (riscv_v_ext_vector_mode_p (mode))
return false;
if (!FP_REG_P (regno + nregs - 1))
return false;
if (GET_MODE_CLASS (mode) != MODE_FLOAT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
return false;
/* Only use callee-saved registers if a potential callee is guaranteed
to spill the requisite width. */
if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG
|| (!call_used_or_fixed_reg_p (regno)
&& GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_ARG))
return false;
}
else if (V_REG_P (regno))
{
if (!riscv_v_ext_vector_mode_p (mode))
return false;
if (!V_REG_P (regno + nregs - 1))
return false;
/* 3.3.2. LMUL = 2,4,8, register numbers should be multiple of 2,4,8.
but for mask vector register, register numbers can be any number. */
int lmul = 1;
if (known_gt (GET_MODE_SIZE (mode), UNITS_PER_V_REG))
lmul = exact_div (GET_MODE_SIZE (mode), UNITS_PER_V_REG).to_constant ();
if (lmul != 1)
return ((regno % lmul) == 0);
}
else if (regno == VL_REGNUM || regno == VTYPE_REGNUM)
return true;
else
return false;
/* Require same callee-savedness for all registers. */
for (unsigned i = 1; i < nregs; i++)
if (call_used_or_fixed_reg_p (regno)
!= call_used_or_fixed_reg_p (regno + i))
return false;
/* Only use even registers in RV32 ZDINX */
if (!TARGET_64BIT && TARGET_ZDINX){
if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
return !(regno & 1);
}
return true;
}
/* Implement TARGET_MODES_TIEABLE_P.
Don't allow floating-point modes to be tied, since type punning of
single-precision and double-precision is implementation defined. */
static bool
riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
return (mode1 == mode2
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
}
/* Implement CLASS_MAX_NREGS. */
static unsigned char
riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
{
if (reg_class_subset_p (rclass, FP_REGS))
return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
if (reg_class_subset_p (rclass, GR_REGS))
return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
if (reg_class_subset_p (rclass, V_REGS))
return riscv_hard_regno_nregs (V_REG_FIRST, mode);
if (reg_class_subset_p (rclass, VL_REGS))
return 1;
if (reg_class_subset_p (rclass, VTYPE_REGS))
return 1;
return 0;
}
/* Implement TARGET_MEMORY_MOVE_COST. */
static int
riscv_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in)
{
return (tune_param->memory_cost
+ memory_move_secondary_cost (mode, rclass, in));
}
/* Return the number of instructions that can be issued per cycle. */
static int
riscv_issue_rate (void)
{
return tune_param->issue_rate;
}
/* Auxiliary function to emit RISC-V ELF attribute. */
static void
riscv_emit_attribute ()
{
fprintf (asm_out_file, "\t.attribute arch, \"%s\"\n",
riscv_arch_str ().c_str ());
fprintf (asm_out_file, "\t.attribute unaligned_access, %d\n",
TARGET_STRICT_ALIGN ? 0 : 1);
fprintf (asm_out_file, "\t.attribute stack_align, %d\n",
riscv_stack_boundary / 8);
}
/* Implement TARGET_ASM_FILE_START. */
static void
riscv_file_start (void)
{
default_file_start ();
/* Instruct GAS to generate position-[in]dependent code. */
fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
/* If the user specifies "-mno-relax" on the command line then disable linker
relaxation in the assembler. */
if (! riscv_mrelax)
fprintf (asm_out_file, "\t.option norelax\n");
/* If the user specifies "-mcsr-check" on the command line then enable csr
check in the assembler. */
if (riscv_mcsr_check)
fprintf (asm_out_file, "\t.option csr-check\n");
if (riscv_emit_attribute_p)
riscv_emit_attribute ();
}
/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
in order to avoid duplicating too much logic from elsewhere. */
static void
riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
rtx this_rtx, temp1, temp2, fnaddr;
rtx_insn *insn;
/* Pretend to be a post-reload pass while generating rtl. */
reload_completed = 1;
/* Mark the end of the (empty) prologue. */
emit_note (NOTE_INSN_PROLOGUE_END);
/* Determine if we can use a sibcall to call FUNCTION directly. */
fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0));
/* We need two temporary registers in some cases. */
temp1 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM);
temp2 = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
/* Find out which register contains the "this" pointer. */
if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
else
this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
/* Add DELTA to THIS_RTX. */
if (delta != 0)
{
rtx offset = GEN_INT (delta);
if (!SMALL_OPERAND (delta))
{
riscv_emit_move (temp1, offset);
offset = temp1;
}
emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
}
/* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
if (vcall_offset != 0)
{
rtx addr;
/* Set TEMP1 to *THIS_RTX. */
riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
/* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
addr = riscv_add_offset (temp2, temp1, vcall_offset);
/* Load the offset and add it to THIS_RTX. */
riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
}
/* Jump to the target function. */
insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, NULL, const0_rtx));
SIBLING_CALL_P (insn) = 1;
/* Run just enough of rest_of_compilation. This sequence was
"borrowed" from alpha.cc. */
insn = get_insns ();
split_all_insns_noflow ();
shorten_branches (insn);
assemble_start_function (thunk_fndecl, fnname);
final_start_function (insn, file, 1);
final (insn, file, 1);
final_end_function ();
assemble_end_function (thunk_fndecl, fnname);
/* Clean up the vars set above. Note that final_end_function resets
the global pointer for us. */
reload_completed = 0;
}
/* Allocate a chunk of memory for per-function machine-dependent data. */
static struct machine_function *
riscv_init_machine_status (void)
{
return ggc_cleared_alloc<machine_function> ();
}
/* Return the VLEN value associated with -march.
TODO: So far we only support length-agnostic value. */
static poly_uint16
riscv_convert_vector_bits (void)
{
if (TARGET_MIN_VLEN > 32)
{
/* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
Otherwise we can not include SEW = 64bits.
Runtime invariant: The single indeterminate represent the
number of 64-bit chunks in a vector beyond minimum length of 64 bits.
Thus the number of bytes in a vector is 8 + 8 * x1 which is
riscv_vector_chunks * 8 = poly_int (8, 8). */
riscv_bytes_per_vector_chunk = 8;
}
else
{
/* When targetting minimum VLEN = 32, we should use 32-bit
chunk size. Runtime invariant: The single indeterminate represent the
number of 32-bit chunks in a vector beyond minimum length of 32 bits.
Thus the number of bytes in a vector is 4 + 4 * x1 which is
riscv_vector_chunks * 4 = poly_int (4, 4). */
riscv_bytes_per_vector_chunk = 4;
}
/* Set riscv_vector_chunks as poly (1, 1) run-time constant if TARGET_VECTOR
is enabled. Set riscv_vector_chunks as 1 compile-time constant if
TARGET_VECTOR is disabled. riscv_vector_chunks is used in "riscv-modes.def"
to set RVV mode size. The RVV machine modes size are run-time constant if
TARGET_VECTOR is enabled. The RVV machine modes size remains default
compile-time constant if TARGET_VECTOR is disabled. */
return TARGET_VECTOR ? poly_uint16 (1, 1) : 1;
}
/* Implement TARGET_OPTION_OVERRIDE. */
static void
riscv_option_override (void)
{
const struct riscv_tune_info *cpu;
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
#endif
flag_pcc_struct_return = 0;
if (flag_pic)
g_switch_value = 0;
/* The presence of the M extension implies that division instructions
are present, so include them unless explicitly disabled. */
if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
target_flags |= MASK_DIV;
else if (!TARGET_MUL && TARGET_DIV)
error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
/* Likewise floating-point division and square root. */
if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
target_flags |= MASK_FDIV;
/* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
if -mtune and -mcpu both not given. */
cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string :
(riscv_cpu_string ? riscv_cpu_string :
RISCV_TUNE_STRING_DEFAULT));
riscv_microarchitecture = cpu->microarchitecture;
tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param;
/* Use -mtune's setting for slow_unaligned_access, even when optimizing
for size. For architectures that trap and emulate unaligned accesses,
the performance cost is too great, even for -Os. Similarly, if
-m[no-]strict-align is left unspecified, heed -mtune's advice. */
riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
|| TARGET_STRICT_ALIGN);
if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
&& cpu->tune_param->slow_unaligned_access)
target_flags |= MASK_STRICT_ALIGN;
/* If the user hasn't specified a branch cost, use the processor's
default. */
if (riscv_branch_cost == 0)
riscv_branch_cost = tune_param->branch_cost;
/* Function to allocate machine-dependent function status. */
init_machine_status = &riscv_init_machine_status;
if (flag_pic)
riscv_cmodel = CM_PIC;
/* We get better code with explicit relocs for CM_MEDLOW, but
worse code for the others (for now). Pick the best default. */
if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
if (riscv_cmodel == CM_MEDLOW)
target_flags |= MASK_EXPLICIT_RELOCS;
/* Require that the ISA supports the requested floating-point ABI. */
if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0))
error ("requested ABI requires %<-march%> to subsume the %qc extension",
UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
if (TARGET_RVE && riscv_abi != ABI_ILP32E)
error ("rv32e requires ilp32e ABI");
// Zfinx require abi ilp32,ilp32e or lp64.
if (TARGET_ZFINX && riscv_abi != ABI_ILP32
&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
error ("z*inx requires ABI ilp32, ilp32e or lp64");
/* We do not yet support ILP32 on RV64. */
if (BITS_PER_WORD != POINTER_SIZE)
error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
/* Validate -mpreferred-stack-boundary= value. */
riscv_stack_boundary = ABI_STACK_BOUNDARY;
if (riscv_preferred_stack_boundary_arg)
{
int min = ctz_hwi (STACK_BOUNDARY / 8);
int max = 8;
if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max))
error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d",
riscv_preferred_stack_boundary_arg, min, max);
riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg;
}
if (riscv_emit_attribute_p < 0)
#ifdef HAVE_AS_RISCV_ATTRIBUTE
riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE;
#else
riscv_emit_attribute_p = 0;
if (riscv_emit_attribute_p)
error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"
" [%<-mriscv-attribute%>]");
#endif
if (riscv_stack_protector_guard == SSP_GLOBAL
&& OPTION_SET_P (riscv_stack_protector_guard_offset_str))
{
error ("incompatible options %<-mstack-protector-guard=global%> and "
"%<-mstack-protector-guard-offset=%s%>",
riscv_stack_protector_guard_offset_str);
}
if (riscv_stack_protector_guard == SSP_TLS
&& !(OPTION_SET_P (riscv_stack_protector_guard_offset_str)
&& OPTION_SET_P (riscv_stack_protector_guard_reg_str)))
{
error ("both %<-mstack-protector-guard-offset%> and "
"%<-mstack-protector-guard-reg%> must be used "
"with %<-mstack-protector-guard=sysreg%>");
}
if (OPTION_SET_P (riscv_stack_protector_guard_reg_str))
{
const char *str = riscv_stack_protector_guard_reg_str;
int reg = decode_reg_name (str);
if (!IN_RANGE (reg, GP_REG_FIRST + 1, GP_REG_LAST))
error ("%qs is not a valid base register in %qs", str,
"-mstack-protector-guard-reg=");
riscv_stack_protector_guard_reg = reg;
}
if (OPTION_SET_P (riscv_stack_protector_guard_offset_str))
{
char *end;
const char *str = riscv_stack_protector_guard_offset_str;
errno = 0;
long offs = strtol (riscv_stack_protector_guard_offset_str, &end, 0);
if (!*str || *end || errno)
error ("%qs is not a valid number in %qs", str,
"-mstack-protector-guard-offset=");
if (!SMALL_OPERAND (offs))
error ("%qs is not a valid offset in %qs", str,
"-mstack-protector-guard-offset=");
riscv_stack_protector_guard_offset = offs;
}
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits ();
}
/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
static void
riscv_conditional_register_usage (void)
{
/* We have only x0~x15 on RV32E. */
if (TARGET_RVE)
{
for (int r = 16; r <= 31; r++)
fixed_regs[r] = 1;
}
if (riscv_abi == ABI_ILP32E)
{
for (int r = 16; r <= 31; r++)
call_used_regs[r] = 1;
}
if (!TARGET_HARD_FLOAT)
{
for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
}
/* In the soft-float ABI, there are no callee-saved FP registers. */
if (UNITS_PER_FP_ARG == 0)
{
for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
call_used_regs[regno] = 1;
}
if (!TARGET_VECTOR)
{
for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
}
}
/* Return a register priority for hard reg REGNO. */
static int
riscv_register_priority (int regno)
{
/* Favor compressed registers to improve the odds of RVC instruction
selection. */
if (riscv_compressed_reg_p (regno))
return 1;
return 0;
}
/* Implement TARGET_TRAMPOLINE_INIT. */
static void
riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
{
rtx addr, end_addr, mem;
uint32_t trampoline[4];
unsigned int i;
HOST_WIDE_INT static_chain_offset, target_function_offset;
/* Work out the offsets of the pointers from the start of the
trampoline code. */
gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE);
/* Get pointers to the beginning and end of the code block. */
addr = force_reg (Pmode, XEXP (m_tramp, 0));
end_addr = riscv_force_binary (Pmode, PLUS, addr,
GEN_INT (TRAMPOLINE_CODE_SIZE));
if (Pmode == SImode)
{
chain_value = force_reg (Pmode, chain_value);
rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0));
/* lui t2, hi(chain)
lui t0, hi(func)
addi t2, t2, lo(chain)
jr t0, lo(func)
*/
unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code;
unsigned HOST_WIDE_INT lo_chain_code, lo_func_code;
rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode));
/* 0xfff. */
rtx imm12_mask = gen_reg_rtx (SImode);
emit_insn (gen_one_cmplsi2 (imm12_mask, uimm_mask));
rtx fixup_value = force_reg (SImode, gen_int_mode (IMM_REACH/2, SImode));
/* Gen lui t2, hi(chain). */
rtx hi_chain = riscv_force_binary (SImode, PLUS, chain_value,
fixup_value);
hi_chain = riscv_force_binary (SImode, AND, hi_chain,
uimm_mask);
lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD);
rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain,
gen_int_mode (lui_hi_chain_code, SImode));
mem = adjust_address (m_tramp, SImode, 0);
riscv_emit_move (mem, riscv_swap_instruction (lui_hi_chain));
/* Gen lui t0, hi(func). */
rtx hi_func = riscv_force_binary (SImode, PLUS, target_function,
fixup_value);
hi_func = riscv_force_binary (SImode, AND, hi_func,
uimm_mask);
lui_hi_func_code = OPCODE_LUI | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD);
rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func,
gen_int_mode (lui_hi_func_code, SImode));
mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, riscv_swap_instruction (lui_hi_func));
/* Gen addi t2, t2, lo(chain). */
rtx lo_chain = riscv_force_binary (SImode, AND, chain_value,
imm12_mask);
lo_chain = riscv_force_binary (SImode, ASHIFT, lo_chain, GEN_INT (20));
lo_chain_code = OPCODE_ADDI
| (STATIC_CHAIN_REGNUM << SHIFT_RD)
| (STATIC_CHAIN_REGNUM << SHIFT_RS1);
rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain,
force_reg (SImode, GEN_INT (lo_chain_code)));
mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, riscv_swap_instruction (addi_lo_chain));
/* Gen jr t0, lo(func). */
rtx lo_func = riscv_force_binary (SImode, AND, target_function,
imm12_mask);
lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20));
lo_func_code = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1);
rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func,
force_reg (SImode, GEN_INT (lo_func_code)));
mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, riscv_swap_instruction (jr_lo_func));
}
else
{
static_chain_offset = TRAMPOLINE_CODE_SIZE;
target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
/* auipc t2, 0
l[wd] t0, target_function_offset(t2)
l[wd] t2, static_chain_offset(t2)
jr t0
*/
trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD);
trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
| (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD)
| (STATIC_CHAIN_REGNUM << SHIFT_RS1)
| (target_function_offset << SHIFT_IMM);
trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW)
| (STATIC_CHAIN_REGNUM << SHIFT_RD)
| (STATIC_CHAIN_REGNUM << SHIFT_RS1)
| (static_chain_offset << SHIFT_IMM);
trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1);
/* Copy the trampoline code. */
for (i = 0; i < ARRAY_SIZE (trampoline); i++)
{
if (BYTES_BIG_ENDIAN)
trampoline[i] = __builtin_bswap32(trampoline[i]);
mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode));
riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode));
}
/* Set up the static chain pointer field. */
mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
riscv_emit_move (mem, chain_value);
/* Set up the target function field. */
mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
}
/* Flush the code part of the trampoline. */
emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
emit_insn (gen_clear_cache (addr, end_addr));
}
/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
static bool
riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
tree exp ATTRIBUTE_UNUSED)
{
/* Don't use sibcalls when use save-restore routine. */
if (TARGET_SAVE_RESTORE)
return false;
/* Don't use sibcall for naked functions. */
if (cfun->machine->naked_p)
return false;
/* Don't use sibcall for interrupt functions. */
if (cfun->machine->interrupt_handler_p)
return false;
return true;
}
/* Get the interrupt type, return UNKNOWN_MODE if it's not
interrupt function. */
static enum riscv_privilege_levels
riscv_get_interrupt_type (tree decl)
{
gcc_assert (decl != NULL_TREE);
if ((TREE_CODE(decl) != FUNCTION_DECL)
|| (!riscv_interrupt_type_p (TREE_TYPE (decl))))
return UNKNOWN_MODE;
tree attr_args
= TREE_VALUE (lookup_attribute ("interrupt",
TYPE_ATTRIBUTES (TREE_TYPE (decl))));
if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE)
{
const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args));
if (!strcmp (string, "user"))
return USER_MODE;
else if (!strcmp (string, "supervisor"))
return SUPERVISOR_MODE;
else /* Must be "machine". */
return MACHINE_MODE;
}
else
/* Interrupt attributes are machine mode by default. */
return MACHINE_MODE;
}
/* Implement `TARGET_SET_CURRENT_FUNCTION'. */
/* Sanity cheching for above function attributes. */
static void
riscv_set_current_function (tree decl)
{
if (decl == NULL_TREE
|| current_function_decl == NULL_TREE
|| current_function_decl == error_mark_node
|| ! cfun->machine
|| cfun->machine->attributes_checked_p)
return;
cfun->machine->naked_p = riscv_naked_function_p (decl);
cfun->machine->interrupt_handler_p
= riscv_interrupt_type_p (TREE_TYPE (decl));
if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p)
error ("function attributes %qs and %qs are mutually exclusive",
"interrupt", "naked");
if (cfun->machine->interrupt_handler_p)
{
tree ret = TREE_TYPE (TREE_TYPE (decl));
tree args = TYPE_ARG_TYPES (TREE_TYPE (decl));
if (TREE_CODE (ret) != VOID_TYPE)
error ("%qs function cannot return a value", "interrupt");
if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
error ("%qs function cannot have arguments", "interrupt");
cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl);
gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE);
}
/* Don't print the above diagnostics more than once. */
cfun->machine->attributes_checked_p = 1;
}
/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
static tree
riscv_merge_decl_attributes (tree olddecl, tree newdecl)
{
tree combined_attrs;
enum riscv_privilege_levels old_interrupt_type
= riscv_get_interrupt_type (olddecl);
enum riscv_privilege_levels new_interrupt_type
= riscv_get_interrupt_type (newdecl);
/* Check old and new has same interrupt type. */
if ((old_interrupt_type != UNKNOWN_MODE)
&& (new_interrupt_type != UNKNOWN_MODE)
&& (old_interrupt_type != new_interrupt_type))
error ("%qs function cannot have different interrupt type", "interrupt");
/* Create combined attributes. */
combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl),
DECL_ATTRIBUTES (newdecl));
return combined_attrs;
}
/* Implement TARGET_CANNOT_COPY_INSN_P. */
static bool
riscv_cannot_copy_insn_p (rtx_insn *insn)
{
return recog_memoized (insn) >= 0 && get_attr_cannot_copy (insn);
}
/* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
static bool
riscv_slow_unaligned_access (machine_mode, unsigned int)
{
return riscv_slow_unaligned_access_p;
}
/* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
static bool
riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass)
{
return !reg_classes_intersect_p (FP_REGS, rclass);
}
/* Implement TARGET_CONSTANT_ALIGNMENT. */
static HOST_WIDE_INT
riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align)
{
if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR)
&& (riscv_align_data_type == riscv_align_data_type_xlen))
return MAX (align, BITS_PER_WORD);
return align;
}
/* Implement TARGET_PROMOTE_FUNCTION_MODE. */
/* This function is equivalent to default_promote_function_mode_always_promote
except that it returns a promoted mode even if type is NULL_TREE. This is
needed by libcalls which have no type (only a mode) such as fixed conversion
routines that take a signed or unsigned char/short/int argument and convert
it to a fixed type. */
static machine_mode
riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
machine_mode mode,
int *punsignedp ATTRIBUTE_UNUSED,
const_tree fntype ATTRIBUTE_UNUSED,
int for_return ATTRIBUTE_UNUSED)
{
int unsignedp;
if (type != NULL_TREE)
return promote_mode (type, mode, punsignedp);
unsignedp = *punsignedp;
PROMOTE_MODE (as_a <scalar_mode> (mode), unsignedp, type);
*punsignedp = unsignedp;
return mode;
}
/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
static void
riscv_reorg (void)
{
/* Do nothing unless we have -msave-restore */
if (TARGET_SAVE_RESTORE)
riscv_remove_unneeded_save_restore_calls ();
}
/* Return nonzero if register FROM_REGNO can be renamed to register
TO_REGNO. */
bool
riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED,
unsigned to_regno)
{
/* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be
call-clobbered. */
return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno);
}
/* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
bool
riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
{
/* Prefer old address if it is less expensive. */
addr_space_t as = MEM_ADDR_SPACE (memref);
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
int old_cost = address_cost (XEXP (memref, 0), GET_MODE (memref), as, speed);
int new_cost = address_cost (new_addr, GET_MODE (memref), as, speed);
return new_cost <= old_cost;
}
/* Helper function for generating gpr_save pattern. */
rtx
riscv_gen_gpr_save_insn (struct riscv_frame_info *frame)
{
unsigned count = riscv_save_libcall_count (frame->mask);
/* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
unsigned veclen = 1 + 2 + 1 + count;
rtvec vec = rtvec_alloc (veclen);
gcc_assert (veclen <= ARRAY_SIZE (gpr_save_reg_order));
RTVEC_ELT (vec, 0) =
gen_rtx_UNSPEC_VOLATILE (VOIDmode,
gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE);
for (unsigned i = 1; i < veclen; ++i)
{
unsigned regno = gpr_save_reg_order[i];
rtx reg = gen_rtx_REG (Pmode, regno);
rtx elt;
/* t0 and t1 are CLOBBERs, others are USEs. */
if (i < 3)
elt = gen_rtx_CLOBBER (Pmode, reg);
else
elt = gen_rtx_USE (Pmode, reg);
RTVEC_ELT (vec, i) = elt;
}
/* Largest number of caller-save register must set in mask if we are
not using __riscv_save_0. */
gcc_assert ((count == 0) ||
BITSET_P (frame->mask, gpr_save_reg_order[veclen - 1]));
return gen_rtx_PARALLEL (VOIDmode, vec);
}
/* Return true if it's valid gpr_save pattern. */
bool
riscv_gpr_save_operation_p (rtx op)
{
unsigned len = XVECLEN (op, 0);
if (len > ARRAY_SIZE (gpr_save_reg_order))
return false;
for (unsigned i = 0; i < len; i++)
{
rtx elt = XVECEXP (op, 0, i);
if (i == 0)
{
/* First element in parallel is unspec. */
if (GET_CODE (elt) != UNSPEC_VOLATILE
|| GET_CODE (XVECEXP (elt, 0, 0)) != CONST_INT
|| XINT (elt, 1) != UNSPECV_GPR_SAVE)
return false;
}
else
{
/* Two CLOBBER and USEs, must check the order. */
unsigned expect_code = i < 3 ? CLOBBER : USE;
if (GET_CODE (elt) != expect_code
|| !REG_P (XEXP (elt, 1))
|| (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i]))
return false;
}
break;
}
return true;
}
/* Implement TARGET_ASAN_SHADOW_OFFSET. */
static unsigned HOST_WIDE_INT
riscv_asan_shadow_offset (void)
{
/* We only have libsanitizer support for RV64 at present.
This number must match kRiscv*_ShadowOffset* in the file
libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
even though 1<<36 makes more sense. */
return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
}
/* Implement TARGET_MANGLE_TYPE. */
static const char *
riscv_mangle_type (const_tree type)
{
/* Half-precision float, _Float16 is "DF16_". */
if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16)
return "DF16_";
/* Mangle all vector type for vector extension. */
/* The mangle name follows the rule of RVV LLVM
that is "u" + length of (abi_name) + abi_name. */
if (TYPE_NAME (type) != NULL)
{
const char *res = riscv_vector::mangle_builtin_type (type);
if (res)
return res;
}
/* Use the default mangling. */
return NULL;
}
/* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
static bool
riscv_scalar_mode_supported_p (scalar_mode mode)
{
if (mode == HFmode)
return true;
else
return default_scalar_mode_supported_p (mode);
}
/* Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P - return TRUE
if MODE is HFmode, and punt to the generic implementation otherwise. */
static bool
riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode)
{
if (mode == HFmode)
return true;
else
return default_libgcc_floating_mode_supported_p (mode);
}
/* Set the value of FLT_EVAL_METHOD.
ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
0: evaluate all operations and constants, whose semantic type has at
most the range and precision of type float, to the range and
precision of float; evaluate all other operations and constants to
the range and precision of the semantic type;
N, where _FloatN is a supported interchange floating type
evaluate all operations and constants, whose semantic type has at
most the range and precision of _FloatN type, to the range and
precision of the _FloatN type; evaluate all other operations and
constants to the range and precision of the semantic type;
If we have the zfh/zhinx extensions then we support _Float16 in native
precision, so we should set this to 16. */
static enum flt_eval_method
riscv_excess_precision (enum excess_precision_type type)
{
switch (type)
{
case EXCESS_PRECISION_TYPE_FAST:
case EXCESS_PRECISION_TYPE_STANDARD:
return ((TARGET_ZFH || TARGET_ZHINX)
? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
: FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
case EXCESS_PRECISION_TYPE_IMPLICIT:
case EXCESS_PRECISION_TYPE_FLOAT16:
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;
default:
gcc_unreachable ();
}
return FLT_EVAL_METHOD_UNPREDICTABLE;
}
/* Implement TARGET_FLOATN_MODE. */
static opt_scalar_float_mode
riscv_floatn_mode (int n, bool extended)
{
if (!extended && n == 16)
return HFmode;
return default_floatn_mode (n, extended);
}
static void
riscv_init_libfuncs (void)
{
/* Half-precision float operations. The compiler handles all operations
with NULL libfuncs by converting to SFmode. */
/* Arithmetic. */
set_optab_libfunc (add_optab, HFmode, NULL);
set_optab_libfunc (sdiv_optab, HFmode, NULL);
set_optab_libfunc (smul_optab, HFmode, NULL);
set_optab_libfunc (neg_optab, HFmode, NULL);
set_optab_libfunc (sub_optab, HFmode, NULL);
/* Comparisons. */
set_optab_libfunc (eq_optab, HFmode, NULL);
set_optab_libfunc (ne_optab, HFmode, NULL);
set_optab_libfunc (lt_optab, HFmode, NULL);
set_optab_libfunc (le_optab, HFmode, NULL);
set_optab_libfunc (ge_optab, HFmode, NULL);
set_optab_libfunc (gt_optab, HFmode, NULL);
set_optab_libfunc (unord_optab, HFmode, NULL);
}
#if CHECKING_P
void
riscv_reinit (void)
{
riscv_option_override ();
init_adjust_machine_modes ();
init_derived_machine_modes ();
reinit_regs ();
init_optabs ();
}
#endif
#if CHECKING_P
#undef TARGET_RUN_TARGET_SELFTESTS
#define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests
#endif /* #if CHECKING_P */
/* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
static bool
riscv_vector_mode_supported_p (machine_mode mode)
{
if (TARGET_VECTOR)
return riscv_v_ext_vector_mode_p (mode);
return false;
}
/* Implement TARGET_VERIFY_TYPE_CONTEXT. */
static bool
riscv_verify_type_context (location_t loc, type_context_kind context,
const_tree type, bool silent_p)
{
return riscv_vector::verify_type_context (loc, context, type, silent_p);
}
/* Implement TARGET_VECTOR_ALIGNMENT. */
static HOST_WIDE_INT
riscv_vector_alignment (const_tree type)
{
/* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
be set for non-predicate vectors of booleans. Modes are the most
direct way we have of identifying real RVV predicate types. */
/* FIXME: RVV didn't mention the alignment of bool, we uses
one byte align. */
if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_BOOL)
return 8;
widest_int min_size
= constant_lower_bound (wi::to_poly_widest (TYPE_SIZE (type)));
return wi::umin (min_size, 128).to_uhwi ();
}
/* Implement REGMODE_NATURAL_SIZE. */
poly_uint64
riscv_regmode_natural_size (machine_mode mode)
{
/* The natural size for RVV data modes is one RVV data vector,
and similarly for predicates. We can't independently modify
anything smaller than that. */
/* ??? For now, only do this for variable-width RVV registers.
Doing it for constant-sized registers breaks lower-subreg.c. */
if (!riscv_vector_chunks.is_constant () && riscv_v_ext_vector_mode_p (mode))
return BYTES_PER_RISCV_VECTOR;
return UNITS_PER_WORD;
}
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE riscv_option_override
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
#undef TARGET_SET_CURRENT_FUNCTION
#define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
#undef TARGET_REGISTER_MOVE_COST
#define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
#undef TARGET_MEMORY_MOVE_COST
#define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS riscv_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST riscv_address_cost
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START riscv_file_start
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
#undef TARGET_PRINT_OPERAND
#define TARGET_PRINT_OPERAND riscv_print_operand
#undef TARGET_PRINT_OPERAND_ADDRESS
#define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
#undef TARGET_FUNCTION_ARG
#define TARGET_FUNCTION_ARG riscv_function_arg
#undef TARGET_FUNCTION_ARG_ADVANCE
#define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
#undef TARGET_FUNCTION_ARG_BOUNDARY
#define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
/* The generic ELF target does not always have TLS support. */
#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#endif
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE riscv_can_eliminate
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
#undef TARGET_CLASS_MAX_NREGS
#define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
#undef TARGET_HAVE_SRODATA_SECTION
#define TARGET_HAVE_SRODATA_SECTION true
#undef TARGET_ASM_SELECT_SECTION
#define TARGET_ASM_SELECT_SECTION riscv_select_section
#undef TARGET_ASM_UNIQUE_SECTION
#define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
#undef TARGET_MIN_ANCHOR_OFFSET
#define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
#undef TARGET_MAX_ANCHOR_OFFSET
#define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
#undef TARGET_REGISTER_PRIORITY
#define TARGET_REGISTER_PRIORITY riscv_register_priority
#undef TARGET_CANNOT_COPY_INSN_P
#define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS riscv_init_builtins
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL riscv_builtin_decl
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN riscv_expand_builtin
#undef TARGET_HARD_REGNO_NREGS
#define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
#undef TARGET_MODES_TIEABLE_P
#define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
#undef TARGET_SLOW_UNALIGNED_ACCESS
#define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
#undef TARGET_SECONDARY_MEMORY_NEEDED
#define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
#undef TARGET_CAN_CHANGE_MODE_CLASS
#define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
#undef TARGET_CONSTANT_ALIGNMENT
#define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
#undef TARGET_MERGE_DECL_ATTRIBUTES
#define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
/* The low bit is ignored by jump instructions so is safe to use. */
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
#undef TARGET_NEW_ADDRESS_PROFITABLE_P
#define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
#undef TARGET_MANGLE_TYPE
#define TARGET_MANGLE_TYPE riscv_mangle_type
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P riscv_scalar_mode_supported_p
#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
#define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
riscv_libgcc_floating_mode_supported_p
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS riscv_init_libfuncs
#undef TARGET_C_EXCESS_PRECISION
#define TARGET_C_EXCESS_PRECISION riscv_excess_precision
#undef TARGET_FLOATN_MODE
#define TARGET_FLOATN_MODE riscv_floatn_mode
#undef TARGET_ASAN_SHADOW_OFFSET
#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
#ifdef TARGET_BIG_ENDIAN_DEFAULT
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
#endif
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p
#undef TARGET_VERIFY_TYPE_CONTEXT
#define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context
#undef TARGET_VECTOR_ALIGNMENT
#define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
|