1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501
6502
6503
6504
6505
6506
6507
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588
6589
6590
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
|
/* Subroutines for insn-output.c for Motorola 68000 family.
Copyright (C) 1987-2018 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "cfghooks.h"
#include "tree.h"
#include "stringpool.h"
#include "attribs.h"
#include "rtl.h"
#include "df.h"
#include "alias.h"
#include "fold-const.h"
#include "calls.h"
#include "stor-layout.h"
#include "varasm.h"
#include "regs.h"
#include "insn-config.h"
#include "conditions.h"
#include "output.h"
#include "insn-attr.h"
#include "recog.h"
#include "diagnostic-core.h"
#include "flags.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "memmodel.h"
#include "emit-rtl.h"
#include "stmt.h"
#include "expr.h"
#include "reload.h"
#include "tm_p.h"
#include "target.h"
#include "debug.h"
#include "cfgrtl.h"
#include "cfganal.h"
#include "lcm.h"
#include "cfgbuild.h"
#include "cfgcleanup.h"
/* ??? Need to add a dependency between m68k.o and sched-int.h. */
#include "sched-int.h"
#include "insn-codes.h"
#include "opts.h"
#include "optabs.h"
#include "builtins.h"
#include "rtl-iter.h"
/* This file should be included last. */
#include "target-def.h"
enum reg_class regno_reg_class[] =
{
DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
ADDR_REGS
};
/* The minimum number of integer registers that we want to save with the
movem instruction. Using two movel instructions instead of a single
moveml is about 15% faster for the 68020 and 68030 at no expense in
code size. */
#define MIN_MOVEM_REGS 3
/* The minimum number of floating point registers that we want to save
with the fmovem instruction. */
#define MIN_FMOVEM_REGS 1
/* Structure describing stack frame layout. */
struct m68k_frame
{
/* Stack pointer to frame pointer offset. */
HOST_WIDE_INT offset;
/* Offset of FPU registers. */
HOST_WIDE_INT foffset;
/* Frame size in bytes (rounded up). */
HOST_WIDE_INT size;
/* Data and address register. */
int reg_no;
unsigned int reg_mask;
/* FPU registers. */
int fpu_no;
unsigned int fpu_mask;
/* Offsets relative to ARG_POINTER. */
HOST_WIDE_INT frame_pointer_offset;
HOST_WIDE_INT stack_pointer_offset;
/* Function which the above information refers to. */
int funcdef_no;
};
/* Current frame information calculated by m68k_compute_frame_layout(). */
static struct m68k_frame current_frame;
/* Structure describing an m68k address.
If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
with null fields evaluating to 0. Here:
- BASE satisfies m68k_legitimate_base_reg_p
- INDEX satisfies m68k_legitimate_index_reg_p
- OFFSET satisfies m68k_legitimate_constant_address_p
INDEX is either HImode or SImode. The other fields are SImode.
If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
the address is (BASE)+. */
struct m68k_address {
enum rtx_code code;
rtx base;
rtx index;
rtx offset;
int scale;
};
static int m68k_sched_adjust_cost (rtx_insn *, int, rtx_insn *, int,
unsigned int);
static int m68k_sched_issue_rate (void);
static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int);
static void m68k_sched_md_init_global (FILE *, int, int);
static void m68k_sched_md_finish_global (FILE *, int);
static void m68k_sched_md_init (FILE *, int, int);
static void m68k_sched_dfa_pre_advance_cycle (void);
static void m68k_sched_dfa_post_advance_cycle (void);
static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
static bool m68k_can_eliminate (const int, const int);
static void m68k_conditional_register_usage (void);
static bool m68k_legitimate_address_p (machine_mode, rtx, bool);
static void m68k_option_override (void);
static void m68k_override_options_after_change (void);
static rtx find_addr_reg (rtx);
static const char *singlemove_string (rtx *);
static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree);
static rtx m68k_struct_value_rtx (tree, int);
static tree m68k_handle_fndecl_attribute (tree *node, tree name,
tree args, int flags,
bool *no_add_attrs);
static void m68k_compute_frame_layout (void);
static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
static bool m68k_ok_for_sibcall_p (tree, tree);
static bool m68k_tls_symbol_p (rtx);
static rtx m68k_legitimize_address (rtx, rtx, machine_mode);
static bool m68k_rtx_costs (rtx, machine_mode, int, int, int *, bool);
#if M68K_HONOR_TARGET_STRICT_ALIGNMENT
static bool m68k_return_in_memory (const_tree, const_tree);
#endif
static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
static void m68k_trampoline_init (rtx, tree, rtx);
static poly_int64 m68k_return_pops_args (tree, tree, poly_int64);
static rtx m68k_delegitimize_address (rtx);
static void m68k_function_arg_advance (cumulative_args_t, machine_mode,
const_tree, bool);
static rtx m68k_function_arg (cumulative_args_t, machine_mode,
const_tree, bool);
static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x);
static bool m68k_output_addr_const_extra (FILE *, rtx);
static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
static enum flt_eval_method
m68k_excess_precision (enum excess_precision_type);
static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode);
static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode);
static bool m68k_modes_tieable_p (machine_mode, machine_mode);
static machine_mode m68k_promote_function_mode (const_tree, machine_mode,
int *, const_tree, int);
/* Initialize the GCC target structure. */
#if INT_OP_GROUP == INT_OP_DOT_WORD
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
#endif
#if INT_OP_GROUP == INT_OP_NO_DOT
#undef TARGET_ASM_BYTE_OP
#define TARGET_ASM_BYTE_OP "\tbyte\t"
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
#endif
#if INT_OP_GROUP == INT_OP_DC
#undef TARGET_ASM_BYTE_OP
#define TARGET_ASM_BYTE_OP "\tdc.b\t"
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
#endif
#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
#undef TARGET_ASM_FILE_START_APP_OFF
#define TARGET_ASM_FILE_START_APP_OFF true
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
#undef TARGET_SCHED_VARIABLE_ISSUE
#define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
#undef TARGET_SCHED_INIT_GLOBAL
#define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
#undef TARGET_SCHED_FINISH_GLOBAL
#define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
#undef TARGET_SCHED_INIT
#define TARGET_SCHED_INIT m68k_sched_md_init
#undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
#define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
#undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
#define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
m68k_sched_first_cycle_multipass_dfa_lookahead
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE m68k_option_override
#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS m68k_rtx_costs
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
#if M68K_HONOR_TARGET_STRICT_ALIGNMENT
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
#endif
#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS (true)
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
#define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
#endif
#undef TARGET_LRA_P
#define TARGET_LRA_P hook_bool_void_false
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
#undef TARGET_CAN_ELIMINATE
#define TARGET_CAN_ELIMINATE m68k_can_eliminate
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
#undef TARGET_RETURN_POPS_ARGS
#define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
#undef TARGET_DELEGITIMIZE_ADDRESS
#define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
#undef TARGET_FUNCTION_ARG
#define TARGET_FUNCTION_ARG m68k_function_arg
#undef TARGET_FUNCTION_ARG_ADVANCE
#define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
#undef TARGET_C_EXCESS_PRECISION
#define TARGET_C_EXCESS_PRECISION m68k_excess_precision
/* The value stored by TAS. */
#undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
#define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
#undef TARGET_HARD_REGNO_NREGS
#define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
#undef TARGET_MODES_TIEABLE_P
#define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req,
affects_type_identity, handler, exclude } */
{ "interrupt", 0, 0, true, false, false, false,
m68k_handle_fndecl_attribute, NULL },
{ "interrupt_handler", 0, 0, true, false, false, false,
m68k_handle_fndecl_attribute, NULL },
{ "interrupt_thread", 0, 0, true, false, false, false,
m68k_handle_fndecl_attribute, NULL },
{ NULL, 0, 0, false, false, false, false, NULL, NULL }
};
struct gcc_target targetm = TARGET_INITIALIZER;
/* Base flags for 68k ISAs. */
#define FL_FOR_isa_00 FL_ISA_68000
#define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
/* FL_68881 controls the default setting of -m68881. gcc has traditionally
generated 68881 code for 68020 and 68030 targets unless explicitly told
not to. */
#define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
| FL_BITFIELD | FL_68881 | FL_CAS)
#define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
#define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
/* Base flags for ColdFire ISAs. */
#define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
#define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
/* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
#define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
/* ISA_C is not upwardly compatible with ISA_B. */
#define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
enum m68k_isa
{
/* Traditional 68000 instruction sets. */
isa_00,
isa_10,
isa_20,
isa_40,
isa_cpu32,
/* ColdFire instruction set variants. */
isa_a,
isa_aplus,
isa_b,
isa_c,
isa_max
};
/* Information about one of the -march, -mcpu or -mtune arguments. */
struct m68k_target_selection
{
/* The argument being described. */
const char *name;
/* For -mcpu, this is the device selected by the option.
For -mtune and -march, it is a representative device
for the microarchitecture or ISA respectively. */
enum target_device device;
/* The M68K_DEVICE fields associated with DEVICE. See the comment
in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
const char *family;
enum uarch_type microarch;
enum m68k_isa isa;
unsigned long flags;
};
/* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
static const struct m68k_target_selection all_devices[] =
{
#define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
{ NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
#include "m68k-devices.def"
#undef M68K_DEVICE
{ NULL, unk_device, NULL, unk_arch, isa_max, 0 }
};
/* A list of all ISAs, mapping each one to a representative device.
Used for -march selection. */
static const struct m68k_target_selection all_isas[] =
{
#define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
{ NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
#include "m68k-isas.def"
#undef M68K_ISA
{ NULL, unk_device, NULL, unk_arch, isa_max, 0 }
};
/* A list of all microarchitectures, mapping each one to a representative
device. Used for -mtune selection. */
static const struct m68k_target_selection all_microarchs[] =
{
#define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
{ NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
#include "m68k-microarchs.def"
#undef M68K_MICROARCH
{ NULL, unk_device, NULL, unk_arch, isa_max, 0 }
};
/* The entries associated with the -mcpu, -march and -mtune settings,
or null for options that have not been used. */
const struct m68k_target_selection *m68k_cpu_entry;
const struct m68k_target_selection *m68k_arch_entry;
const struct m68k_target_selection *m68k_tune_entry;
/* Which CPU we are generating code for. */
enum target_device m68k_cpu;
/* Which microarchitecture to tune for. */
enum uarch_type m68k_tune;
/* Which FPU to use. */
enum fpu_type m68k_fpu;
/* The set of FL_* flags that apply to the target processor. */
unsigned int m68k_cpu_flags;
/* The set of FL_* flags that apply to the processor to be tuned for. */
unsigned int m68k_tune_flags;
/* Asm templates for calling or jumping to an arbitrary symbolic address,
or NULL if such calls or jumps are not supported. The address is held
in operand 0. */
const char *m68k_symbolic_call;
const char *m68k_symbolic_jump;
/* Enum variable that corresponds to m68k_symbolic_call values. */
enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
/* Implement TARGET_OPTION_OVERRIDE. */
static void
m68k_option_override (void)
{
const struct m68k_target_selection *entry;
unsigned long target_mask;
if (global_options_set.x_m68k_arch_option)
m68k_arch_entry = &all_isas[m68k_arch_option];
if (global_options_set.x_m68k_cpu_option)
m68k_cpu_entry = &all_devices[(int) m68k_cpu_option];
if (global_options_set.x_m68k_tune_option)
m68k_tune_entry = &all_microarchs[(int) m68k_tune_option];
/* User can choose:
-mcpu=
-march=
-mtune=
-march=ARCH should generate code that runs any processor
implementing architecture ARCH. -mcpu=CPU should override -march
and should generate code that runs on processor CPU, making free
use of any instructions that CPU understands. -mtune=UARCH applies
on top of -mcpu or -march and optimizes the code for UARCH. It does
not change the target architecture. */
if (m68k_cpu_entry)
{
/* Complain if the -march setting is for a different microarchitecture,
or includes flags that the -mcpu setting doesn't. */
if (m68k_arch_entry
&& (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
|| (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
warning (0, "-mcpu=%s conflicts with -march=%s",
m68k_cpu_entry->name, m68k_arch_entry->name);
entry = m68k_cpu_entry;
}
else
entry = m68k_arch_entry;
if (!entry)
entry = all_devices + TARGET_CPU_DEFAULT;
m68k_cpu_flags = entry->flags;
/* Use the architecture setting to derive default values for
certain flags. */
target_mask = 0;
/* ColdFire is lenient about alignment. */
if (!TARGET_COLDFIRE)
target_mask |= MASK_STRICT_ALIGNMENT;
if ((m68k_cpu_flags & FL_BITFIELD) != 0)
target_mask |= MASK_BITFIELD;
if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
target_mask |= MASK_CF_HWDIV;
if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
target_mask |= MASK_HARD_FLOAT;
target_flags |= target_mask & ~target_flags_explicit;
/* Set the directly-usable versions of the -mcpu and -mtune settings. */
m68k_cpu = entry->device;
if (m68k_tune_entry)
{
m68k_tune = m68k_tune_entry->microarch;
m68k_tune_flags = m68k_tune_entry->flags;
}
#ifdef M68K_DEFAULT_TUNE
else if (!m68k_cpu_entry && !m68k_arch_entry)
{
enum target_device dev;
dev = all_microarchs[M68K_DEFAULT_TUNE].device;
m68k_tune_flags = all_devices[dev].flags;
}
#endif
else
{
m68k_tune = entry->microarch;
m68k_tune_flags = entry->flags;
}
/* Set the type of FPU. */
m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
: (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
: FPUTYPE_68881);
/* Sanity check to ensure that msep-data and mid-sahred-library are not
* both specified together. Doing so simply doesn't make sense.
*/
if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
error ("cannot specify both -msep-data and -mid-shared-library");
/* If we're generating code for a separate A5 relative data segment,
* we've got to enable -fPIC as well. This might be relaxable to
* -fpic but it hasn't been tested properly.
*/
if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
flag_pic = 2;
/* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
error if the target does not support them. */
if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
error ("-mpcrel -fPIC is not currently supported on selected cpu");
/* ??? A historic way of turning on pic, or is this intended to
be an embedded thing that doesn't have the same name binding
significance that it does on hosted ELF systems? */
if (TARGET_PCREL && flag_pic == 0)
flag_pic = 1;
if (!flag_pic)
{
m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
m68k_symbolic_jump = "jra %a0";
}
else if (TARGET_ID_SHARED_LIBRARY)
/* All addresses must be loaded from the GOT. */
;
else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
{
if (TARGET_PCREL)
m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
else
m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
if (TARGET_ISAC)
/* No unconditional long branch */;
else if (TARGET_PCREL)
m68k_symbolic_jump = "bra%.l %c0";
else
m68k_symbolic_jump = "bra%.l %p0";
/* Turn off function cse if we are doing PIC. We always want
function call to be done as `bsr foo@PLTPC'. */
/* ??? It's traditional to do this for -mpcrel too, but it isn't
clear how intentional that is. */
flag_no_function_cse = 1;
}
switch (m68k_symbolic_call_var)
{
case M68K_SYMBOLIC_CALL_JSR:
m68k_symbolic_call = "jsr %a0";
break;
case M68K_SYMBOLIC_CALL_BSR_C:
m68k_symbolic_call = "bsr%.l %c0";
break;
case M68K_SYMBOLIC_CALL_BSR_P:
m68k_symbolic_call = "bsr%.l %p0";
break;
case M68K_SYMBOLIC_CALL_NONE:
gcc_assert (m68k_symbolic_call == NULL);
break;
default:
gcc_unreachable ();
}
#ifndef ASM_OUTPUT_ALIGN_WITH_NOP
if (align_labels > 2)
{
warning (0, "-falign-labels=%d is not supported", align_labels);
align_labels = 0;
}
if (align_loops > 2)
{
warning (0, "-falign-loops=%d is not supported", align_loops);
align_loops = 0;
}
#endif
if ((opt_fstack_limit_symbol_arg != NULL || opt_fstack_limit_register_no >= 0)
&& !TARGET_68020)
{
warning (0, "-fstack-limit- options are not supported on this cpu");
opt_fstack_limit_symbol_arg = NULL;
opt_fstack_limit_register_no = -1;
}
SUBTARGET_OVERRIDE_OPTIONS;
/* Setup scheduling options. */
if (TUNE_CFV1)
m68k_sched_cpu = CPU_CFV1;
else if (TUNE_CFV2)
m68k_sched_cpu = CPU_CFV2;
else if (TUNE_CFV3)
m68k_sched_cpu = CPU_CFV3;
else if (TUNE_CFV4)
m68k_sched_cpu = CPU_CFV4;
else
{
m68k_sched_cpu = CPU_UNKNOWN;
flag_schedule_insns = 0;
flag_schedule_insns_after_reload = 0;
flag_modulo_sched = 0;
flag_live_range_shrinkage = 0;
}
if (m68k_sched_cpu != CPU_UNKNOWN)
{
if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
m68k_sched_mac = MAC_CF_EMAC;
else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
m68k_sched_mac = MAC_CF_MAC;
else
m68k_sched_mac = MAC_NO;
}
}
/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
static void
m68k_override_options_after_change (void)
{
if (m68k_sched_cpu == CPU_UNKNOWN)
{
flag_schedule_insns = 0;
flag_schedule_insns_after_reload = 0;
flag_modulo_sched = 0;
flag_live_range_shrinkage = 0;
}
}
/* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
given argument and NAME is the argument passed to -mcpu. Return NULL
if -mcpu was not passed. */
const char *
m68k_cpp_cpu_ident (const char *prefix)
{
if (!m68k_cpu_entry)
return NULL;
return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
}
/* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
given argument and NAME is the name of the representative device for
the -mcpu argument's family. Return NULL if -mcpu was not passed. */
const char *
m68k_cpp_cpu_family (const char *prefix)
{
if (!m68k_cpu_entry)
return NULL;
return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
}
/* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
"interrupt_handler" attribute and interrupt_thread if FUNC has an
"interrupt_thread" attribute. Otherwise, return
m68k_fk_normal_function. */
enum m68k_function_kind
m68k_get_function_kind (tree func)
{
tree a;
gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
if (a != NULL_TREE)
return m68k_fk_interrupt_handler;
a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
if (a != NULL_TREE)
return m68k_fk_interrupt_handler;
a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
if (a != NULL_TREE)
return m68k_fk_interrupt_thread;
return m68k_fk_normal_function;
}
/* Handle an attribute requiring a FUNCTION_DECL; arguments as in
struct attribute_spec.handler. */
static tree
m68k_handle_fndecl_attribute (tree *node, tree name,
tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED,
bool *no_add_attrs)
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
warning (OPT_Wattributes, "%qE attribute only applies to functions",
name);
*no_add_attrs = true;
}
if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
{
error ("multiple interrupt attributes not allowed");
*no_add_attrs = true;
}
if (!TARGET_FIDOA
&& !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
{
error ("interrupt_thread is available only on fido");
*no_add_attrs = true;
}
return NULL_TREE;
}
static void
m68k_compute_frame_layout (void)
{
int regno, saved;
unsigned int mask;
enum m68k_function_kind func_kind =
m68k_get_function_kind (current_function_decl);
bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
/* Only compute the frame once per function.
Don't cache information until reload has been completed. */
if (current_frame.funcdef_no == current_function_funcdef_no
&& reload_completed)
return;
current_frame.size = (get_frame_size () + 3) & -4;
mask = saved = 0;
/* Interrupt thread does not need to save any register. */
if (!interrupt_thread)
for (regno = 0; regno < 16; regno++)
if (m68k_save_reg (regno, interrupt_handler))
{
mask |= 1 << (regno - D0_REG);
saved++;
}
current_frame.offset = saved * 4;
current_frame.reg_no = saved;
current_frame.reg_mask = mask;
current_frame.foffset = 0;
mask = saved = 0;
if (TARGET_HARD_FLOAT)
{
/* Interrupt thread does not need to save any register. */
if (!interrupt_thread)
for (regno = 16; regno < 24; regno++)
if (m68k_save_reg (regno, interrupt_handler))
{
mask |= 1 << (regno - FP0_REG);
saved++;
}
current_frame.foffset = saved * TARGET_FP_REG_SIZE;
current_frame.offset += current_frame.foffset;
}
current_frame.fpu_no = saved;
current_frame.fpu_mask = mask;
/* Remember what function this frame refers to. */
current_frame.funcdef_no = current_function_funcdef_no;
}
/* Worker function for TARGET_CAN_ELIMINATE. */
bool
m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
{
return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
}
HOST_WIDE_INT
m68k_initial_elimination_offset (int from, int to)
{
int argptr_offset;
/* The arg pointer points 8 bytes before the start of the arguments,
as defined by FIRST_PARM_OFFSET. This makes it coincident with the
frame pointer in most frames. */
argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
return argptr_offset;
m68k_compute_frame_layout ();
gcc_assert (to == STACK_POINTER_REGNUM);
switch (from)
{
case ARG_POINTER_REGNUM:
return current_frame.offset + current_frame.size - argptr_offset;
case FRAME_POINTER_REGNUM:
return current_frame.offset + current_frame.size;
default:
gcc_unreachable ();
}
}
/* Refer to the array `regs_ever_live' to determine which registers
to save; `regs_ever_live[I]' is nonzero if register number I
is ever used in the function. This function is responsible for
knowing which registers should not be saved even if used.
Return true if we need to save REGNO. */
static bool
m68k_save_reg (unsigned int regno, bool interrupt_handler)
{
if (flag_pic && regno == PIC_REG)
{
if (crtl->saves_all_registers)
return true;
if (crtl->uses_pic_offset_table)
return true;
/* Reload may introduce constant pool references into a function
that thitherto didn't need a PIC register. Note that the test
above will not catch that case because we will only set
crtl->uses_pic_offset_table when emitting
the address reloads. */
if (crtl->uses_const_pool)
return true;
}
if (crtl->calls_eh_return)
{
unsigned int i;
for (i = 0; ; i++)
{
unsigned int test = EH_RETURN_DATA_REGNO (i);
if (test == INVALID_REGNUM)
break;
if (test == regno)
return true;
}
}
/* Fixed regs we never touch. */
if (fixed_regs[regno])
return false;
/* The frame pointer (if it is such) is handled specially. */
if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
return false;
/* Interrupt handlers must also save call_used_regs
if they are live or when calling nested functions. */
if (interrupt_handler)
{
if (df_regs_ever_live_p (regno))
return true;
if (!crtl->is_leaf && call_used_regs[regno])
return true;
}
/* Never need to save registers that aren't touched. */
if (!df_regs_ever_live_p (regno))
return false;
/* Otherwise save everything that isn't call-clobbered. */
return !call_used_regs[regno];
}
/* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
the lowest memory address. COUNT is the number of registers to be
moved, with register REGNO + I being moved if bit I of MASK is set.
STORE_P specifies the direction of the move and ADJUST_STACK_P says
whether or not this is pre-decrement (if STORE_P) or post-increment
(if !STORE_P) operation. */
static rtx_insn *
m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
unsigned int count, unsigned int regno,
unsigned int mask, bool store_p, bool adjust_stack_p)
{
int i;
rtx body, addr, src, operands[2];
machine_mode mode;
body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
mode = reg_raw_mode[regno];
i = 0;
if (adjust_stack_p)
{
src = plus_constant (Pmode, base,
(count
* GET_MODE_SIZE (mode)
* (HOST_WIDE_INT) (store_p ? -1 : 1)));
XVECEXP (body, 0, i++) = gen_rtx_SET (base, src);
}
for (; mask != 0; mask >>= 1, regno++)
if (mask & 1)
{
addr = plus_constant (Pmode, base, offset);
operands[!store_p] = gen_frame_mem (mode, addr);
operands[store_p] = gen_rtx_REG (mode, regno);
XVECEXP (body, 0, i++)
= gen_rtx_SET (operands[0], operands[1]);
offset += GET_MODE_SIZE (mode);
}
gcc_assert (i == XVECLEN (body, 0));
return emit_insn (body);
}
/* Make INSN a frame-related instruction. */
static void
m68k_set_frame_related (rtx_insn *insn)
{
rtx body;
int i;
RTX_FRAME_RELATED_P (insn) = 1;
body = PATTERN (insn);
if (GET_CODE (body) == PARALLEL)
for (i = 0; i < XVECLEN (body, 0); i++)
RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
}
/* Emit RTL for the "prologue" define_expand. */
void
m68k_expand_prologue (void)
{
HOST_WIDE_INT fsize_with_regs;
rtx limit, src, dest;
m68k_compute_frame_layout ();
if (flag_stack_usage_info)
current_function_static_stack_size
= current_frame.size + current_frame.offset;
/* If the stack limit is a symbol, we can check it here,
before actually allocating the space. */
if (crtl->limit_stack
&& GET_CODE (stack_limit_rtx) == SYMBOL_REF)
{
limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4);
if (!m68k_legitimate_constant_p (Pmode, limit))
{
emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
limit = gen_rtx_REG (Pmode, D0_REG);
}
emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode,
stack_pointer_rtx, limit),
stack_pointer_rtx, limit,
const1_rtx));
}
fsize_with_regs = current_frame.size;
if (TARGET_COLDFIRE)
{
/* ColdFire's move multiple instructions do not allow pre-decrement
addressing. Add the size of movem saves to the initial stack
allocation instead. */
if (current_frame.reg_no >= MIN_MOVEM_REGS)
fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
}
if (frame_pointer_needed)
{
if (fsize_with_regs == 0 && TUNE_68040)
{
/* On the 68040, two separate moves are faster than link.w 0. */
dest = gen_frame_mem (Pmode,
gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
stack_pointer_rtx));
}
else if (fsize_with_regs < 0x8000 || TARGET_68020)
m68k_set_frame_related
(emit_insn (gen_link (frame_pointer_rtx,
GEN_INT (-4 - fsize_with_regs))));
else
{
m68k_set_frame_related
(emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
m68k_set_frame_related
(emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-fsize_with_regs))));
}
/* If the frame pointer is needed, emit a special barrier that
will prevent the scheduler from moving stores to the frame
before the stack adjustment. */
emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx));
}
else if (fsize_with_regs != 0)
m68k_set_frame_related
(emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-fsize_with_regs))));
if (current_frame.fpu_mask)
{
gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
if (TARGET_68881)
m68k_set_frame_related
(m68k_emit_movem (stack_pointer_rtx,
current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, true, true));
else
{
int offset;
/* If we're using moveml to save the integer registers,
the stack pointer will point to the bottom of the moveml
save area. Find the stack offset of the first FP register. */
if (current_frame.reg_no < MIN_MOVEM_REGS)
offset = 0;
else
offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
m68k_set_frame_related
(m68k_emit_movem (stack_pointer_rtx, offset,
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, true, false));
}
}
/* If the stack limit is not a symbol, check it here.
This has the disadvantage that it may be too late... */
if (crtl->limit_stack)
{
if (REG_P (stack_limit_rtx))
emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx,
stack_limit_rtx),
stack_pointer_rtx, stack_limit_rtx,
const1_rtx));
else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
warning (0, "stack limit expression is not supported");
}
if (current_frame.reg_no < MIN_MOVEM_REGS)
{
/* Store each register separately in the same order moveml does. */
int i;
for (i = 16; i-- > 0; )
if (current_frame.reg_mask & (1 << i))
{
src = gen_rtx_REG (SImode, D0_REG + i);
dest = gen_frame_mem (SImode,
gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
}
}
else
{
if (TARGET_COLDFIRE)
/* The required register save space has already been allocated.
The first register should be stored at (%sp). */
m68k_set_frame_related
(m68k_emit_movem (stack_pointer_rtx, 0,
current_frame.reg_no, D0_REG,
current_frame.reg_mask, true, false));
else
m68k_set_frame_related
(m68k_emit_movem (stack_pointer_rtx,
current_frame.reg_no * -GET_MODE_SIZE (SImode),
current_frame.reg_no, D0_REG,
current_frame.reg_mask, true, true));
}
if (!TARGET_SEP_DATA
&& crtl->uses_pic_offset_table)
emit_insn (gen_load_got (pic_offset_table_rtx));
}
/* Return true if a simple (return) instruction is sufficient for this
instruction (i.e. if no epilogue is needed). */
bool
m68k_use_return_insn (void)
{
if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
return false;
m68k_compute_frame_layout ();
return current_frame.offset == 0;
}
/* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
SIBCALL_P says which.
The function epilogue should not depend on the current stack pointer!
It should use the frame pointer only, if there is a frame pointer.
This is mandatory because of alloca; we also take advantage of it to
omit stack adjustments before returning. */
void
m68k_expand_epilogue (bool sibcall_p)
{
HOST_WIDE_INT fsize, fsize_with_regs;
bool big, restore_from_sp;
m68k_compute_frame_layout ();
fsize = current_frame.size;
big = false;
restore_from_sp = false;
/* FIXME : crtl->is_leaf below is too strong.
What we really need to know there is if there could be pending
stack adjustment needed at that point. */
restore_from_sp = (!frame_pointer_needed
|| (!cfun->calls_alloca && crtl->is_leaf));
/* fsize_with_regs is the size we need to adjust the sp when
popping the frame. */
fsize_with_regs = fsize;
if (TARGET_COLDFIRE && restore_from_sp)
{
/* ColdFire's move multiple instructions do not allow post-increment
addressing. Add the size of movem loads to the final deallocation
instead. */
if (current_frame.reg_no >= MIN_MOVEM_REGS)
fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
}
if (current_frame.offset + fsize >= 0x8000
&& !restore_from_sp
&& (current_frame.reg_mask || current_frame.fpu_mask))
{
if (TARGET_COLDFIRE
&& (current_frame.reg_no >= MIN_MOVEM_REGS
|| current_frame.fpu_no >= MIN_FMOVEM_REGS))
{
/* ColdFire's move multiple instructions do not support the
(d8,Ax,Xi) addressing mode, so we're as well using a normal
stack-based restore. */
emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
GEN_INT (-(current_frame.offset + fsize)));
emit_insn (gen_blockage ());
emit_insn (gen_addsi3 (stack_pointer_rtx,
gen_rtx_REG (Pmode, A1_REG),
frame_pointer_rtx));
restore_from_sp = true;
}
else
{
emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
fsize = 0;
big = true;
}
}
if (current_frame.reg_no < MIN_MOVEM_REGS)
{
/* Restore each register separately in the same order moveml does. */
int i;
HOST_WIDE_INT offset;
offset = current_frame.offset + fsize;
for (i = 0; i < 16; i++)
if (current_frame.reg_mask & (1 << i))
{
rtx addr;
if (big)
{
/* Generate the address -OFFSET(%fp,%a1.l). */
addr = gen_rtx_REG (Pmode, A1_REG);
addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
addr = plus_constant (Pmode, addr, -offset);
}
else if (restore_from_sp)
addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
else
addr = plus_constant (Pmode, frame_pointer_rtx, -offset);
emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
gen_frame_mem (SImode, addr));
offset -= GET_MODE_SIZE (SImode);
}
}
else if (current_frame.reg_mask)
{
if (big)
m68k_emit_movem (gen_rtx_PLUS (Pmode,
gen_rtx_REG (Pmode, A1_REG),
frame_pointer_rtx),
-(current_frame.offset + fsize),
current_frame.reg_no, D0_REG,
current_frame.reg_mask, false, false);
else if (restore_from_sp)
m68k_emit_movem (stack_pointer_rtx, 0,
current_frame.reg_no, D0_REG,
current_frame.reg_mask, false,
!TARGET_COLDFIRE);
else
m68k_emit_movem (frame_pointer_rtx,
-(current_frame.offset + fsize),
current_frame.reg_no, D0_REG,
current_frame.reg_mask, false, false);
}
if (current_frame.fpu_no > 0)
{
if (big)
m68k_emit_movem (gen_rtx_PLUS (Pmode,
gen_rtx_REG (Pmode, A1_REG),
frame_pointer_rtx),
-(current_frame.foffset + fsize),
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, false, false);
else if (restore_from_sp)
{
if (TARGET_COLDFIRE)
{
int offset;
/* If we used moveml to restore the integer registers, the
stack pointer will still point to the bottom of the moveml
save area. Find the stack offset of the first FP
register. */
if (current_frame.reg_no < MIN_MOVEM_REGS)
offset = 0;
else
offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
m68k_emit_movem (stack_pointer_rtx, offset,
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, false, false);
}
else
m68k_emit_movem (stack_pointer_rtx, 0,
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, false, true);
}
else
m68k_emit_movem (frame_pointer_rtx,
-(current_frame.foffset + fsize),
current_frame.fpu_no, FP0_REG,
current_frame.fpu_mask, false, false);
}
emit_insn (gen_blockage ());
if (frame_pointer_needed)
emit_insn (gen_unlink (frame_pointer_rtx));
else if (fsize_with_regs)
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (fsize_with_regs)));
if (crtl->calls_eh_return)
emit_insn (gen_addsi3 (stack_pointer_rtx,
stack_pointer_rtx,
EH_RETURN_STACKADJ_RTX));
if (!sibcall_p)
emit_jump_insn (ret_rtx);
}
/* Return true if X is a valid comparison operator for the dbcc
instruction.
Note it rejects floating point comparison operators.
(In the future we could use Fdbcc).
It also rejects some comparisons when CC_NO_OVERFLOW is set. */
int
valid_dbcc_comparison_p_2 (rtx x, machine_mode mode ATTRIBUTE_UNUSED)
{
switch (GET_CODE (x))
{
case EQ: case NE: case GTU: case LTU:
case GEU: case LEU:
return 1;
/* Reject some when CC_NO_OVERFLOW is set. This may be over
conservative */
case GT: case LT: case GE: case LE:
return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
default:
return 0;
}
}
/* Return nonzero if flags are currently in the 68881 flag register. */
int
flags_in_68881 (void)
{
/* We could add support for these in the future */
return cc_status.flags & CC_IN_68881;
}
/* Return true if PARALLEL contains register REGNO. */
static bool
m68k_reg_present_p (const_rtx parallel, unsigned int regno)
{
int i;
if (REG_P (parallel) && REGNO (parallel) == regno)
return true;
if (GET_CODE (parallel) != PARALLEL)
return false;
for (i = 0; i < XVECLEN (parallel, 0); ++i)
{
const_rtx x;
x = XEXP (XVECEXP (parallel, 0, i), 0);
if (REG_P (x) && REGNO (x) == regno)
return true;
}
return false;
}
/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
static bool
m68k_ok_for_sibcall_p (tree decl, tree exp)
{
enum m68k_function_kind kind;
/* We cannot use sibcalls for nested functions because we use the
static chain register for indirect calls. */
if (CALL_EXPR_STATIC_CHAIN (exp))
return false;
if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
{
/* Check that the return value locations are the same. For
example that we aren't returning a value from the sibling in
a D0 register but then need to transfer it to a A0 register. */
rtx cfun_value;
rtx call_value;
cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)),
cfun->decl);
call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl);
/* Check that the values are equal or that the result the callee
function returns is superset of what the current function returns. */
if (!(rtx_equal_p (cfun_value, call_value)
|| (REG_P (cfun_value)
&& m68k_reg_present_p (call_value, REGNO (cfun_value)))))
return false;
}
kind = m68k_get_function_kind (current_function_decl);
if (kind == m68k_fk_normal_function)
/* We can always sibcall from a normal function, because it's
undefined if it is calling an interrupt function. */
return true;
/* Otherwise we can only sibcall if the function kind is known to be
the same. */
if (decl && m68k_get_function_kind (decl) == kind)
return true;
return false;
}
/* On the m68k all args are always pushed. */
static rtx
m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED,
machine_mode mode ATTRIBUTE_UNUSED,
const_tree type ATTRIBUTE_UNUSED,
bool named ATTRIBUTE_UNUSED)
{
return NULL_RTX;
}
static void
m68k_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
const_tree type, bool named ATTRIBUTE_UNUSED)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
*cum += (mode != BLKmode
? (GET_MODE_SIZE (mode) + 3) & ~3
: (int_size_in_bytes (type) + 3) & ~3);
}
/* Convert X to a legitimate function call memory reference and return the
result. */
rtx
m68k_legitimize_call_address (rtx x)
{
gcc_assert (MEM_P (x));
if (call_operand (XEXP (x, 0), VOIDmode))
return x;
return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
}
/* Likewise for sibling calls. */
rtx
m68k_legitimize_sibcall_address (rtx x)
{
gcc_assert (MEM_P (x));
if (sibcall_operand (XEXP (x, 0), VOIDmode))
return x;
emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
}
/* Convert X to a legitimate address and return it if successful. Otherwise
return X.
For the 68000, we handle X+REG by loading X into a register R and
using R+REG. R will go in an address reg and indexing will be used.
However, if REG is a broken-out memory address or multiplication,
nothing needs to be done because REG can certainly go in an address reg. */
static rtx
m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
{
if (m68k_tls_symbol_p (x))
return m68k_legitimize_tls_address (x);
if (GET_CODE (x) == PLUS)
{
int ch = (x) != (oldx);
int copied = 0;
#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
if (GET_CODE (XEXP (x, 0)) == MULT)
{
COPY_ONCE (x);
XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
}
if (GET_CODE (XEXP (x, 1)) == MULT)
{
COPY_ONCE (x);
XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
}
if (ch)
{
if (GET_CODE (XEXP (x, 1)) == REG
&& GET_CODE (XEXP (x, 0)) == REG)
{
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
{
COPY_ONCE (x);
x = force_operand (x, 0);
}
return x;
}
if (memory_address_p (mode, x))
return x;
}
if (GET_CODE (XEXP (x, 0)) == REG
|| (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
&& GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 1), 0);
emit_move_insn (temp, val);
COPY_ONCE (x);
XEXP (x, 1) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
&& GET_CODE (XEXP (x, 0)) == REG)
x = force_operand (x, 0);
}
else if (GET_CODE (XEXP (x, 1)) == REG
|| (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
&& GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
&& GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 0), 0);
emit_move_insn (temp, val);
COPY_ONCE (x);
XEXP (x, 0) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
&& GET_CODE (XEXP (x, 1)) == REG)
x = force_operand (x, 0);
}
}
return x;
}
/* Output a dbCC; jCC sequence. Note we do not handle the
floating point version of this sequence (Fdbcc). We also
do not handle alternative conditions when CC_NO_OVERFLOW is
set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
kick those out before we get here. */
void
output_dbcc_and_branch (rtx *operands)
{
switch (GET_CODE (operands[3]))
{
case EQ:
output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
break;
case NE:
output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
break;
case GT:
output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
break;
case GTU:
output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
break;
case LT:
output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
break;
case LTU:
output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
break;
case GE:
output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
break;
case GEU:
output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
break;
case LE:
output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
break;
case LEU:
output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
break;
default:
gcc_unreachable ();
}
/* If the decrement is to be done in SImode, then we have
to compensate for the fact that dbcc decrements in HImode. */
switch (GET_MODE (operands[0]))
{
case E_SImode:
output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
break;
case E_HImode:
break;
default:
gcc_unreachable ();
}
}
const char *
output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
{
rtx loperands[7];
enum rtx_code op_code = GET_CODE (op);
/* This does not produce a useful cc. */
CC_STATUS_INIT;
/* The m68k cmp.l instruction requires operand1 to be a reg as used
below. Swap the operands and change the op if these requirements
are not fulfilled. */
if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
{
rtx tmp = operand1;
operand1 = operand2;
operand2 = tmp;
op_code = swap_condition (op_code);
}
loperands[0] = operand1;
if (GET_CODE (operand1) == REG)
loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
else
loperands[1] = adjust_address (operand1, SImode, 4);
if (operand2 != const0_rtx)
{
loperands[2] = operand2;
if (GET_CODE (operand2) == REG)
loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
else
loperands[3] = adjust_address (operand2, SImode, 4);
}
loperands[4] = gen_label_rtx ();
if (operand2 != const0_rtx)
output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
else
{
if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
output_asm_insn ("tst%.l %0", loperands);
else
output_asm_insn ("cmp%.w #0,%0", loperands);
output_asm_insn ("jne %l4", loperands);
if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
output_asm_insn ("tst%.l %1", loperands);
else
output_asm_insn ("cmp%.w #0,%1", loperands);
}
loperands[5] = dest;
switch (op_code)
{
case EQ:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("seq %5", loperands);
break;
case NE:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("sne %5", loperands);
break;
case GT:
loperands[6] = gen_label_rtx ();
output_asm_insn ("shi %5\n\tjra %l6", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("sgt %5", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[6]));
break;
case GTU:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("shi %5", loperands);
break;
case LT:
loperands[6] = gen_label_rtx ();
output_asm_insn ("scs %5\n\tjra %l6", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("slt %5", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[6]));
break;
case LTU:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("scs %5", loperands);
break;
case GE:
loperands[6] = gen_label_rtx ();
output_asm_insn ("scc %5\n\tjra %l6", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("sge %5", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[6]));
break;
case GEU:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("scc %5", loperands);
break;
case LE:
loperands[6] = gen_label_rtx ();
output_asm_insn ("sls %5\n\tjra %l6", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("sle %5", loperands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[6]));
break;
case LEU:
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (loperands[4]));
output_asm_insn ("sls %5", loperands);
break;
default:
gcc_unreachable ();
}
return "";
}
const char *
output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos)
{
operands[0] = countop;
operands[1] = dataop;
if (GET_CODE (countop) == CONST_INT)
{
register int count = INTVAL (countop);
/* If COUNT is bigger than size of storage unit in use,
advance to the containing unit of same size. */
if (count > signpos)
{
int offset = (count & ~signpos) / 8;
count = count & signpos;
operands[1] = dataop = adjust_address (dataop, QImode, offset);
}
if (count == signpos)
cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
else
cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
/* These three statements used to use next_insns_test_no...
but it appears that this should do the same job. */
if (count == 31
&& next_insn_tests_no_inequality (insn))
return "tst%.l %1";
if (count == 15
&& next_insn_tests_no_inequality (insn))
return "tst%.w %1";
if (count == 7
&& next_insn_tests_no_inequality (insn))
return "tst%.b %1";
/* Try to use `movew to ccr' followed by the appropriate branch insn.
On some m68k variants unfortunately that's slower than btst.
On 68000 and higher, that should also work for all HImode operands. */
if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
{
if (count == 3 && DATA_REG_P (operands[1])
&& next_insn_tests_no_inequality (insn))
{
cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
return "move%.w %1,%%ccr";
}
if (count == 2 && DATA_REG_P (operands[1])
&& next_insn_tests_no_inequality (insn))
{
cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
return "move%.w %1,%%ccr";
}
/* count == 1 followed by bvc/bvs and
count == 0 followed by bcc/bcs are also possible, but need
m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
}
cc_status.flags = CC_NOT_NEGATIVE;
}
return "btst %0,%1";
}
/* Return true if X is a legitimate base register. STRICT_P says
whether we need strict checking. */
bool
m68k_legitimate_base_reg_p (rtx x, bool strict_p)
{
/* Allow SUBREG everywhere we allow REG. This results in better code. */
if (!strict_p && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
return (REG_P (x)
&& (strict_p
? REGNO_OK_FOR_BASE_P (REGNO (x))
: REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
}
/* Return true if X is a legitimate index register. STRICT_P says
whether we need strict checking. */
bool
m68k_legitimate_index_reg_p (rtx x, bool strict_p)
{
if (!strict_p && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
return (REG_P (x)
&& (strict_p
? REGNO_OK_FOR_INDEX_P (REGNO (x))
: REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
}
/* Return true if X is a legitimate index expression for a (d8,An,Xn) or
(bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
ADDRESS if so. STRICT_P says whether we need strict checking. */
static bool
m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
{
int scale;
/* Check for a scale factor. */
scale = 1;
if ((TARGET_68020 || TARGET_COLDFIRE)
&& GET_CODE (x) == MULT
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& (INTVAL (XEXP (x, 1)) == 2
|| INTVAL (XEXP (x, 1)) == 4
|| (INTVAL (XEXP (x, 1)) == 8
&& (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
{
scale = INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
}
/* Check for a word extension. */
if (!TARGET_COLDFIRE
&& GET_CODE (x) == SIGN_EXTEND
&& GET_MODE (XEXP (x, 0)) == HImode)
x = XEXP (x, 0);
if (m68k_legitimate_index_reg_p (x, strict_p))
{
address->scale = scale;
address->index = x;
return true;
}
return false;
}
/* Return true if X is an illegitimate symbolic constant. */
bool
m68k_illegitimate_symbolic_constant_p (rtx x)
{
rtx base, offset;
if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
{
split_const (x, &base, &offset);
if (GET_CODE (base) == SYMBOL_REF
&& !offset_within_block_p (base, INTVAL (offset)))
return true;
}
return m68k_tls_reference_p (x, false);
}
/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
static bool
m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
return m68k_illegitimate_symbolic_constant_p (x);
}
/* Return true if X is a legitimate constant address that can reach
bytes in the range [X, X + REACH). STRICT_P says whether we need
strict checking. */
static bool
m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
{
rtx base, offset;
if (!CONSTANT_ADDRESS_P (x))
return false;
if (flag_pic
&& !(strict_p && TARGET_PCREL)
&& symbolic_operand (x, VOIDmode))
return false;
if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
{
split_const (x, &base, &offset);
if (GET_CODE (base) == SYMBOL_REF
&& !offset_within_block_p (base, INTVAL (offset) + reach - 1))
return false;
}
return !m68k_tls_reference_p (x, false);
}
/* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
labels will become jump tables. */
static bool
m68k_jump_table_ref_p (rtx x)
{
if (GET_CODE (x) != LABEL_REF)
return false;
rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0));
if (!NEXT_INSN (insn) && !PREV_INSN (insn))
return true;
insn = next_nonnote_insn (insn);
return insn && JUMP_TABLE_DATA_P (insn);
}
/* Return true if X is a legitimate address for values of mode MODE.
STRICT_P says whether strict checking is needed. If the address
is valid, describe its components in *ADDRESS. */
static bool
m68k_decompose_address (machine_mode mode, rtx x,
bool strict_p, struct m68k_address *address)
{
unsigned int reach;
memset (address, 0, sizeof (*address));
if (mode == BLKmode)
reach = 1;
else
reach = GET_MODE_SIZE (mode);
/* Check for (An) (mode 2). */
if (m68k_legitimate_base_reg_p (x, strict_p))
{
address->base = x;
return true;
}
/* Check for -(An) and (An)+ (modes 3 and 4). */
if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
&& m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
{
address->code = GET_CODE (x);
address->base = XEXP (x, 0);
return true;
}
/* Check for (d16,An) (mode 5). */
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
&& m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
{
address->base = XEXP (x, 0);
address->offset = XEXP (x, 1);
return true;
}
/* Check for GOT loads. These are (bd,An,Xn) addresses if
TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
addresses. */
if (GET_CODE (x) == PLUS
&& XEXP (x, 0) == pic_offset_table_rtx)
{
/* As we are processing a PLUS, do not unwrap RELOC32 symbols --
they are invalid in this context. */
if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
{
address->base = XEXP (x, 0);
address->offset = XEXP (x, 1);
return true;
}
}
/* The ColdFire FPU only accepts addressing modes 2-5. */
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
return false;
/* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
All these modes are variations of mode 7. */
if (m68k_legitimate_constant_address_p (x, reach, strict_p))
{
address->offset = x;
return true;
}
/* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
tablejumps.
??? do_tablejump creates these addresses before placing the target
label, so we have to assume that unplaced labels are jump table
references. It seems unlikely that we would ever generate indexed
accesses to unplaced labels in other cases. */
if (GET_CODE (x) == PLUS
&& m68k_jump_table_ref_p (XEXP (x, 1))
&& m68k_decompose_index (XEXP (x, 0), strict_p, address))
{
address->offset = XEXP (x, 1);
return true;
}
/* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
(bd,An,Xn.SIZE*SCALE) addresses. */
if (TARGET_68020)
{
/* Check for a nonzero base displacement. */
if (GET_CODE (x) == PLUS
&& m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
{
address->offset = XEXP (x, 1);
x = XEXP (x, 0);
}
/* Check for a suppressed index register. */
if (m68k_legitimate_base_reg_p (x, strict_p))
{
address->base = x;
return true;
}
/* Check for a suppressed base register. Do not allow this case
for non-symbolic offsets as it effectively gives gcc freedom
to treat data registers as base registers, which can generate
worse code. */
if (address->offset
&& symbolic_operand (address->offset, VOIDmode)
&& m68k_decompose_index (x, strict_p, address))
return true;
}
else
{
/* Check for a nonzero base displacement. */
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
{
address->offset = XEXP (x, 1);
x = XEXP (x, 0);
}
}
/* We now expect the sum of a base and an index. */
if (GET_CODE (x) == PLUS)
{
if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
&& m68k_decompose_index (XEXP (x, 1), strict_p, address))
{
address->base = XEXP (x, 0);
return true;
}
if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
&& m68k_decompose_index (XEXP (x, 0), strict_p, address))
{
address->base = XEXP (x, 1);
return true;
}
}
return false;
}
/* Return true if X is a legitimate address for values of mode MODE.
STRICT_P says whether strict checking is needed. */
bool
m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
{
struct m68k_address address;
return m68k_decompose_address (mode, x, strict_p, &address);
}
/* Return true if X is a memory, describing its address in ADDRESS if so.
Apply strict checking if called during or after reload. */
static bool
m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
{
return (MEM_P (x)
&& m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
reload_in_progress || reload_completed,
address));
}
/* Implement TARGET_LEGITIMATE_CONSTANT_P. */
bool
m68k_legitimate_constant_p (machine_mode mode, rtx x)
{
return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x);
}
/* Return true if X matches the 'Q' constraint. It must be a memory
with a base address and no constant offset or index. */
bool
m68k_matches_q_p (rtx x)
{
struct m68k_address address;
return (m68k_legitimate_mem_p (x, &address)
&& address.code == UNKNOWN
&& address.base
&& !address.offset
&& !address.index);
}
/* Return true if X matches the 'U' constraint. It must be a base address
with a constant offset and no index. */
bool
m68k_matches_u_p (rtx x)
{
struct m68k_address address;
return (m68k_legitimate_mem_p (x, &address)
&& address.code == UNKNOWN
&& address.base
&& address.offset
&& !address.index);
}
/* Return GOT pointer. */
static rtx
m68k_get_gp (void)
{
if (pic_offset_table_rtx == NULL_RTX)
pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
crtl->uses_pic_offset_table = 1;
return pic_offset_table_rtx;
}
/* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
wrappers. */
enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
RELOC_TLSIE, RELOC_TLSLE };
#define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
/* Wrap symbol X into unspec representing relocation RELOC.
BASE_REG - register that should be added to the result.
TEMP_REG - if non-null, temporary register. */
static rtx
m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
{
bool use_x_p;
use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
if (TARGET_COLDFIRE && use_x_p)
/* When compiling with -mx{got, tls} switch the code will look like this:
move.l <X>@<RELOC>,<TEMP_REG>
add.l <BASE_REG>,<TEMP_REG> */
{
/* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
to put @RELOC after reference. */
x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
UNSPEC_RELOC32);
x = gen_rtx_CONST (Pmode, x);
if (temp_reg == NULL)
{
gcc_assert (can_create_pseudo_p ());
temp_reg = gen_reg_rtx (Pmode);
}
emit_move_insn (temp_reg, x);
emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
x = temp_reg;
}
else
{
x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
UNSPEC_RELOC16);
x = gen_rtx_CONST (Pmode, x);
x = gen_rtx_PLUS (Pmode, base_reg, x);
}
return x;
}
/* Helper for m68k_unwrap_symbol.
Also, if unwrapping was successful (that is if (ORIG != <return value>)),
sets *RELOC_PTR to relocation type for the symbol. */
static rtx
m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
enum m68k_reloc *reloc_ptr)
{
if (GET_CODE (orig) == CONST)
{
rtx x;
enum m68k_reloc dummy;
x = XEXP (orig, 0);
if (reloc_ptr == NULL)
reloc_ptr = &dummy;
/* Handle an addend. */
if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
&& CONST_INT_P (XEXP (x, 1)))
x = XEXP (x, 0);
if (GET_CODE (x) == UNSPEC)
{
switch (XINT (x, 1))
{
case UNSPEC_RELOC16:
orig = XVECEXP (x, 0, 0);
*reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
break;
case UNSPEC_RELOC32:
if (unwrap_reloc32_p)
{
orig = XVECEXP (x, 0, 0);
*reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
}
break;
default:
break;
}
}
}
return orig;
}
/* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
UNSPEC_RELOC32 wrappers. */
rtx
m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
{
return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
}
/* Prescan insn before outputing assembler for it. */
void
m68k_final_prescan_insn (rtx_insn *insn ATTRIBUTE_UNUSED,
rtx *operands, int n_operands)
{
int i;
/* Combine and, possibly, other optimizations may do good job
converting
(const (unspec [(symbol)]))
into
(const (plus (unspec [(symbol)])
(const_int N))).
The problem with this is emitting @TLS or @GOT decorations.
The decoration is emitted when processing (unspec), so the
result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
It seems that the easiest solution to this is to convert such
operands to
(const (unspec [(plus (symbol)
(const_int N))])).
Note, that the top level of operand remains intact, so we don't have
to patch up anything outside of the operand. */
subrtx_var_iterator::array_type array;
for (i = 0; i < n_operands; ++i)
{
rtx op;
op = operands[i];
FOR_EACH_SUBRTX_VAR (iter, array, op, ALL)
{
rtx x = *iter;
if (m68k_unwrap_symbol (x, true) != x)
{
rtx plus;
gcc_assert (GET_CODE (x) == CONST);
plus = XEXP (x, 0);
if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
{
rtx unspec;
rtx addend;
unspec = XEXP (plus, 0);
gcc_assert (GET_CODE (unspec) == UNSPEC);
addend = XEXP (plus, 1);
gcc_assert (CONST_INT_P (addend));
/* We now have all the pieces, rearrange them. */
/* Move symbol to plus. */
XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
/* Move plus inside unspec. */
XVECEXP (unspec, 0, 0) = plus;
/* Move unspec to top level of const. */
XEXP (x, 0) = unspec;
}
iter.skip_subrtxes ();
}
}
}
}
/* Move X to a register and add REG_EQUAL note pointing to ORIG.
If REG is non-null, use it; generate new pseudo otherwise. */
static rtx
m68k_move_to_reg (rtx x, rtx orig, rtx reg)
{
rtx_insn *insn;
if (reg == NULL_RTX)
{
gcc_assert (can_create_pseudo_p ());
reg = gen_reg_rtx (Pmode);
}
insn = emit_move_insn (reg, x);
/* Put a REG_EQUAL note on this insn, so that it can be optimized
by loop. */
set_unique_reg_note (insn, REG_EQUAL, orig);
return reg;
}
/* Does the same as m68k_wrap_symbol, but returns a memory reference to
GOT slot. */
static rtx
m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
{
x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
x = gen_rtx_MEM (Pmode, x);
MEM_READONLY_P (x) = 1;
return x;
}
/* Legitimize PIC addresses. If the address is already
position-independent, we return ORIG. Newly generated
position-independent addresses go to REG. If we need more
than one register, we lose.
An address is legitimized by making an indirect reference
through the Global Offset Table with the name of the symbol
used as an offset.
The assembler and linker are responsible for placing the
address of the symbol in the GOT. The function prologue
is responsible for initializing a5 to the starting address
of the GOT.
The assembler is also responsible for translating a symbol name
into a constant displacement from the start of the GOT.
A quick example may make things a little clearer:
When not generating PIC code to store the value 12345 into _foo
we would generate the following code:
movel #12345, _foo
When generating PIC two transformations are made. First, the compiler
loads the address of foo into a register. So the first transformation makes:
lea _foo, a0
movel #12345, a0@
The code in movsi will intercept the lea instruction and call this
routine which will transform the instructions into:
movel a5@(_foo:w), a0
movel #12345, a0@
That (in a nutshell) is how *all* symbol and label references are
handled. */
rtx
legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
rtx pic_ref = orig;
/* First handle a simple SYMBOL_REF or LABEL_REF */
if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
{
gcc_assert (reg);
pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
}
else if (GET_CODE (orig) == CONST)
{
rtx base;
/* Make sure this has not already been legitimized. */
if (m68k_unwrap_symbol (orig, true) != orig)
return orig;
gcc_assert (reg);
/* legitimize both operands of the PLUS */
gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg);
if (GET_CODE (orig) == CONST_INT)
pic_ref = plus_constant (Pmode, base, INTVAL (orig));
else
pic_ref = gen_rtx_PLUS (Pmode, base, orig);
}
return pic_ref;
}
/* The __tls_get_addr symbol. */
static GTY(()) rtx m68k_tls_get_addr;
/* Return SYMBOL_REF for __tls_get_addr. */
static rtx
m68k_get_tls_get_addr (void)
{
if (m68k_tls_get_addr == NULL_RTX)
m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
return m68k_tls_get_addr;
}
/* Return libcall result in A0 instead of usual D0. */
static bool m68k_libcall_value_in_a0_p = false;
/* Emit instruction sequence that calls __tls_get_addr. X is
the TLS symbol we are referencing and RELOC is the symbol type to use
(either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
emitted. A pseudo register with result of __tls_get_addr call is
returned. */
static rtx
m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
{
rtx a0;
rtx_insn *insns;
rtx dest;
/* Emit the call sequence. */
start_sequence ();
/* FIXME: Unfortunately, emit_library_call_value does not
consider (plus (%a5) (const (unspec))) to be a good enough
operand for push, so it forces it into a register. The bad
thing about this is that combiner, due to copy propagation and other
optimizations, sometimes can not later fix this. As a consequence,
additional register may be allocated resulting in a spill.
For reference, see args processing loops in
calls.c:emit_library_call_value_1.
For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
/* __tls_get_addr() is not a libcall, but emitting a libcall_value
is the simpliest way of generating a call. The difference between
__tls_get_addr() and libcall is that the result is returned in D0
instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
which temporarily switches returning the result to A0. */
m68k_libcall_value_in_a0_p = true;
a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
Pmode, x, Pmode);
m68k_libcall_value_in_a0_p = false;
insns = get_insns ();
end_sequence ();
gcc_assert (can_create_pseudo_p ());
dest = gen_reg_rtx (Pmode);
emit_libcall_block (insns, dest, a0, eqv);
return dest;
}
/* The __tls_get_addr symbol. */
static GTY(()) rtx m68k_read_tp;
/* Return SYMBOL_REF for __m68k_read_tp. */
static rtx
m68k_get_m68k_read_tp (void)
{
if (m68k_read_tp == NULL_RTX)
m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
return m68k_read_tp;
}
/* Emit instruction sequence that calls __m68k_read_tp.
A pseudo register with result of __m68k_read_tp call is returned. */
static rtx
m68k_call_m68k_read_tp (void)
{
rtx a0;
rtx eqv;
rtx_insn *insns;
rtx dest;
start_sequence ();
/* __m68k_read_tp() is not a libcall, but emitting a libcall_value
is the simpliest way of generating a call. The difference between
__m68k_read_tp() and libcall is that the result is returned in D0
instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
which temporarily switches returning the result to A0. */
/* Emit the call sequence. */
m68k_libcall_value_in_a0_p = true;
a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
Pmode);
m68k_libcall_value_in_a0_p = false;
insns = get_insns ();
end_sequence ();
/* Attach a unique REG_EQUIV, to allow the RTL optimizers to
share the m68k_read_tp result with other IE/LE model accesses. */
eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
gcc_assert (can_create_pseudo_p ());
dest = gen_reg_rtx (Pmode);
emit_libcall_block (insns, dest, a0, eqv);
return dest;
}
/* Return a legitimized address for accessing TLS SYMBOL_REF X.
For explanations on instructions sequences see TLS/NPTL ABI for m68k and
ColdFire. */
rtx
m68k_legitimize_tls_address (rtx orig)
{
switch (SYMBOL_REF_TLS_MODEL (orig))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
break;
case TLS_MODEL_LOCAL_DYNAMIC:
{
rtx eqv;
rtx a0;
rtx x;
/* Attach a unique REG_EQUIV, to allow the RTL optimizers to
share the LDM result with other LD model accesses. */
eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
UNSPEC_RELOC32);
a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
if (can_create_pseudo_p ())
x = m68k_move_to_reg (x, orig, NULL_RTX);
orig = x;
break;
}
case TLS_MODEL_INITIAL_EXEC:
{
rtx a0;
rtx x;
a0 = m68k_call_m68k_read_tp ();
x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
x = gen_rtx_PLUS (Pmode, x, a0);
if (can_create_pseudo_p ())
x = m68k_move_to_reg (x, orig, NULL_RTX);
orig = x;
break;
}
case TLS_MODEL_LOCAL_EXEC:
{
rtx a0;
rtx x;
a0 = m68k_call_m68k_read_tp ();
x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
if (can_create_pseudo_p ())
x = m68k_move_to_reg (x, orig, NULL_RTX);
orig = x;
break;
}
default:
gcc_unreachable ();
}
return orig;
}
/* Return true if X is a TLS symbol. */
static bool
m68k_tls_symbol_p (rtx x)
{
if (!TARGET_HAVE_TLS)
return false;
if (GET_CODE (x) != SYMBOL_REF)
return false;
return SYMBOL_REF_TLS_MODEL (x) != 0;
}
/* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
though illegitimate one.
If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
bool
m68k_tls_reference_p (rtx x, bool legitimate_p)
{
if (!TARGET_HAVE_TLS)
return false;
if (!legitimate_p)
{
subrtx_var_iterator::array_type array;
FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
{
rtx x = *iter;
/* Note: this is not the same as m68k_tls_symbol_p. */
if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Don't recurse into legitimate TLS references. */
if (m68k_tls_reference_p (x, true))
iter.skip_subrtxes ();
}
return false;
}
else
{
enum m68k_reloc reloc = RELOC_GOT;
return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
&& TLS_RELOC_P (reloc));
}
}
#define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
/* Return the type of move that should be used for integer I. */
M68K_CONST_METHOD
m68k_const_method (HOST_WIDE_INT i)
{
unsigned u;
if (USE_MOVQ (i))
return MOVQ;
/* The ColdFire doesn't have byte or word operations. */
/* FIXME: This may not be useful for the m68060 either. */
if (!TARGET_COLDFIRE)
{
/* if -256 < N < 256 but N is not in range for a moveq
N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
if (USE_MOVQ (i ^ 0xff))
return NOTB;
/* Likewise, try with not.w */
if (USE_MOVQ (i ^ 0xffff))
return NOTW;
/* This is the only value where neg.w is useful */
if (i == -65408)
return NEGW;
}
/* Try also with swap. */
u = i;
if (USE_MOVQ ((u >> 16) | (u << 16)))
return SWAP;
if (TARGET_ISAB)
{
/* Try using MVZ/MVS with an immediate value to load constants. */
if (i >= 0 && i <= 65535)
return MVZ;
if (i >= -32768 && i <= 32767)
return MVS;
}
/* Otherwise, use move.l */
return MOVL;
}
/* Return the cost of moving constant I into a data register. */
static int
const_int_cost (HOST_WIDE_INT i)
{
switch (m68k_const_method (i))
{
case MOVQ:
/* Constants between -128 and 127 are cheap due to moveq. */
return 0;
case MVZ:
case MVS:
case NOTB:
case NOTW:
case NEGW:
case SWAP:
/* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
return 1;
case MOVL:
return 2;
default:
gcc_unreachable ();
}
}
static bool
m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
int opno ATTRIBUTE_UNUSED,
int *total, bool speed ATTRIBUTE_UNUSED)
{
int code = GET_CODE (x);
switch (code)
{
case CONST_INT:
/* Constant zero is super cheap due to clr instruction. */
if (x == const0_rtx)
*total = 0;
else
*total = const_int_cost (INTVAL (x));
return true;
case CONST:
case LABEL_REF:
case SYMBOL_REF:
*total = 3;
return true;
case CONST_DOUBLE:
/* Make 0.0 cheaper than other floating constants to
encourage creating tstsf and tstdf insns. */
if (outer_code == COMPARE
&& (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
*total = 4;
else
*total = 5;
return true;
/* These are vaguely right for a 68020. */
/* The costs for long multiply have been adjusted to work properly
in synth_mult on the 68020, relative to an average of the time
for add and the time for shift, taking away a little more because
sometimes move insns are needed. */
/* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
terms. */
#define MULL_COST \
(TUNE_68060 ? 2 \
: TUNE_68040 ? 5 \
: (TUNE_CFV2 && TUNE_EMAC) ? 3 \
: (TUNE_CFV2 && TUNE_MAC) ? 4 \
: TUNE_CFV2 ? 8 \
: TARGET_COLDFIRE ? 3 : 13)
#define MULW_COST \
(TUNE_68060 ? 2 \
: TUNE_68040 ? 3 \
: TUNE_68000_10 ? 5 \
: (TUNE_CFV2 && TUNE_EMAC) ? 3 \
: (TUNE_CFV2 && TUNE_MAC) ? 2 \
: TUNE_CFV2 ? 8 \
: TARGET_COLDFIRE ? 2 : 8)
#define DIVW_COST \
(TARGET_CF_HWDIV ? 11 \
: TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
case PLUS:
/* An lea costs about three times as much as a simple add. */
if (mode == SImode
&& GET_CODE (XEXP (x, 1)) == REG
&& GET_CODE (XEXP (x, 0)) == MULT
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 4
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
{
/* lea an@(dx:l:i),am */
*total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
return true;
}
return false;
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
if (TUNE_68060)
{
*total = COSTS_N_INSNS(1);
return true;
}
if (TUNE_68000_10)
{
if (GET_CODE (XEXP (x, 1)) == CONST_INT)
{
if (INTVAL (XEXP (x, 1)) < 16)
*total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
else
/* We're using clrw + swap for these cases. */
*total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
}
else
*total = COSTS_N_INSNS (10); /* Worst case. */
return true;
}
/* A shift by a big integer takes an extra instruction. */
if (GET_CODE (XEXP (x, 1)) == CONST_INT
&& (INTVAL (XEXP (x, 1)) == 16))
{
*total = COSTS_N_INSNS (2); /* clrw;swap */
return true;
}
if (GET_CODE (XEXP (x, 1)) == CONST_INT
&& !(INTVAL (XEXP (x, 1)) > 0
&& INTVAL (XEXP (x, 1)) <= 8))
{
*total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
return true;
}
return false;
case MULT:
if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
|| GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
&& mode == SImode)
*total = COSTS_N_INSNS (MULW_COST);
else if (mode == QImode || mode == HImode)
*total = COSTS_N_INSNS (MULW_COST);
else
*total = COSTS_N_INSNS (MULL_COST);
return true;
case DIV:
case UDIV:
case MOD:
case UMOD:
if (mode == QImode || mode == HImode)
*total = COSTS_N_INSNS (DIVW_COST); /* div.w */
else if (TARGET_CF_HWDIV)
*total = COSTS_N_INSNS (18);
else
*total = COSTS_N_INSNS (43); /* div.l */
return true;
case ZERO_EXTRACT:
if (outer_code == COMPARE)
*total = 0;
return false;
default:
return false;
}
}
/* Return an instruction to move CONST_INT OPERANDS[1] into data register
OPERANDS[0]. */
static const char *
output_move_const_into_data_reg (rtx *operands)
{
HOST_WIDE_INT i;
i = INTVAL (operands[1]);
switch (m68k_const_method (i))
{
case MVZ:
return "mvzw %1,%0";
case MVS:
return "mvsw %1,%0";
case MOVQ:
return "moveq %1,%0";
case NOTB:
CC_STATUS_INIT;
operands[1] = GEN_INT (i ^ 0xff);
return "moveq %1,%0\n\tnot%.b %0";
case NOTW:
CC_STATUS_INIT;
operands[1] = GEN_INT (i ^ 0xffff);
return "moveq %1,%0\n\tnot%.w %0";
case NEGW:
CC_STATUS_INIT;
return "moveq #-128,%0\n\tneg%.w %0";
case SWAP:
{
unsigned u = i;
operands[1] = GEN_INT ((u << 16) | (u >> 16));
return "moveq %1,%0\n\tswap %0";
}
case MOVL:
return "move%.l %1,%0";
default:
gcc_unreachable ();
}
}
/* Return true if I can be handled by ISA B's mov3q instruction. */
bool
valid_mov3q_const (HOST_WIDE_INT i)
{
return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
}
/* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
I is the value of OPERANDS[1]. */
static const char *
output_move_simode_const (rtx *operands)
{
rtx dest;
HOST_WIDE_INT src;
dest = operands[0];
src = INTVAL (operands[1]);
if (src == 0
&& (DATA_REG_P (dest) || MEM_P (dest))
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
|| !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
return "clr%.l %0";
else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
return "mov3q%.l %1,%0";
else if (src == 0 && ADDRESS_REG_P (dest))
return "sub%.l %0,%0";
else if (DATA_REG_P (dest))
return output_move_const_into_data_reg (operands);
else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
{
if (valid_mov3q_const (src))
return "mov3q%.l %1,%0";
return "move%.w %1,%0";
}
else if (MEM_P (dest)
&& GET_CODE (XEXP (dest, 0)) == PRE_DEC
&& REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
&& IN_RANGE (src, -0x8000, 0x7fff))
{
if (valid_mov3q_const (src))
return "mov3q%.l %1,%-";
return "pea %a1";
}
return "move%.l %1,%0";
}
const char *
output_move_simode (rtx *operands)
{
if (GET_CODE (operands[1]) == CONST_INT)
return output_move_simode_const (operands);
else if ((GET_CODE (operands[1]) == SYMBOL_REF
|| GET_CODE (operands[1]) == CONST)
&& push_operand (operands[0], SImode))
return "pea %a1";
else if ((GET_CODE (operands[1]) == SYMBOL_REF
|| GET_CODE (operands[1]) == CONST)
&& ADDRESS_REG_P (operands[0]))
return "lea %a1,%0";
return "move%.l %1,%0";
}
const char *
output_move_himode (rtx *operands)
{
if (GET_CODE (operands[1]) == CONST_INT)
{
if (operands[1] == const0_rtx
&& (DATA_REG_P (operands[0])
|| GET_CODE (operands[0]) == MEM)
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM
&& MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0";
else if (operands[1] == const0_rtx
&& ADDRESS_REG_P (operands[0]))
return "sub%.l %0,%0";
else if (DATA_REG_P (operands[0])
&& INTVAL (operands[1]) < 128
&& INTVAL (operands[1]) >= -128)
return "moveq %1,%0";
else if (INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
return "move%.w %1,%0";
}
else if (CONSTANT_P (operands[1]))
return "move%.l %1,%0";
return "move%.w %1,%0";
}
const char *
output_move_qimode (rtx *operands)
{
/* 68k family always modifies the stack pointer by at least 2, even for
byte pushes. The 5200 (ColdFire) does not do this. */
/* This case is generated by pushqi1 pattern now. */
gcc_assert (!(GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
&& ! ADDRESS_REG_P (operands[1])
&& ! TARGET_COLDFIRE));
/* clr and st insns on 68000 read before writing. */
if (!ADDRESS_REG_P (operands[0])
&& ((TARGET_68010 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
{
if (operands[1] == const0_rtx)
return "clr%.b %0";
if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
&& GET_CODE (operands[1]) == CONST_INT
&& (INTVAL (operands[1]) & 255) == 255)
{
CC_STATUS_INIT;
return "st %0";
}
}
if (GET_CODE (operands[1]) == CONST_INT
&& DATA_REG_P (operands[0])
&& INTVAL (operands[1]) < 128
&& INTVAL (operands[1]) >= -128)
return "moveq %1,%0";
if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
return "sub%.l %0,%0";
if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
return "move%.l %1,%0";
/* 68k family (including the 5200 ColdFire) does not support byte moves to
from address registers. */
if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
return "move%.w %1,%0";
return "move%.b %1,%0";
}
const char *
output_move_stricthi (rtx *operands)
{
if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0";
return "move%.w %1,%0";
}
const char *
output_move_strictqi (rtx *operands)
{
if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
|| !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
return "clr%.b %0";
return "move%.b %1,%0";
}
/* Return the best assembler insn template
for moving operands[1] into operands[0] as a fullword. */
static const char *
singlemove_string (rtx *operands)
{
if (GET_CODE (operands[1]) == CONST_INT)
return output_move_simode_const (operands);
return "move%.l %1,%0";
}
/* Output assembler or rtl code to perform a doubleword move insn
with operands OPERANDS.
Pointers to 3 helper functions should be specified:
HANDLE_REG_ADJUST to adjust a register by a small value,
HANDLE_COMPADR to compute an address and
HANDLE_MOVSI to move 4 bytes. */
static void
handle_move_double (rtx operands[2],
void (*handle_reg_adjust) (rtx, int),
void (*handle_compadr) (rtx [2]),
void (*handle_movsi) (rtx [2]))
{
enum
{
REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
} optype0, optype1;
rtx latehalf[2];
rtx middlehalf[2];
rtx xops[2];
rtx addreg0 = 0, addreg1 = 0;
int dest_overlapped_low = 0;
int size = GET_MODE_SIZE (GET_MODE (operands[0]));
middlehalf[0] = 0;
middlehalf[1] = 0;
/* First classify both operands. */
if (REG_P (operands[0]))
optype0 = REGOP;
else if (offsettable_memref_p (operands[0]))
optype0 = OFFSOP;
else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
optype0 = POPOP;
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
optype0 = PUSHOP;
else if (GET_CODE (operands[0]) == MEM)
optype0 = MEMOP;
else
optype0 = RNDOP;
if (REG_P (operands[1]))
optype1 = REGOP;
else if (CONSTANT_P (operands[1]))
optype1 = CNSTOP;
else if (offsettable_memref_p (operands[1]))
optype1 = OFFSOP;
else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
optype1 = POPOP;
else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
optype1 = PUSHOP;
else if (GET_CODE (operands[1]) == MEM)
optype1 = MEMOP;
else
optype1 = RNDOP;
/* Check for the cases that the operand constraints are not supposed
to allow to happen. Generating code for these cases is
painful. */
gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
/* If one operand is decrementing and one is incrementing
decrement the former register explicitly
and change that operand into ordinary indexing. */
if (optype0 == PUSHOP && optype1 == POPOP)
{
operands[0] = XEXP (XEXP (operands[0], 0), 0);
handle_reg_adjust (operands[0], -size);
if (GET_MODE (operands[1]) == XFmode)
operands[0] = gen_rtx_MEM (XFmode, operands[0]);
else if (GET_MODE (operands[0]) == DFmode)
operands[0] = gen_rtx_MEM (DFmode, operands[0]);
else
operands[0] = gen_rtx_MEM (DImode, operands[0]);
optype0 = OFFSOP;
}
if (optype0 == POPOP && optype1 == PUSHOP)
{
operands[1] = XEXP (XEXP (operands[1], 0), 0);
handle_reg_adjust (operands[1], -size);
if (GET_MODE (operands[1]) == XFmode)
operands[1] = gen_rtx_MEM (XFmode, operands[1]);
else if (GET_MODE (operands[1]) == DFmode)
operands[1] = gen_rtx_MEM (DFmode, operands[1]);
else
operands[1] = gen_rtx_MEM (DImode, operands[1]);
optype1 = OFFSOP;
}
/* If an operand is an unoffsettable memory ref, find a register
we can increment temporarily to make it refer to the second word. */
if (optype0 == MEMOP)
addreg0 = find_addr_reg (XEXP (operands[0], 0));
if (optype1 == MEMOP)
addreg1 = find_addr_reg (XEXP (operands[1], 0));
/* Ok, we can do one word at a time.
Normally we do the low-numbered word first,
but if either operand is autodecrementing then we
do the high-numbered word first.
In either case, set up in LATEHALF the operands to use
for the high-numbered word and in some cases alter the
operands in OPERANDS to be suitable for the low-numbered word. */
if (size == 12)
{
if (optype0 == REGOP)
{
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
}
else if (optype0 == OFFSOP)
{
middlehalf[0] = adjust_address (operands[0], SImode, 4);
latehalf[0] = adjust_address (operands[0], SImode, size - 4);
}
else
{
middlehalf[0] = adjust_address (operands[0], SImode, 0);
latehalf[0] = adjust_address (operands[0], SImode, 0);
}
if (optype1 == REGOP)
{
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
}
else if (optype1 == OFFSOP)
{
middlehalf[1] = adjust_address (operands[1], SImode, 4);
latehalf[1] = adjust_address (operands[1], SImode, size - 4);
}
else if (optype1 == CNSTOP)
{
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
long l[3];
REAL_VALUE_TO_TARGET_LONG_DOUBLE
(*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
operands[1] = GEN_INT (l[0]);
middlehalf[1] = GEN_INT (l[1]);
latehalf[1] = GEN_INT (l[2]);
}
else
{
/* No non-CONST_DOUBLE constant should ever appear
here. */
gcc_assert (!CONSTANT_P (operands[1]));
}
}
else
{
middlehalf[1] = adjust_address (operands[1], SImode, 0);
latehalf[1] = adjust_address (operands[1], SImode, 0);
}
}
else
/* size is not 12: */
{
if (optype0 == REGOP)
latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else if (optype0 == OFFSOP)
latehalf[0] = adjust_address (operands[0], SImode, size - 4);
else
latehalf[0] = adjust_address (operands[0], SImode, 0);
if (optype1 == REGOP)
latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (optype1 == OFFSOP)
latehalf[1] = adjust_address (operands[1], SImode, size - 4);
else if (optype1 == CNSTOP)
split_double (operands[1], &operands[1], &latehalf[1]);
else
latehalf[1] = adjust_address (operands[1], SImode, 0);
}
/* If insn is effectively movd N(REG),-(REG) then we will do the high
word first. We should use the adjusted operand 1 (which is N+4(REG))
for the low word as well, to compensate for the first decrement of
REG. */
if (optype0 == PUSHOP
&& reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))
operands[1] = middlehalf[1] = latehalf[1];
/* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
if the upper part of reg N does not appear in the MEM, arrange to
emit the move late-half first. Otherwise, compute the MEM address
into the upper part of N and use that as a pointer to the memory
operand. */
if (optype0 == REGOP
&& (optype1 == OFFSOP || optype1 == MEMOP))
{
rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
&& reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
{
/* If both halves of dest are used in the src memory address,
compute the address into latehalf of dest.
Note that this can't happen if the dest is two data regs. */
compadr:
xops[0] = latehalf[0];
xops[1] = XEXP (operands[1], 0);
handle_compadr (xops);
if (GET_MODE (operands[1]) == XFmode)
{
operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
latehalf[1] = adjust_address (operands[1], DImode, size - 4);
}
else
{
operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
latehalf[1] = adjust_address (operands[1], DImode, size - 4);
}
}
else if (size == 12
&& reg_overlap_mentioned_p (middlehalf[0],
XEXP (operands[1], 0)))
{
/* Check for two regs used by both source and dest.
Note that this can't happen if the dest is all data regs.
It can happen if the dest is d6, d7, a0.
But in that case, latehalf is an addr reg, so
the code at compadr does ok. */
if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
|| reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
goto compadr;
/* JRV says this can't happen: */
gcc_assert (!addreg0 && !addreg1);
/* Only the middle reg conflicts; simply put it last. */
handle_movsi (operands);
handle_movsi (latehalf);
handle_movsi (middlehalf);
return;
}
else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
/* If the low half of dest is mentioned in the source memory
address, the arrange to emit the move late half first. */
dest_overlapped_low = 1;
}
/* If one or both operands autodecrementing,
do the two words, high-numbered first. */
/* Likewise, the first move would clobber the source of the second one,
do them in the other order. This happens only for registers;
such overlap can't happen in memory unless the user explicitly
sets it up, and that is an undefined circumstance. */
if (optype0 == PUSHOP || optype1 == PUSHOP
|| (optype0 == REGOP && optype1 == REGOP
&& ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
|| REGNO (operands[0]) == REGNO (latehalf[1])))
|| dest_overlapped_low)
{
/* Make any unoffsettable addresses point at high-numbered word. */
if (addreg0)
handle_reg_adjust (addreg0, size - 4);
if (addreg1)
handle_reg_adjust (addreg1, size - 4);
/* Do that word. */
handle_movsi (latehalf);
/* Undo the adds we just did. */
if (addreg0)
handle_reg_adjust (addreg0, -4);
if (addreg1)
handle_reg_adjust (addreg1, -4);
if (size == 12)
{
handle_movsi (middlehalf);
if (addreg0)
handle_reg_adjust (addreg0, -4);
if (addreg1)
handle_reg_adjust (addreg1, -4);
}
/* Do low-numbered word. */
handle_movsi (operands);
return;
}
/* Normal case: do the two words, low-numbered first. */
m68k_final_prescan_insn (NULL, operands, 2);
handle_movsi (operands);
/* Do the middle one of the three words for long double */
if (size == 12)
{
if (addreg0)
handle_reg_adjust (addreg0, 4);
if (addreg1)
handle_reg_adjust (addreg1, 4);
m68k_final_prescan_insn (NULL, middlehalf, 2);
handle_movsi (middlehalf);
}
/* Make any unoffsettable addresses point at high-numbered word. */
if (addreg0)
handle_reg_adjust (addreg0, 4);
if (addreg1)
handle_reg_adjust (addreg1, 4);
/* Do that word. */
m68k_final_prescan_insn (NULL, latehalf, 2);
handle_movsi (latehalf);
/* Undo the adds we just did. */
if (addreg0)
handle_reg_adjust (addreg0, -(size - 4));
if (addreg1)
handle_reg_adjust (addreg1, -(size - 4));
return;
}
/* Output assembler code to adjust REG by N. */
static void
output_reg_adjust (rtx reg, int n)
{
const char *s;
gcc_assert (GET_MODE (reg) == SImode && n >= -12 && n != 0 && n <= 12);
switch (n)
{
case 12:
s = "add%.l #12,%0";
break;
case 8:
s = "addq%.l #8,%0";
break;
case 4:
s = "addq%.l #4,%0";
break;
case -12:
s = "sub%.l #12,%0";
break;
case -8:
s = "subq%.l #8,%0";
break;
case -4:
s = "subq%.l #4,%0";
break;
default:
gcc_unreachable ();
s = NULL;
}
output_asm_insn (s, ®);
}
/* Emit rtl code to adjust REG by N. */
static void
emit_reg_adjust (rtx reg1, int n)
{
rtx reg2;
gcc_assert (GET_MODE (reg1) == SImode && n >= -12 && n != 0 && n <= 12);
reg1 = copy_rtx (reg1);
reg2 = copy_rtx (reg1);
if (n < 0)
emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
else if (n > 0)
emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
else
gcc_unreachable ();
}
/* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
static void
output_compadr (rtx operands[2])
{
output_asm_insn ("lea %a1,%0", operands);
}
/* Output the best assembler insn for moving operands[1] into operands[0]
as a fullword. */
static void
output_movsi (rtx operands[2])
{
output_asm_insn (singlemove_string (operands), operands);
}
/* Copy OP and change its mode to MODE. */
static rtx
copy_operand (rtx op, machine_mode mode)
{
/* ??? This looks really ugly. There must be a better way
to change a mode on the operand. */
if (GET_MODE (op) != VOIDmode)
{
if (REG_P (op))
op = gen_rtx_REG (mode, REGNO (op));
else
{
op = copy_rtx (op);
PUT_MODE (op, mode);
}
}
return op;
}
/* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
static void
emit_movsi (rtx operands[2])
{
operands[0] = copy_operand (operands[0], SImode);
operands[1] = copy_operand (operands[1], SImode);
emit_insn (gen_movsi (operands[0], operands[1]));
}
/* Output assembler code to perform a doubleword move insn
with operands OPERANDS. */
const char *
output_move_double (rtx *operands)
{
handle_move_double (operands,
output_reg_adjust, output_compadr, output_movsi);
return "";
}
/* Output rtl code to perform a doubleword move insn
with operands OPERANDS. */
void
m68k_emit_move_double (rtx operands[2])
{
handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
}
/* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
new rtx with the correct mode. */
static rtx
force_mode (machine_mode mode, rtx orig)
{
if (mode == GET_MODE (orig))
return orig;
if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
abort ();
return gen_rtx_REG (mode, REGNO (orig));
}
static int
fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
return reg_renumber && FP_REG_P (op);
}
/* Emit insns to move operands[1] into operands[0].
Return 1 if we have written out everything that needs to be done to
do the move. Otherwise, return 0 and the caller will emit the move
normally.
Note SCRATCH_REG may not be in the proper mode depending on how it
will be used. This routine is responsible for creating a new copy
of SCRATCH_REG in the proper mode. */
int
emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
{
register rtx operand0 = operands[0];
register rtx operand1 = operands[1];
register rtx tem;
if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == REG
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == SUBREG
&& GET_CODE (SUBREG_REG (operand0)) == REG
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
the code which tracks sets/uses for delete_output_reload. */
rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
SUBREG_BYTE (operand0));
operand0 = alter_subreg (&temp, true);
}
if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == REG
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == SUBREG
&& GET_CODE (SUBREG_REG (operand1)) == REG
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
the code which tracks sets/uses for delete_output_reload. */
rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
SUBREG_BYTE (operand1));
operand1 = alter_subreg (&temp, true);
}
if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
&& ((tem = find_replacement (&XEXP (operand0, 0)))
!= XEXP (operand0, 0)))
operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
&& ((tem = find_replacement (&XEXP (operand1, 0)))
!= XEXP (operand1, 0)))
operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
/* Handle secondary reloads for loads/stores of FP registers where
the address is symbolic by using the scratch register */
if (fp_reg_operand (operand0, mode)
&& ((GET_CODE (operand1) == MEM
&& ! memory_address_p (DFmode, XEXP (operand1, 0)))
|| ((GET_CODE (operand1) == SUBREG
&& GET_CODE (XEXP (operand1, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
&& scratch_reg)
{
if (GET_CODE (operand1) == SUBREG)
operand1 = XEXP (operand1, 0);
/* SCRATCH_REG will hold an address. We want
it in SImode regardless of what mode it was originally given
to us. */
scratch_reg = force_mode (SImode, scratch_reg);
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
if (!memory_address_p (Pmode, XEXP (operand1, 0)))
{
emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
Pmode,
XEXP (XEXP (operand1, 0), 0),
scratch_reg));
}
else
emit_move_insn (scratch_reg, XEXP (operand1, 0));
emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
return 1;
}
else if (fp_reg_operand (operand1, mode)
&& ((GET_CODE (operand0) == MEM
&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
|| ((GET_CODE (operand0) == SUBREG)
&& GET_CODE (XEXP (operand0, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
&& scratch_reg)
{
if (GET_CODE (operand0) == SUBREG)
operand0 = XEXP (operand0, 0);
/* SCRATCH_REG will hold an address and maybe the actual data. We want
it in SIMODE regardless of what mode it was originally given
to us. */
scratch_reg = force_mode (SImode, scratch_reg);
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
if (!memory_address_p (Pmode, XEXP (operand0, 0)))
{
emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
0)),
Pmode,
XEXP (XEXP (operand0, 0),
0),
scratch_reg));
}
else
emit_move_insn (scratch_reg, XEXP (operand0, 0));
emit_insn (gen_rtx_SET (gen_rtx_MEM (mode, scratch_reg), operand1));
return 1;
}
/* Handle secondary reloads for loads of FP registers from constant
expressions by forcing the constant into memory.
use scratch_reg to hold the address of the memory location.
The proper fix is to change PREFERRED_RELOAD_CLASS to return
NO_REGS when presented with a const_int and an register class
containing only FP registers. Doing so unfortunately creates
more problems than it solves. Fix this for 2.5. */
else if (fp_reg_operand (operand0, mode)
&& CONSTANT_P (operand1)
&& scratch_reg)
{
rtx xoperands[2];
/* SCRATCH_REG will hold an address and maybe the actual data. We want
it in SIMODE regardless of what mode it was originally given
to us. */
scratch_reg = force_mode (SImode, scratch_reg);
/* Force the constant into memory and put the address of the
memory location into scratch_reg. */
xoperands[0] = scratch_reg;
xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
emit_insn (gen_rtx_SET (scratch_reg, xoperands[1]));
/* Now load the destination register. */
emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
return 1;
}
/* Now have insn-emit do whatever it normally does. */
return 0;
}
/* Split one or more DImode RTL references into pairs of SImode
references. The RTL can be REG, offsettable MEM, integer constant, or
CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
split and "num" is its length. lo_half and hi_half are output arrays
that parallel "operands". */
void
split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
{
while (num--)
{
rtx op = operands[num];
/* simplify_subreg refuses to split volatile memory addresses,
but we still have to handle it. */
if (GET_CODE (op) == MEM)
{
lo_half[num] = adjust_address (op, SImode, 4);
hi_half[num] = adjust_address (op, SImode, 0);
}
else
{
lo_half[num] = simplify_gen_subreg (SImode, op,
GET_MODE (op) == VOIDmode
? DImode : GET_MODE (op), 4);
hi_half[num] = simplify_gen_subreg (SImode, op,
GET_MODE (op) == VOIDmode
? DImode : GET_MODE (op), 0);
}
}
}
/* Split X into a base and a constant offset, storing them in *BASE
and *OFFSET respectively. */
static void
m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
{
*offset = 0;
if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
{
*offset += INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
}
*base = x;
}
/* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
instruction. STORE_P says whether the move is a load or store.
If the instruction uses post-increment or pre-decrement addressing,
AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
adjustment. This adjustment will be made by the first element of
PARALLEL, with the loads or stores starting at element 1. If the
instruction does not use post-increment or pre-decrement addressing,
AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
start at element 0. */
bool
m68k_movem_pattern_p (rtx pattern, rtx automod_base,
HOST_WIDE_INT automod_offset, bool store_p)
{
rtx base, mem_base, set, mem, reg, last_reg;
HOST_WIDE_INT offset, mem_offset;
int i, first, len;
enum reg_class rclass;
len = XVECLEN (pattern, 0);
first = (automod_base != NULL);
if (automod_base)
{
/* Stores must be pre-decrement and loads must be post-increment. */
if (store_p != (automod_offset < 0))
return false;
/* Work out the base and offset for lowest memory location. */
base = automod_base;
offset = (automod_offset < 0 ? automod_offset : 0);
}
else
{
/* Allow any valid base and offset in the first access. */
base = NULL;
offset = 0;
}
last_reg = NULL;
rclass = NO_REGS;
for (i = first; i < len; i++)
{
/* We need a plain SET. */
set = XVECEXP (pattern, 0, i);
if (GET_CODE (set) != SET)
return false;
/* Check that we have a memory location... */
mem = XEXP (set, !store_p);
if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
return false;
/* ...with the right address. */
if (base == NULL)
{
m68k_split_offset (XEXP (mem, 0), &base, &offset);
/* The ColdFire instruction only allows (An) and (d16,An) modes.
There are no mode restrictions for 680x0 besides the
automodification rules enforced above. */
if (TARGET_COLDFIRE
&& !m68k_legitimate_base_reg_p (base, reload_completed))
return false;
}
else
{
m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
return false;
}
/* Check that we have a register of the required mode and class. */
reg = XEXP (set, store_p);
if (!REG_P (reg)
|| !HARD_REGISTER_P (reg)
|| GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
return false;
if (last_reg)
{
/* The register must belong to RCLASS and have a higher number
than the register in the previous SET. */
if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
|| REGNO (last_reg) >= REGNO (reg))
return false;
}
else
{
/* Work out which register class we need. */
if (INT_REGNO_P (REGNO (reg)))
rclass = GENERAL_REGS;
else if (FP_REGNO_P (REGNO (reg)))
rclass = FP_REGS;
else
return false;
}
last_reg = reg;
offset += GET_MODE_SIZE (GET_MODE (reg));
}
/* If we have an automodification, check whether the final offset is OK. */
if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
return false;
/* Reject unprofitable cases. */
if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
return false;
return true;
}
/* Return the assembly code template for a movem or fmovem instruction
whose pattern is given by PATTERN. Store the template's operands
in OPERANDS.
If the instruction uses post-increment or pre-decrement addressing,
AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
is true if this is a store instruction. */
const char *
m68k_output_movem (rtx *operands, rtx pattern,
HOST_WIDE_INT automod_offset, bool store_p)
{
unsigned int mask;
int i, first;
gcc_assert (GET_CODE (pattern) == PARALLEL);
mask = 0;
first = (automod_offset != 0);
for (i = first; i < XVECLEN (pattern, 0); i++)
{
/* When using movem with pre-decrement addressing, register X + D0_REG
is controlled by bit 15 - X. For all other addressing modes,
register X + D0_REG is controlled by bit X. Confusingly, the
register mask for fmovem is in the opposite order to that for
movem. */
unsigned int regno;
gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
if (automod_offset < 0)
{
if (FP_REGNO_P (regno))
mask |= 1 << (regno - FP0_REG);
else
mask |= 1 << (15 - (regno - D0_REG));
}
else
{
if (FP_REGNO_P (regno))
mask |= 1 << (7 - (regno - FP0_REG));
else
mask |= 1 << (regno - D0_REG);
}
}
CC_STATUS_INIT;
if (automod_offset == 0)
operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
else if (automod_offset < 0)
operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
else
operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
operands[1] = GEN_INT (mask);
if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
{
if (store_p)
return "fmovem %1,%a0";
else
return "fmovem %a0,%1";
}
else
{
if (store_p)
return "movem%.l %1,%a0";
else
return "movem%.l %a0,%1";
}
}
/* Return a REG that occurs in ADDR with coefficient 1.
ADDR can be effectively incremented by incrementing REG. */
static rtx
find_addr_reg (rtx addr)
{
while (GET_CODE (addr) == PLUS)
{
if (GET_CODE (XEXP (addr, 0)) == REG)
addr = XEXP (addr, 0);
else if (GET_CODE (XEXP (addr, 1)) == REG)
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 0)))
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 1)))
addr = XEXP (addr, 0);
else
gcc_unreachable ();
}
gcc_assert (GET_CODE (addr) == REG);
return addr;
}
/* Output assembler code to perform a 32-bit 3-operand add. */
const char *
output_addsi3 (rtx *operands)
{
if (! operands_match_p (operands[0], operands[1]))
{
if (!ADDRESS_REG_P (operands[1]))
{
rtx tmp = operands[1];
operands[1] = operands[2];
operands[2] = tmp;
}
/* These insns can result from reloads to access
stack slots over 64k from the frame pointer. */
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
return "move%.l %2,%0\n\tadd%.l %1,%0";
if (GET_CODE (operands[2]) == REG)
return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
}
if (GET_CODE (operands[2]) == CONST_INT)
{
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
return "addq%.l %2,%0";
if (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) >= -8)
{
operands[2] = GEN_INT (- INTVAL (operands[2]));
return "subq%.l %2,%0";
}
/* On the CPU32 it is faster to use two addql instructions to
add a small integer (8 < N <= 16) to a register.
Likewise for subql. */
if (TUNE_CPU32 && REG_P (operands[0]))
{
if (INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16)
{
operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
return "addq%.l #8,%0\n\taddq%.l %2,%0";
}
if (INTVAL (operands[2]) < -8
&& INTVAL (operands[2]) >= -16)
{
operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
return "subq%.l #8,%0\n\tsubq%.l %2,%0";
}
}
if (ADDRESS_REG_P (operands[0])
&& INTVAL (operands[2]) >= -0x8000
&& INTVAL (operands[2]) < 0x8000)
{
if (TUNE_68040)
return "add%.w %2,%0";
else
return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
}
}
return "add%.l %2,%0";
}
/* Store in cc_status the expressions that the condition codes will
describe after execution of an instruction whose pattern is EXP.
Do not alter them if the instruction would not alter the cc's. */
/* On the 68000, all the insns to store in an address register fail to
set the cc's. However, in some cases these instructions can make it
possibly invalid to use the saved cc's. In those cases we clear out
some or all of the saved cc's so they won't be used. */
void
notice_update_cc (rtx exp, rtx insn)
{
if (GET_CODE (exp) == SET)
{
if (GET_CODE (SET_SRC (exp)) == CALL)
CC_STATUS_INIT;
else if (ADDRESS_REG_P (SET_DEST (exp)))
{
if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
cc_status.value1 = 0;
if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
cc_status.value2 = 0;
}
/* fmoves to memory or data registers do not set the condition
codes. Normal moves _do_ set the condition codes, but not in
a way that is appropriate for comparison with 0, because -0.0
would be treated as a negative nonzero number. Note that it
isn't appropriate to conditionalize this restriction on
HONOR_SIGNED_ZEROS because that macro merely indicates whether
we care about the difference between -0.0 and +0.0. */
else if (!FP_REG_P (SET_DEST (exp))
&& SET_DEST (exp) != cc0_rtx
&& (FP_REG_P (SET_SRC (exp))
|| GET_CODE (SET_SRC (exp)) == FIX
|| FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
CC_STATUS_INIT;
/* A pair of move insns doesn't produce a useful overall cc. */
else if (!FP_REG_P (SET_DEST (exp))
&& !FP_REG_P (SET_SRC (exp))
&& GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
&& (GET_CODE (SET_SRC (exp)) == REG
|| GET_CODE (SET_SRC (exp)) == MEM
|| GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
CC_STATUS_INIT;
else if (SET_DEST (exp) != pc_rtx)
{
cc_status.flags = 0;
cc_status.value1 = SET_DEST (exp);
cc_status.value2 = SET_SRC (exp);
}
}
else if (GET_CODE (exp) == PARALLEL
&& GET_CODE (XVECEXP (exp, 0, 0)) == SET)
{
rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
rtx src = SET_SRC (XVECEXP (exp, 0, 0));
if (ADDRESS_REG_P (dest))
CC_STATUS_INIT;
else if (dest != pc_rtx)
{
cc_status.flags = 0;
cc_status.value1 = dest;
cc_status.value2 = src;
}
}
else
CC_STATUS_INIT;
if (cc_status.value2 != 0
&& ADDRESS_REG_P (cc_status.value2)
&& GET_MODE (cc_status.value2) == QImode)
CC_STATUS_INIT;
if (cc_status.value2 != 0)
switch (GET_CODE (cc_status.value2))
{
case ASHIFT: case ASHIFTRT: case LSHIFTRT:
case ROTATE: case ROTATERT:
/* These instructions always clear the overflow bit, and set
the carry to the bit shifted out. */
cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
break;
case PLUS: case MINUS: case MULT:
case DIV: case UDIV: case MOD: case UMOD: case NEG:
if (GET_MODE (cc_status.value2) != VOIDmode)
cc_status.flags |= CC_NO_OVERFLOW;
break;
case ZERO_EXTEND:
/* (SET r1 (ZERO_EXTEND r2)) on this machine
ends with a move insn moving r2 in r2's mode.
Thus, the cc's are set for r2.
This can set N bit spuriously. */
cc_status.flags |= CC_NOT_NEGATIVE;
default:
break;
}
if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
&& cc_status.value2
&& reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
cc_status.value2 = 0;
/* Check for PRE_DEC in dest modifying a register used in src. */
if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
&& GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
&& cc_status.value2
&& reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
cc_status.value2))
cc_status.value2 = 0;
if (((cc_status.value1 && FP_REG_P (cc_status.value1))
|| (cc_status.value2 && FP_REG_P (cc_status.value2))))
cc_status.flags = CC_IN_68881;
if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
&& GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
{
cc_status.flags = CC_IN_68881;
if (!FP_REG_P (XEXP (cc_status.value2, 0))
&& FP_REG_P (XEXP (cc_status.value2, 1)))
cc_status.flags |= CC_REVERSED;
}
}
const char *
output_move_const_double (rtx *operands)
{
int code = standard_68881_constant_p (operands[1]);
if (code != 0)
{
static char buf[40];
sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
return buf;
}
return "fmove%.d %1,%0";
}
const char *
output_move_const_single (rtx *operands)
{
int code = standard_68881_constant_p (operands[1]);
if (code != 0)
{
static char buf[40];
sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
return buf;
}
return "fmove%.s %f1,%0";
}
/* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
from the "fmovecr" instruction.
The value, anded with 0xff, gives the code to use in fmovecr
to get the desired constant. */
/* This code has been fixed for cross-compilation. */
static int inited_68881_table = 0;
static const char *const strings_68881[7] = {
"0.0",
"1.0",
"10.0",
"100.0",
"10000.0",
"1e8",
"1e16"
};
static const int codes_68881[7] = {
0x0f,
0x32,
0x33,
0x34,
0x35,
0x36,
0x37
};
REAL_VALUE_TYPE values_68881[7];
/* Set up values_68881 array by converting the decimal values
strings_68881 to binary. */
void
init_68881_table (void)
{
int i;
REAL_VALUE_TYPE r;
machine_mode mode;
mode = SFmode;
for (i = 0; i < 7; i++)
{
if (i == 6)
mode = DFmode;
r = REAL_VALUE_ATOF (strings_68881[i], mode);
values_68881[i] = r;
}
inited_68881_table = 1;
}
int
standard_68881_constant_p (rtx x)
{
const REAL_VALUE_TYPE *r;
int i;
/* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
used at all on those chips. */
if (TUNE_68040_60)
return 0;
if (! inited_68881_table)
init_68881_table ();
r = CONST_DOUBLE_REAL_VALUE (x);
/* Use real_identical instead of real_equal so that -0.0 is rejected. */
for (i = 0; i < 6; i++)
{
if (real_identical (r, &values_68881[i]))
return (codes_68881[i]);
}
if (GET_MODE (x) == SFmode)
return 0;
if (real_equal (r, &values_68881[6]))
return (codes_68881[6]);
/* larger powers of ten in the constants ram are not used
because they are not equal to a `double' C constant. */
return 0;
}
/* If X is a floating-point constant, return the logarithm of X base 2,
or 0 if X is not a power of 2. */
int
floating_exact_log2 (rtx x)
{
const REAL_VALUE_TYPE *r;
REAL_VALUE_TYPE r1;
int exp;
r = CONST_DOUBLE_REAL_VALUE (x);
if (real_less (r, &dconst1))
return 0;
exp = real_exponent (r);
real_2expN (&r1, exp, DFmode);
if (real_equal (&r1, r))
return exp;
return 0;
}
/* A C compound statement to output to stdio stream STREAM the
assembler syntax for an instruction operand X. X is an RTL
expression.
CODE is a value that can be used to specify one of several ways
of printing the operand. It is used when identical operands
must be printed differently depending on the context. CODE
comes from the `%' specification that was used to request
printing of the operand. If the specification was just `%DIGIT'
then CODE is 0; if the specification was `%LTR DIGIT' then CODE
is the ASCII code for LTR.
If X is a register, this macro should print the register's name.
The names can be found in an array `reg_names' whose type is
`char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
When the machine description has a specification `%PUNCT' (a `%'
followed by a punctuation character), this macro is called with
a null pointer for X and the punctuation character for CODE.
The m68k specific codes are:
'.' for dot needed in Motorola-style opcode names.
'-' for an operand pushing on the stack:
sp@-, -(sp) or -(%sp) depending on the style of syntax.
'+' for an operand pushing on the stack:
sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
'@' for a reference to the top word on the stack:
sp@, (sp) or (%sp) depending on the style of syntax.
'#' for an immediate operand prefix (# in MIT and Motorola syntax
but & in SGS syntax).
'!' for the cc register (used in an `and to cc' insn).
'$' for the letter `s' in an op code, but only on the 68040.
'&' for the letter `d' in an op code, but only on the 68040.
'/' for register prefix needed by longlong.h.
'?' for m68k_library_id_string
'b' for byte insn (no effect, on the Sun; this is for the ISI).
'd' to force memory addressing to be absolute, not relative.
'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
or print pair of registers as rx:ry.
'p' print an address with @PLTPC attached, but only if the operand
is not locally-bound. */
void
print_operand (FILE *file, rtx op, int letter)
{
if (letter == '.')
{
if (MOTOROLA)
fprintf (file, ".");
}
else if (letter == '#')
asm_fprintf (file, "%I");
else if (letter == '-')
asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
else if (letter == '+')
asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
else if (letter == '@')
asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
else if (letter == '!')
asm_fprintf (file, "%Rfpcr");
else if (letter == '$')
{
if (TARGET_68040)
fprintf (file, "s");
}
else if (letter == '&')
{
if (TARGET_68040)
fprintf (file, "d");
}
else if (letter == '/')
asm_fprintf (file, "%R");
else if (letter == '?')
asm_fprintf (file, m68k_library_id_string);
else if (letter == 'p')
{
output_addr_const (file, op);
if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
fprintf (file, "@PLTPC");
}
else if (GET_CODE (op) == REG)
{
if (letter == 'R')
/* Print out the second register name of a register pair.
I.e., R (6) => 7. */
fputs (M68K_REGNAME(REGNO (op) + 1), file);
else
fputs (M68K_REGNAME(REGNO (op)), file);
}
else if (GET_CODE (op) == MEM)
{
output_address (GET_MODE (op), XEXP (op, 0));
if (letter == 'd' && ! TARGET_68020
&& CONSTANT_ADDRESS_P (XEXP (op, 0))
&& !(GET_CODE (XEXP (op, 0)) == CONST_INT
&& INTVAL (XEXP (op, 0)) < 0x8000
&& INTVAL (XEXP (op, 0)) >= -0x8000))
fprintf (file, MOTOROLA ? ".l" : ":l");
}
else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
{
long l;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
}
else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
{
long l[3];
REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
}
else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
{
long l[2];
REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF);
}
else
{
/* Use `print_operand_address' instead of `output_addr_const'
to ensure that we print relevant PIC stuff. */
asm_fprintf (file, "%I");
if (TARGET_PCREL
&& (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
print_operand_address (file, op);
else
output_addr_const (file, op);
}
}
/* Return string for TLS relocation RELOC. */
static const char *
m68k_get_reloc_decoration (enum m68k_reloc reloc)
{
/* To my knowledge, !MOTOROLA assemblers don't support TLS. */
gcc_assert (MOTOROLA || reloc == RELOC_GOT);
switch (reloc)
{
case RELOC_GOT:
if (MOTOROLA)
{
if (flag_pic == 1 && TARGET_68020)
return "@GOT.w";
else
return "@GOT";
}
else
{
if (TARGET_68020)
{
switch (flag_pic)
{
case 1:
return ":w";
case 2:
return ":l";
default:
return "";
}
}
}
gcc_unreachable ();
case RELOC_TLSGD:
return "@TLSGD";
case RELOC_TLSLDM:
return "@TLSLDM";
case RELOC_TLSLDO:
return "@TLSLDO";
case RELOC_TLSIE:
return "@TLSIE";
case RELOC_TLSLE:
return "@TLSLE";
default:
gcc_unreachable ();
}
}
/* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
static bool
m68k_output_addr_const_extra (FILE *file, rtx x)
{
if (GET_CODE (x) == UNSPEC)
{
switch (XINT (x, 1))
{
case UNSPEC_RELOC16:
case UNSPEC_RELOC32:
output_addr_const (file, XVECEXP (x, 0, 0));
fputs (m68k_get_reloc_decoration
((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file);
return true;
default:
break;
}
}
return false;
}
/* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
static void
m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
gcc_assert (size == 4);
fputs ("\t.long\t", file);
output_addr_const (file, x);
fputs ("@TLSLDO+0x8000", file);
}
/* In the name of slightly smaller debug output, and to cater to
general assembler lossage, recognize various UNSPEC sequences
and turn them back into a direct symbol reference. */
static rtx
m68k_delegitimize_address (rtx orig_x)
{
rtx x;
struct m68k_address addr;
rtx unspec;
orig_x = delegitimize_mem_from_attrs (orig_x);
x = orig_x;
if (MEM_P (x))
x = XEXP (x, 0);
if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
return orig_x;
if (!m68k_decompose_address (GET_MODE (x), x, false, &addr)
|| addr.offset == NULL_RTX
|| GET_CODE (addr.offset) != CONST)
return orig_x;
unspec = XEXP (addr.offset, 0);
if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1)))
unspec = XEXP (unspec, 0);
if (GET_CODE (unspec) != UNSPEC
|| (XINT (unspec, 1) != UNSPEC_RELOC16
&& XINT (unspec, 1) != UNSPEC_RELOC32))
return orig_x;
x = XVECEXP (unspec, 0, 0);
gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF);
if (unspec != XEXP (addr.offset, 0))
x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
if (addr.index)
{
rtx idx = addr.index;
if (addr.scale != 1)
idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale));
x = gen_rtx_PLUS (Pmode, idx, x);
}
if (addr.base)
x = gen_rtx_PLUS (Pmode, addr.base, x);
if (MEM_P (orig_x))
x = replace_equiv_address_nv (orig_x, x);
return x;
}
/* A C compound statement to output to stdio stream STREAM the
assembler syntax for an instruction operand that is a memory
reference whose address is ADDR. ADDR is an RTL expression.
Note that this contains a kludge that knows that the only reason
we have an address (plus (label_ref...) (reg...)) when not generating
PIC code is in the insn before a tablejump, and we know that m68k.md
generates a label LInnn: on such an insn.
It is possible for PIC to generate a (plus (label_ref...) (reg...))
and we handle that just like we would a (plus (symbol_ref...) (reg...)).
This routine is responsible for distinguishing between -fpic and -fPIC
style relocations in an address. When generating -fpic code the
offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
-fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
void
print_operand_address (FILE *file, rtx addr)
{
struct m68k_address address;
if (!m68k_decompose_address (QImode, addr, true, &address))
gcc_unreachable ();
if (address.code == PRE_DEC)
fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
M68K_REGNAME (REGNO (address.base)));
else if (address.code == POST_INC)
fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
M68K_REGNAME (REGNO (address.base)));
else if (!address.base && !address.index)
{
/* A constant address. */
gcc_assert (address.offset == addr);
if (GET_CODE (addr) == CONST_INT)
{
/* (xxx).w or (xxx).l. */
if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
else
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
}
else if (TARGET_PCREL)
{
/* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
fputc ('(', file);
output_addr_const (file, addr);
asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
}
else
{
/* (xxx).l. We need a special case for SYMBOL_REF if the symbol
name ends in `.<letter>', as the last 2 characters can be
mistaken as a size suffix. Put the name in parentheses. */
if (GET_CODE (addr) == SYMBOL_REF
&& strlen (XSTR (addr, 0)) > 2
&& XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
{
putc ('(', file);
output_addr_const (file, addr);
putc (')', file);
}
else
output_addr_const (file, addr);
}
}
else
{
int labelno;
/* If ADDR is a (d8,pc,Xn) address, this is the number of the
label being accessed, otherwise it is -1. */
labelno = (address.offset
&& !address.base
&& GET_CODE (address.offset) == LABEL_REF
? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
: -1);
if (MOTOROLA)
{
/* Print the "offset(base" component. */
if (labelno >= 0)
asm_fprintf (file, "%LL%d(%Rpc,", labelno);
else
{
if (address.offset)
output_addr_const (file, address.offset);
putc ('(', file);
if (address.base)
fputs (M68K_REGNAME (REGNO (address.base)), file);
}
/* Print the ",index" component, if any. */
if (address.index)
{
if (address.base)
putc (',', file);
fprintf (file, "%s.%c",
M68K_REGNAME (REGNO (address.index)),
GET_MODE (address.index) == HImode ? 'w' : 'l');
if (address.scale != 1)
fprintf (file, "*%d", address.scale);
}
putc (')', file);
}
else /* !MOTOROLA */
{
if (!address.offset && !address.index)
fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
else
{
/* Print the "base@(offset" component. */
if (labelno >= 0)
asm_fprintf (file, "%Rpc@(%LL%d", labelno);
else
{
if (address.base)
fputs (M68K_REGNAME (REGNO (address.base)), file);
fprintf (file, "@(");
if (address.offset)
output_addr_const (file, address.offset);
}
/* Print the ",index" component, if any. */
if (address.index)
{
fprintf (file, ",%s:%c",
M68K_REGNAME (REGNO (address.index)),
GET_MODE (address.index) == HImode ? 'w' : 'l');
if (address.scale != 1)
fprintf (file, ":%d", address.scale);
}
putc (')', file);
}
}
}
}
/* Check for cases where a clr insns can be omitted from code using
strict_low_part sets. For example, the second clrl here is not needed:
clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
insn we are checking for redundancy. TARGET is the register set by the
clear insn. */
bool
strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn,
rtx target)
{
rtx_insn *p = first_insn;
while ((p = PREV_INSN (p)))
{
if (NOTE_INSN_BASIC_BLOCK_P (p))
return false;
if (NOTE_P (p))
continue;
/* If it isn't an insn, then give up. */
if (!INSN_P (p))
return false;
if (reg_set_p (target, p))
{
rtx set = single_set (p);
rtx dest;
/* If it isn't an easy to recognize insn, then give up. */
if (! set)
return false;
dest = SET_DEST (set);
/* If this sets the entire target register to zero, then our
first_insn is redundant. */
if (rtx_equal_p (dest, target)
&& SET_SRC (set) == const0_rtx)
return true;
else if (GET_CODE (dest) == STRICT_LOW_PART
&& GET_CODE (XEXP (dest, 0)) == REG
&& REGNO (XEXP (dest, 0)) == REGNO (target)
&& (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
<= GET_MODE_SIZE (mode)))
/* This is a strict low part set which modifies less than
we are using, so it is safe. */
;
else
return false;
}
}
return false;
}
/* Operand predicates for implementing asymmetric pc-relative addressing
on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
when used as a source operand, but not as a destination operand.
We model this by restricting the meaning of the basic predicates
(general_operand, memory_operand, etc) to forbid the use of this
addressing mode, and then define the following predicates that permit
this addressing mode. These predicates can then be used for the
source operands of the appropriate instructions.
n.b. While it is theoretically possible to change all machine patterns
to use this addressing more where permitted by the architecture,
it has only been implemented for "common" cases: SImode, HImode, and
QImode operands, and only for the principle operations that would
require this addressing mode: data movement and simple integer operations.
In parallel with these new predicates, two new constraint letters
were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
In the pcrel case 's' is only valid in combination with 'a' registers.
See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
of how these constraints are used.
The use of these predicates is strictly optional, though patterns that
don't will cause an extra reload register to be allocated where one
was not necessary:
lea (abc:w,%pc),%a0 ; need to reload address
moveq &1,%d1 ; since write to pc-relative space
movel %d1,%a0@ ; is not allowed
...
lea (abc:w,%pc),%a1 ; no need to reload address here
movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
For more info, consult tiemann@cygnus.com.
All of the ugliness with predicates and constraints is due to the
simple fact that the m68k does not allow a pc-relative addressing
mode as a destination. gcc does not distinguish between source and
destination addresses. Hence, if we claim that pc-relative address
modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
end up with invalid code. To get around this problem, we left
pc-relative modes as invalid addresses, and then added special
predicates and constraints to accept them.
A cleaner way to handle this is to modify gcc to distinguish
between source and destination addresses. We can then say that
pc-relative is a valid source address but not a valid destination
address, and hopefully avoid a lot of the predicate and constraint
hackery. Unfortunately, this would be a pretty big change. It would
be a useful change for a number of ports, but there aren't any current
plans to undertake this.
***************************************************************************/
const char *
output_andsi3 (rtx *operands)
{
int logval;
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) | 0xffff) == -1
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
if (GET_CODE (operands[0]) != REG)
operands[0] = adjust_address (operands[0], HImode, 2);
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (operands[2] == const0_rtx)
return "clr%.w %0";
return "and%.w %2,%0";
}
if (GET_CODE (operands[2]) == CONST_INT
&& (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
{
if (DATA_REG_P (operands[0]))
operands[1] = GEN_INT (logval);
else
{
operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
/* This does not set condition codes in a standard way. */
CC_STATUS_INIT;
return "bclr %1,%0";
}
return "and%.l %2,%0";
}
const char *
output_iorsi3 (rtx *operands)
{
register int logval;
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) >> 16 == 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
if (GET_CODE (operands[0]) != REG)
operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (INTVAL (operands[2]) == 0xffff)
return "mov%.w %2,%0";
return "or%.w %2,%0";
}
if (GET_CODE (operands[2]) == CONST_INT
&& (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
{
if (DATA_REG_P (operands[0]))
operands[1] = GEN_INT (logval);
else
{
operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
return "bset %1,%0";
}
return "or%.l %2,%0";
}
const char *
output_xorsi3 (rtx *operands)
{
register int logval;
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) >> 16 == 0
&& (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
&& !TARGET_COLDFIRE)
{
if (! DATA_REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
if (INTVAL (operands[2]) == 0xffff)
return "not%.w %0";
return "eor%.w %2,%0";
}
if (GET_CODE (operands[2]) == CONST_INT
&& (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
{
if (DATA_REG_P (operands[0]))
operands[1] = GEN_INT (logval);
else
{
operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
operands[1] = GEN_INT (logval % 8);
}
CC_STATUS_INIT;
return "bchg %1,%0";
}
return "eor%.l %2,%0";
}
/* Return the instruction that should be used for a call to address X,
which is known to be in operand 0. */
const char *
output_call (rtx x)
{
if (symbolic_operand (x, VOIDmode))
return m68k_symbolic_call;
else
return "jsr %a0";
}
/* Likewise sibling calls. */
const char *
output_sibcall (rtx x)
{
if (symbolic_operand (x, VOIDmode))
return m68k_symbolic_jump;
else
return "jmp %a0";
}
static void
m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
rtx this_slot, offset, addr, mem, tmp;
rtx_insn *insn;
/* Avoid clobbering the struct value reg by using the
static chain reg as a temporary. */
tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
/* Pretend to be a post-reload pass while generating rtl. */
reload_completed = 1;
/* The "this" pointer is stored at 4(%sp). */
this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode,
stack_pointer_rtx, 4));
/* Add DELTA to THIS. */
if (delta != 0)
{
/* Make the offset a legitimate operand for memory addition. */
offset = GEN_INT (delta);
if ((delta < -8 || delta > 8)
&& (TARGET_COLDFIRE || USE_MOVQ (delta)))
{
emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
offset = gen_rtx_REG (Pmode, D0_REG);
}
emit_insn (gen_add3_insn (copy_rtx (this_slot),
copy_rtx (this_slot), offset));
}
/* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
if (vcall_offset != 0)
{
/* Set the static chain register to *THIS. */
emit_move_insn (tmp, this_slot);
emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
/* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
addr = plus_constant (Pmode, tmp, vcall_offset);
if (!m68k_legitimate_address_p (Pmode, addr, true))
{
emit_insn (gen_rtx_SET (tmp, addr));
addr = tmp;
}
/* Load the offset into %d0 and add it to THIS. */
emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
gen_rtx_MEM (Pmode, addr));
emit_insn (gen_add3_insn (copy_rtx (this_slot),
copy_rtx (this_slot),
gen_rtx_REG (Pmode, D0_REG)));
}
/* Jump to the target function. Use a sibcall if direct jumps are
allowed, otherwise load the address into a register first. */
mem = DECL_RTL (function);
if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
{
gcc_assert (flag_pic);
if (!TARGET_SEP_DATA)
{
/* Use the static chain register as a temporary (call-clobbered)
GOT pointer for this function. We can use the static chain
register because it isn't live on entry to the thunk. */
SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
emit_insn (gen_load_got (pic_offset_table_rtx));
}
legitimize_pic_address (XEXP (mem, 0), Pmode, tmp);
mem = replace_equiv_address (mem, tmp);
}
insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
SIBLING_CALL_P (insn) = 1;
/* Run just enough of rest_of_compilation. */
insn = get_insns ();
split_all_insns_noflow ();
final_start_function (insn, file, 1);
final (insn, file, 1);
final_end_function ();
/* Clean up the vars set above. */
reload_completed = 0;
/* Restore the original PIC register. */
if (flag_pic)
SET_REGNO (pic_offset_table_rtx, PIC_REG);
}
/* Worker function for TARGET_STRUCT_VALUE_RTX. */
static rtx
m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
int incoming ATTRIBUTE_UNUSED)
{
return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
}
/* Return nonzero if register old_reg can be renamed to register new_reg. */
int
m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
unsigned int new_reg)
{
/* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be
call-clobbered. */
if ((m68k_get_function_kind (current_function_decl)
== m68k_fk_interrupt_handler)
&& !df_regs_ever_live_p (new_reg))
return 0;
return 1;
}
/* Implement TARGET_HARD_REGNO_NREGS.
On the m68k, ordinary registers hold 32 bits worth;
for the 68881 registers, a single register is always enough for
anything that can be stored in them at all. */
static unsigned int
m68k_hard_regno_nregs (unsigned int regno, machine_mode mode)
{
if (regno >= 16)
return GET_MODE_NUNITS (mode);
return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
}
/* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
registers can hold any mode, but restrict the 68881 registers to
floating-point modes. */
static bool
m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (DATA_REGNO_P (regno))
{
/* Data Registers, can hold aggregate if fits in. */
if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
return true;
}
else if (ADDRESS_REGNO_P (regno))
{
if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
return true;
}
else if (FP_REGNO_P (regno))
{
/* FPU registers, hold float or complex float of long double or
smaller. */
if ((GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
&& GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
return true;
}
return false;
}
/* Implement TARGET_MODES_TIEABLE_P. */
static bool
m68k_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
return (!TARGET_HARD_FLOAT
|| ((GET_MODE_CLASS (mode1) == MODE_FLOAT
|| GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)
== (GET_MODE_CLASS (mode2) == MODE_FLOAT
|| GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT)));
}
/* Implement SECONDARY_RELOAD_CLASS. */
enum reg_class
m68k_secondary_reload_class (enum reg_class rclass,
machine_mode mode, rtx x)
{
int regno;
regno = true_regnum (x);
/* If one operand of a movqi is an address register, the other
operand must be a general register or constant. Other types
of operand must be reloaded through a data register. */
if (GET_MODE_SIZE (mode) == 1
&& reg_classes_intersect_p (rclass, ADDR_REGS)
&& !(INT_REGNO_P (regno) || CONSTANT_P (x)))
return DATA_REGS;
/* PC-relative addresses must be loaded into an address register first. */
if (TARGET_PCREL
&& !reg_class_subset_p (rclass, ADDR_REGS)
&& symbolic_operand (x, VOIDmode))
return ADDR_REGS;
return NO_REGS;
}
/* Implement PREFERRED_RELOAD_CLASS. */
enum reg_class
m68k_preferred_reload_class (rtx x, enum reg_class rclass)
{
enum reg_class secondary_class;
/* If RCLASS might need a secondary reload, try restricting it to
a class that doesn't. */
secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
if (secondary_class != NO_REGS
&& reg_class_subset_p (secondary_class, rclass))
return secondary_class;
/* Prefer to use moveq for in-range constants. */
if (GET_CODE (x) == CONST_INT
&& reg_class_subset_p (DATA_REGS, rclass)
&& IN_RANGE (INTVAL (x), -0x80, 0x7f))
return DATA_REGS;
/* ??? Do we really need this now? */
if (GET_CODE (x) == CONST_DOUBLE
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
{
if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
return FP_REGS;
return NO_REGS;
}
return rclass;
}
/* Return floating point values in a 68881 register. This makes 68881 code
a little bit faster. It also makes -msoft-float code incompatible with
hard-float code, so people have to be careful not to mix the two.
For ColdFire it was decided the ABI incompatibility is undesirable.
If there is need for a hard-float ABI it is probably worth doing it
properly and also passing function arguments in FP registers. */
rtx
m68k_libcall_value (machine_mode mode)
{
switch (mode) {
case E_SFmode:
case E_DFmode:
case E_XFmode:
if (TARGET_68881)
return gen_rtx_REG (mode, FP0_REG);
break;
default:
break;
}
return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
}
/* Location in which function value is returned.
NOTE: Due to differences in ABIs, don't call this function directly,
use FUNCTION_VALUE instead. */
rtx
m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
{
machine_mode mode;
mode = TYPE_MODE (valtype);
switch (mode) {
case E_SFmode:
case E_DFmode:
case E_XFmode:
if (TARGET_68881)
return gen_rtx_REG (mode, FP0_REG);
break;
default:
break;
}
/* If the function returns a pointer, push that into %a0. */
if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
/* For compatibility with the large body of existing code which
does not always properly declare external functions returning
pointer types, the m68k/SVR4 convention is to copy the value
returned for pointer functions from a0 to d0 in the function
epilogue, so that callers that have neglected to properly
declare the callee can still find the correct return value in
d0. */
return gen_rtx_PARALLEL
(mode,
gen_rtvec (2,
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode, A0_REG),
const0_rtx),
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode, D0_REG),
const0_rtx)));
else if (POINTER_TYPE_P (valtype))
return gen_rtx_REG (mode, A0_REG);
else
return gen_rtx_REG (mode, D0_REG);
}
/* Worker function for TARGET_RETURN_IN_MEMORY. */
#if M68K_HONOR_TARGET_STRICT_ALIGNMENT
static bool
m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
{
machine_mode mode = TYPE_MODE (type);
if (mode == BLKmode)
return true;
/* If TYPE's known alignment is less than the alignment of MODE that
would contain the structure, then return in memory. We need to
do so to maintain the compatibility between code compiled with
-mstrict-align and that compiled with -mno-strict-align. */
if (AGGREGATE_TYPE_P (type)
&& TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
return true;
return false;
}
#endif
/* CPU to schedule the program for. */
enum attr_cpu m68k_sched_cpu;
/* MAC to schedule the program for. */
enum attr_mac m68k_sched_mac;
/* Operand type. */
enum attr_op_type
{
/* No operand. */
OP_TYPE_NONE,
/* Integer register. */
OP_TYPE_RN,
/* FP register. */
OP_TYPE_FPN,
/* Implicit mem reference (e.g. stack). */
OP_TYPE_MEM1,
/* Memory without offset or indexing. EA modes 2, 3 and 4. */
OP_TYPE_MEM234,
/* Memory with offset but without indexing. EA mode 5. */
OP_TYPE_MEM5,
/* Memory with indexing. EA mode 6. */
OP_TYPE_MEM6,
/* Memory referenced by absolute address. EA mode 7. */
OP_TYPE_MEM7,
/* Immediate operand that doesn't require extension word. */
OP_TYPE_IMM_Q,
/* Immediate 16 bit operand. */
OP_TYPE_IMM_W,
/* Immediate 32 bit operand. */
OP_TYPE_IMM_L
};
/* Return type of memory ADDR_RTX refers to. */
static enum attr_op_type
sched_address_type (machine_mode mode, rtx addr_rtx)
{
struct m68k_address address;
if (symbolic_operand (addr_rtx, VOIDmode))
return OP_TYPE_MEM7;
if (!m68k_decompose_address (mode, addr_rtx,
reload_completed, &address))
{
gcc_assert (!reload_completed);
/* Reload will likely fix the address to be in the register. */
return OP_TYPE_MEM234;
}
if (address.scale != 0)
return OP_TYPE_MEM6;
if (address.base != NULL_RTX)
{
if (address.offset == NULL_RTX)
return OP_TYPE_MEM234;
return OP_TYPE_MEM5;
}
gcc_assert (address.offset != NULL_RTX);
return OP_TYPE_MEM7;
}
/* Return X or Y (depending on OPX_P) operand of INSN. */
static rtx
sched_get_operand (rtx_insn *insn, bool opx_p)
{
int i;
if (recog_memoized (insn) < 0)
gcc_unreachable ();
extract_constrain_insn_cached (insn);
if (opx_p)
i = get_attr_opx (insn);
else
i = get_attr_opy (insn);
if (i >= recog_data.n_operands)
return NULL;
return recog_data.operand[i];
}
/* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
If ADDRESS_P is true, return type of memory location operand refers to. */
static enum attr_op_type
sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
{
rtx op;
op = sched_get_operand (insn, opx_p);
if (op == NULL)
{
gcc_assert (!reload_completed);
return OP_TYPE_RN;
}
if (address_p)
return sched_address_type (QImode, op);
if (memory_operand (op, VOIDmode))
return sched_address_type (GET_MODE (op), XEXP (op, 0));
if (register_operand (op, VOIDmode))
{
if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op)))
|| (reload_completed && FP_REG_P (op)))
return OP_TYPE_FPN;
return OP_TYPE_RN;
}
if (GET_CODE (op) == CONST_INT)
{
int ival;
ival = INTVAL (op);
/* Check for quick constants. */
switch (get_attr_type (insn))
{
case TYPE_ALUQ_L:
if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1))
return OP_TYPE_IMM_Q;
gcc_assert (!reload_completed);
break;
case TYPE_MOVEQ_L:
if (USE_MOVQ (ival))
return OP_TYPE_IMM_Q;
gcc_assert (!reload_completed);
break;
case TYPE_MOV3Q_L:
if (valid_mov3q_const (ival))
return OP_TYPE_IMM_Q;
gcc_assert (!reload_completed);
break;
default:
break;
}
if (IN_RANGE (ival, -0x8000, 0x7fff))
return OP_TYPE_IMM_W;
return OP_TYPE_IMM_L;
}
if (GET_CODE (op) == CONST_DOUBLE)
{
switch (GET_MODE (op))
{
case E_SFmode:
return OP_TYPE_IMM_W;
case E_VOIDmode:
case E_DFmode:
return OP_TYPE_IMM_L;
default:
gcc_unreachable ();
}
}
if (GET_CODE (op) == CONST
|| symbolic_operand (op, VOIDmode)
|| LABEL_P (op))
{
switch (GET_MODE (op))
{
case E_QImode:
return OP_TYPE_IMM_Q;
case E_HImode:
return OP_TYPE_IMM_W;
case E_SImode:
return OP_TYPE_IMM_L;
default:
if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
/* Just a guess. */
return OP_TYPE_IMM_W;
return OP_TYPE_IMM_L;
}
}
gcc_assert (!reload_completed);
if (FLOAT_MODE_P (GET_MODE (op)))
return OP_TYPE_FPN;
return OP_TYPE_RN;
}
/* Implement opx_type attribute.
Return type of INSN's operand X.
If ADDRESS_P is true, return type of memory location operand refers to. */
enum attr_opx_type
m68k_sched_attr_opx_type (rtx_insn *insn, int address_p)
{
switch (sched_attr_op_type (insn, true, address_p != 0))
{
case OP_TYPE_RN:
return OPX_TYPE_RN;
case OP_TYPE_FPN:
return OPX_TYPE_FPN;
case OP_TYPE_MEM1:
return OPX_TYPE_MEM1;
case OP_TYPE_MEM234:
return OPX_TYPE_MEM234;
case OP_TYPE_MEM5:
return OPX_TYPE_MEM5;
case OP_TYPE_MEM6:
return OPX_TYPE_MEM6;
case OP_TYPE_MEM7:
return OPX_TYPE_MEM7;
case OP_TYPE_IMM_Q:
return OPX_TYPE_IMM_Q;
case OP_TYPE_IMM_W:
return OPX_TYPE_IMM_W;
case OP_TYPE_IMM_L:
return OPX_TYPE_IMM_L;
default:
gcc_unreachable ();
}
}
/* Implement opy_type attribute.
Return type of INSN's operand Y.
If ADDRESS_P is true, return type of memory location operand refers to. */
enum attr_opy_type
m68k_sched_attr_opy_type (rtx_insn *insn, int address_p)
{
switch (sched_attr_op_type (insn, false, address_p != 0))
{
case OP_TYPE_RN:
return OPY_TYPE_RN;
case OP_TYPE_FPN:
return OPY_TYPE_FPN;
case OP_TYPE_MEM1:
return OPY_TYPE_MEM1;
case OP_TYPE_MEM234:
return OPY_TYPE_MEM234;
case OP_TYPE_MEM5:
return OPY_TYPE_MEM5;
case OP_TYPE_MEM6:
return OPY_TYPE_MEM6;
case OP_TYPE_MEM7:
return OPY_TYPE_MEM7;
case OP_TYPE_IMM_Q:
return OPY_TYPE_IMM_Q;
case OP_TYPE_IMM_W:
return OPY_TYPE_IMM_W;
case OP_TYPE_IMM_L:
return OPY_TYPE_IMM_L;
default:
gcc_unreachable ();
}
}
/* Return size of INSN as int. */
static int
sched_get_attr_size_int (rtx_insn *insn)
{
int size;
switch (get_attr_type (insn))
{
case TYPE_IGNORE:
/* There should be no references to m68k_sched_attr_size for 'ignore'
instructions. */
gcc_unreachable ();
return 0;
case TYPE_MUL_L:
size = 2;
break;
default:
size = 1;
break;
}
switch (get_attr_opx_type (insn))
{
case OPX_TYPE_NONE:
case OPX_TYPE_RN:
case OPX_TYPE_FPN:
case OPX_TYPE_MEM1:
case OPX_TYPE_MEM234:
case OPY_TYPE_IMM_Q:
break;
case OPX_TYPE_MEM5:
case OPX_TYPE_MEM6:
/* Here we assume that most absolute references are short. */
case OPX_TYPE_MEM7:
case OPY_TYPE_IMM_W:
++size;
break;
case OPY_TYPE_IMM_L:
size += 2;
break;
default:
gcc_unreachable ();
}
switch (get_attr_opy_type (insn))
{
case OPY_TYPE_NONE:
case OPY_TYPE_RN:
case OPY_TYPE_FPN:
case OPY_TYPE_MEM1:
case OPY_TYPE_MEM234:
case OPY_TYPE_IMM_Q:
break;
case OPY_TYPE_MEM5:
case OPY_TYPE_MEM6:
/* Here we assume that most absolute references are short. */
case OPY_TYPE_MEM7:
case OPY_TYPE_IMM_W:
++size;
break;
case OPY_TYPE_IMM_L:
size += 2;
break;
default:
gcc_unreachable ();
}
if (size > 3)
{
gcc_assert (!reload_completed);
size = 3;
}
return size;
}
/* Return size of INSN as attribute enum value. */
enum attr_size
m68k_sched_attr_size (rtx_insn *insn)
{
switch (sched_get_attr_size_int (insn))
{
case 1:
return SIZE_1;
case 2:
return SIZE_2;
case 3:
return SIZE_3;
default:
gcc_unreachable ();
}
}
/* Return operand X or Y (depending on OPX_P) of INSN,
if it is a MEM, or NULL overwise. */
static enum attr_op_type
sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p)
{
if (opx_p)
{
switch (get_attr_opx_type (insn))
{
case OPX_TYPE_NONE:
case OPX_TYPE_RN:
case OPX_TYPE_FPN:
case OPX_TYPE_IMM_Q:
case OPX_TYPE_IMM_W:
case OPX_TYPE_IMM_L:
return OP_TYPE_RN;
case OPX_TYPE_MEM1:
case OPX_TYPE_MEM234:
case OPX_TYPE_MEM5:
case OPX_TYPE_MEM7:
return OP_TYPE_MEM1;
case OPX_TYPE_MEM6:
return OP_TYPE_MEM6;
default:
gcc_unreachable ();
}
}
else
{
switch (get_attr_opy_type (insn))
{
case OPY_TYPE_NONE:
case OPY_TYPE_RN:
case OPY_TYPE_FPN:
case OPY_TYPE_IMM_Q:
case OPY_TYPE_IMM_W:
case OPY_TYPE_IMM_L:
return OP_TYPE_RN;
case OPY_TYPE_MEM1:
case OPY_TYPE_MEM234:
case OPY_TYPE_MEM5:
case OPY_TYPE_MEM7:
return OP_TYPE_MEM1;
case OPY_TYPE_MEM6:
return OP_TYPE_MEM6;
default:
gcc_unreachable ();
}
}
}
/* Implement op_mem attribute. */
enum attr_op_mem
m68k_sched_attr_op_mem (rtx_insn *insn)
{
enum attr_op_type opx;
enum attr_op_type opy;
opx = sched_get_opxy_mem_type (insn, true);
opy = sched_get_opxy_mem_type (insn, false);
if (opy == OP_TYPE_RN && opx == OP_TYPE_RN)
return OP_MEM_00;
if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1)
{
switch (get_attr_opx_access (insn))
{
case OPX_ACCESS_R:
return OP_MEM_10;
case OPX_ACCESS_W:
return OP_MEM_01;
case OPX_ACCESS_RW:
return OP_MEM_11;
default:
gcc_unreachable ();
}
}
if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6)
{
switch (get_attr_opx_access (insn))
{
case OPX_ACCESS_R:
return OP_MEM_I0;
case OPX_ACCESS_W:
return OP_MEM_0I;
case OPX_ACCESS_RW:
return OP_MEM_I1;
default:
gcc_unreachable ();
}
}
if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN)
return OP_MEM_10;
if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1)
{
switch (get_attr_opx_access (insn))
{
case OPX_ACCESS_W:
return OP_MEM_11;
default:
gcc_assert (!reload_completed);
return OP_MEM_11;
}
}
if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6)
{
switch (get_attr_opx_access (insn))
{
case OPX_ACCESS_W:
return OP_MEM_1I;
default:
gcc_assert (!reload_completed);
return OP_MEM_1I;
}
}
if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN)
return OP_MEM_I0;
if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1)
{
switch (get_attr_opx_access (insn))
{
case OPX_ACCESS_W:
return OP_MEM_I1;
default:
gcc_assert (!reload_completed);
return OP_MEM_I1;
}
}
gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6);
gcc_assert (!reload_completed);
return OP_MEM_I1;
}
/* Data for ColdFire V4 index bypass.
Producer modifies register that is used as index in consumer with
specified scale. */
static struct
{
/* Producer instruction. */
rtx pro;
/* Consumer instruction. */
rtx con;
/* Scale of indexed memory access within consumer.
Or zero if bypass should not be effective at the moment. */
int scale;
} sched_cfv4_bypass_data;
/* An empty state that is used in m68k_sched_adjust_cost. */
static state_t sched_adjust_cost_state;
/* Implement adjust_cost scheduler hook.
Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
static int
m68k_sched_adjust_cost (rtx_insn *insn, int, rtx_insn *def_insn, int cost,
unsigned int)
{
int delay;
if (recog_memoized (def_insn) < 0
|| recog_memoized (insn) < 0)
return cost;
if (sched_cfv4_bypass_data.scale == 1)
/* Handle ColdFire V4 bypass for indexed address with 1x scale. */
{
/* haifa-sched.c: insn_cost () calls bypass_p () just before
targetm.sched.adjust_cost (). Hence, we can be relatively sure
that the data in sched_cfv4_bypass_data is up to date. */
gcc_assert (sched_cfv4_bypass_data.pro == def_insn
&& sched_cfv4_bypass_data.con == insn);
if (cost < 3)
cost = 3;
sched_cfv4_bypass_data.pro = NULL;
sched_cfv4_bypass_data.con = NULL;
sched_cfv4_bypass_data.scale = 0;
}
else
gcc_assert (sched_cfv4_bypass_data.pro == NULL
&& sched_cfv4_bypass_data.con == NULL
&& sched_cfv4_bypass_data.scale == 0);
/* Don't try to issue INSN earlier than DFA permits.
This is especially useful for instructions that write to memory,
as their true dependence (default) latency is better to be set to 0
to workaround alias analysis limitations.
This is, in fact, a machine independent tweak, so, probably,
it should be moved to haifa-sched.c: insn_cost (). */
delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
if (delay > cost)
cost = delay;
return cost;
}
/* Return maximal number of insns that can be scheduled on a single cycle. */
static int
m68k_sched_issue_rate (void)
{
switch (m68k_sched_cpu)
{
case CPU_CFV1:
case CPU_CFV2:
case CPU_CFV3:
return 1;
case CPU_CFV4:
return 2;
default:
gcc_unreachable ();
return 0;
}
}
/* Maximal length of instruction for current CPU.
E.g. it is 3 for any ColdFire core. */
static int max_insn_size;
/* Data to model instruction buffer of CPU. */
struct _sched_ib
{
/* True if instruction buffer model is modeled for current CPU. */
bool enabled_p;
/* Size of the instruction buffer in words. */
int size;
/* Number of filled words in the instruction buffer. */
int filled;
/* Additional information about instruction buffer for CPUs that have
a buffer of instruction records, rather then a plain buffer
of instruction words. */
struct _sched_ib_records
{
/* Size of buffer in records. */
int n_insns;
/* Array to hold data on adjustments made to the size of the buffer. */
int *adjust;
/* Index of the above array. */
int adjust_index;
} records;
/* An insn that reserves (marks empty) one word in the instruction buffer. */
rtx insn;
};
static struct _sched_ib sched_ib;
/* ID of memory unit. */
static int sched_mem_unit_code;
/* Implementation of the targetm.sched.variable_issue () hook.
It is called after INSN was issued. It returns the number of insns
that can possibly get scheduled on the current cycle.
It is used here to determine the effect of INSN on the instruction
buffer. */
static int
m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
int sched_verbose ATTRIBUTE_UNUSED,
rtx_insn *insn, int can_issue_more)
{
int insn_size;
if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE)
{
switch (m68k_sched_cpu)
{
case CPU_CFV1:
case CPU_CFV2:
insn_size = sched_get_attr_size_int (insn);
break;
case CPU_CFV3:
insn_size = sched_get_attr_size_int (insn);
/* ColdFire V3 and V4 cores have instruction buffers that can
accumulate up to 8 instructions regardless of instructions'
sizes. So we should take care not to "prefetch" 24 one-word
or 12 two-words instructions.
To model this behavior we temporarily decrease size of the
buffer by (max_insn_size - insn_size) for next 7 instructions. */
{
int adjust;
adjust = max_insn_size - insn_size;
sched_ib.size -= adjust;
if (sched_ib.filled > sched_ib.size)
sched_ib.filled = sched_ib.size;
sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
}
++sched_ib.records.adjust_index;
if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
sched_ib.records.adjust_index = 0;
/* Undo adjustment we did 7 instructions ago. */
sched_ib.size
+= sched_ib.records.adjust[sched_ib.records.adjust_index];
break;
case CPU_CFV4:
gcc_assert (!sched_ib.enabled_p);
insn_size = 0;
break;
default:
gcc_unreachable ();
}
if (insn_size > sched_ib.filled)
/* Scheduling for register pressure does not always take DFA into
account. Workaround instruction buffer not being filled enough. */
{
gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
insn_size = sched_ib.filled;
}
--can_issue_more;
}
else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
|| asm_noperands (PATTERN (insn)) >= 0)
insn_size = sched_ib.filled;
else
insn_size = 0;
sched_ib.filled -= insn_size;
return can_issue_more;
}
/* Return how many instructions should scheduler lookahead to choose the
best one. */
static int
m68k_sched_first_cycle_multipass_dfa_lookahead (void)
{
return m68k_sched_issue_rate () - 1;
}
/* Implementation of targetm.sched.init_global () hook.
It is invoked once per scheduling pass and is used here
to initialize scheduler constants. */
static void
m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
int sched_verbose ATTRIBUTE_UNUSED,
int n_insns ATTRIBUTE_UNUSED)
{
/* Check that all instructions have DFA reservations and
that all instructions can be issued from a clean state. */
if (flag_checking)
{
rtx_insn *insn;
state_t state;
state = alloca (state_size ());
for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn))
{
if (INSN_P (insn) && recog_memoized (insn) >= 0)
{
gcc_assert (insn_has_dfa_reservation_p (insn));
state_reset (state);
if (state_transition (state, insn) >= 0)
gcc_unreachable ();
}
}
}
/* Setup target cpu. */
/* ColdFire V4 has a set of features to keep its instruction buffer full
(e.g., a separate memory bus for instructions) and, hence, we do not model
buffer for this CPU. */
sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4);
switch (m68k_sched_cpu)
{
case CPU_CFV4:
sched_ib.filled = 0;
/* FALLTHRU */
case CPU_CFV1:
case CPU_CFV2:
max_insn_size = 3;
sched_ib.records.n_insns = 0;
sched_ib.records.adjust = NULL;
break;
case CPU_CFV3:
max_insn_size = 3;
sched_ib.records.n_insns = 8;
sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns);
break;
default:
gcc_unreachable ();
}
sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
sched_adjust_cost_state = xmalloc (state_size ());
state_reset (sched_adjust_cost_state);
start_sequence ();
emit_insn (gen_ib ());
sched_ib.insn = get_insns ();
end_sequence ();
}
/* Scheduling pass is now finished. Free/reset static variables. */
static void
m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
int verbose ATTRIBUTE_UNUSED)
{
sched_ib.insn = NULL;
free (sched_adjust_cost_state);
sched_adjust_cost_state = NULL;
sched_mem_unit_code = 0;
free (sched_ib.records.adjust);
sched_ib.records.adjust = NULL;
sched_ib.records.n_insns = 0;
max_insn_size = 0;
}
/* Implementation of targetm.sched.init () hook.
It is invoked each time scheduler starts on the new block (basic block or
extended basic block). */
static void
m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
int sched_verbose ATTRIBUTE_UNUSED,
int n_insns ATTRIBUTE_UNUSED)
{
switch (m68k_sched_cpu)
{
case CPU_CFV1:
case CPU_CFV2:
sched_ib.size = 6;
break;
case CPU_CFV3:
sched_ib.size = sched_ib.records.n_insns * max_insn_size;
memset (sched_ib.records.adjust, 0,
sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
sched_ib.records.adjust_index = 0;
break;
case CPU_CFV4:
gcc_assert (!sched_ib.enabled_p);
sched_ib.size = 0;
break;
default:
gcc_unreachable ();
}
if (sched_ib.enabled_p)
/* haifa-sched.c: schedule_block () calls advance_cycle () just before
the first cycle. Workaround that. */
sched_ib.filled = -2;
}
/* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
It is invoked just before current cycle finishes and is used here
to track if instruction buffer got its two words this cycle. */
static void
m68k_sched_dfa_pre_advance_cycle (void)
{
if (!sched_ib.enabled_p)
return;
if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
{
sched_ib.filled += 2;
if (sched_ib.filled > sched_ib.size)
sched_ib.filled = sched_ib.size;
}
}
/* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
It is invoked just after new cycle begins and is used here
to setup number of filled words in the instruction buffer so that
instructions which won't have all their words prefetched would be
stalled for a cycle. */
static void
m68k_sched_dfa_post_advance_cycle (void)
{
int i;
if (!sched_ib.enabled_p)
return;
/* Setup number of prefetched instruction words in the instruction
buffer. */
i = max_insn_size - sched_ib.filled;
while (--i >= 0)
{
if (state_transition (curr_state, sched_ib.insn) >= 0)
/* Pick up scheduler state. */
++sched_ib.filled;
}
}
/* Return X or Y (depending on OPX_P) operand of INSN,
if it is an integer register, or NULL overwise. */
static rtx
sched_get_reg_operand (rtx_insn *insn, bool opx_p)
{
rtx op = NULL;
if (opx_p)
{
if (get_attr_opx_type (insn) == OPX_TYPE_RN)
{
op = sched_get_operand (insn, true);
gcc_assert (op != NULL);
if (!reload_completed && !REG_P (op))
return NULL;
}
}
else
{
if (get_attr_opy_type (insn) == OPY_TYPE_RN)
{
op = sched_get_operand (insn, false);
gcc_assert (op != NULL);
if (!reload_completed && !REG_P (op))
return NULL;
}
}
return op;
}
/* Return true, if X or Y (depending on OPX_P) operand of INSN
is a MEM. */
static bool
sched_mem_operand_p (rtx_insn *insn, bool opx_p)
{
switch (sched_get_opxy_mem_type (insn, opx_p))
{
case OP_TYPE_MEM1:
case OP_TYPE_MEM6:
return true;
default:
return false;
}
}
/* Return X or Y (depending on OPX_P) operand of INSN,
if it is a MEM, or NULL overwise. */
static rtx
sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p)
{
bool opx_p;
bool opy_p;
opx_p = false;
opy_p = false;
if (must_read_p)
{
opx_p = true;
opy_p = true;
}
if (must_write_p)
{
opx_p = true;
opy_p = false;
}
if (opy_p && sched_mem_operand_p (insn, false))
return sched_get_operand (insn, false);
if (opx_p && sched_mem_operand_p (insn, true))
return sched_get_operand (insn, true);
gcc_unreachable ();
return NULL;
}
/* Return non-zero if PRO modifies register used as part of
address in CON. */
int
m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con)
{
rtx pro_x;
rtx con_mem_read;
pro_x = sched_get_reg_operand (pro, true);
if (pro_x == NULL)
return 0;
con_mem_read = sched_get_mem_operand (con, true, false);
gcc_assert (con_mem_read != NULL);
if (reg_mentioned_p (pro_x, con_mem_read))
return 1;
return 0;
}
/* Helper function for m68k_sched_indexed_address_bypass_p.
if PRO modifies register used as index in CON,
return scale of indexed memory access in CON. Return zero overwise. */
static int
sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con)
{
rtx reg;
rtx mem;
struct m68k_address address;
reg = sched_get_reg_operand (pro, true);
if (reg == NULL)
return 0;
mem = sched_get_mem_operand (con, true, false);
gcc_assert (mem != NULL && MEM_P (mem));
if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
&address))
gcc_unreachable ();
if (REGNO (reg) == REGNO (address.index))
{
gcc_assert (address.scale != 0);
return address.scale;
}
return 0;
}
/* Return non-zero if PRO modifies register used
as index with scale 2 or 4 in CON. */
int
m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con)
{
gcc_assert (sched_cfv4_bypass_data.pro == NULL
&& sched_cfv4_bypass_data.con == NULL
&& sched_cfv4_bypass_data.scale == 0);
switch (sched_get_indexed_address_scale (pro, con))
{
case 1:
/* We can't have a variable latency bypass, so
remember to adjust the insn cost in adjust_cost hook. */
sched_cfv4_bypass_data.pro = pro;
sched_cfv4_bypass_data.con = con;
sched_cfv4_bypass_data.scale = 1;
return 0;
case 2:
case 4:
return 1;
default:
return 0;
}
}
/* We generate a two-instructions program at M_TRAMP :
movea.l &CHAIN_VALUE,%a0
jmp FNADDR
where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
static void
m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
{
rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
rtx mem;
gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM));
mem = adjust_address (m_tramp, HImode, 0);
emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));
mem = adjust_address (m_tramp, SImode, 2);
emit_move_insn (mem, chain_value);
mem = adjust_address (m_tramp, HImode, 6);
emit_move_insn (mem, GEN_INT(0x4EF9));
mem = adjust_address (m_tramp, SImode, 8);
emit_move_insn (mem, fnaddr);
FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0));
}
/* On the 68000, the RTS insn cannot pop anything.
On the 68010, the RTD insn may be used to pop them if the number
of args is fixed, but if the number is variable then the caller
must pop them all. RTD can't be used for library calls now
because the library is compiled with the Unix compiler.
Use of RTD is a selectable option, since it is incompatible with
standard Unix calling sequences. If the option is not selected,
the caller must always pop the args. */
static poly_int64
m68k_return_pops_args (tree fundecl, tree funtype, poly_int64 size)
{
return ((TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl) != IDENTIFIER_NODE)
&& (!stdarg_p (funtype)))
? (HOST_WIDE_INT) size : 0);
}
/* Make sure everything's fine if we *don't* have a given processor.
This assumes that putting a register in fixed_regs will keep the
compiler's mitts completely off it. We don't bother to zero it out
of register classes. */
static void
m68k_conditional_register_usage (void)
{
int i;
HARD_REG_SET x;
if (!TARGET_HARD_FLOAT)
{
COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (x, i))
fixed_regs[i] = call_used_regs[i] = 1;
}
if (flag_pic)
fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;
}
static void
m68k_init_sync_libfuncs (void)
{
init_sync_libfuncs (UNITS_PER_WORD);
}
/* Implements EPILOGUE_USES. All registers are live on exit from an
interrupt routine. */
bool
m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED)
{
return (reload_completed
&& (m68k_get_function_kind (current_function_decl)
== m68k_fk_interrupt_handler));
}
/* Implement TARGET_C_EXCESS_PRECISION.
Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
instructions, we get proper intermediate rounding, otherwise we
get extended precision results. */
static enum flt_eval_method
m68k_excess_precision (enum excess_precision_type type)
{
switch (type)
{
case EXCESS_PRECISION_TYPE_FAST:
/* The fastest type to promote to will always be the native type,
whether that occurs with implicit excess precision or
otherwise. */
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
case EXCESS_PRECISION_TYPE_STANDARD:
case EXCESS_PRECISION_TYPE_IMPLICIT:
/* Otherwise, the excess precision we want when we are
in a standards compliant mode, and the implicit precision we
provide can be identical. */
if (TARGET_68040 || ! TARGET_68881)
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE;
default:
gcc_unreachable ();
}
return FLT_EVAL_METHOD_UNPREDICTABLE;
}
/* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes
a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */
poly_int64
m68k_push_rounding (poly_int64 bytes)
{
if (TARGET_COLDFIRE)
return bytes;
return (bytes + 1) & ~1;
}
/* Implement TARGET_PROMOTE_FUNCTION_MODE. */
static machine_mode
m68k_promote_function_mode (const_tree type, machine_mode mode,
int *punsignedp ATTRIBUTE_UNUSED,
const_tree fntype ATTRIBUTE_UNUSED,
int for_return)
{
/* Promote libcall arguments narrower than int to match the normal C
ABI (for which promotions are handled via
TARGET_PROMOTE_PROTOTYPES). */
if (type == NULL_TREE && !for_return && (mode == QImode || mode == HImode))
return SImode;
return mode;
}
#include "gt-m68k.h"
|