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; Generated by "genstr" from the template "loongarch.opt.in"
; and definitions from "loongarch-strings".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
; if you change "loongarch.opt.in" or "loongarch-strings".
;
; Copyright (C) 2021-2022 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
;
; Variables (macros) that should be exported by loongarch.opt:
; la_opt_switches,
; la_opt_abi_base, la_opt_abi_ext,
; la_opt_cpu_arch, la_opt_cpu_tune,
; la_opt_fpu,
; la_cmodel.
HeaderInclude
config/loongarch/loongarch-opts.h
HeaderInclude
config/loongarch/loongarch-str.h
Variable
HOST_WIDE_INT la_opt_switches = 0
; ISA related options
;; Base ISA
Enum
Name(isa_base) Type(int)
Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
FPU types of LoongArch:
EnumValue
Enum(isa_ext_fpu) String(none) Value(ISA_EXT_NOFPU)
EnumValue
Enum(isa_ext_fpu) String(32) Value(ISA_EXT_FPU32)
EnumValue
Enum(isa_ext_fpu) String(64) Value(ISA_EXT_FPU64)
mfpu=
Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) Init(M_OPTION_NOT_SEEN)
-mfpu=FPU Generate code for the given FPU.
mfpu=0
Target RejectNegative Alias(mfpu=,none)
msoft-float
Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_SOFTF) Negative(msingle-float)
Prevent the use of all hardware floating-point instructions.
msingle-float
Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F32) Negative(mdouble-float)
Restrict the use of hardware floating-point instructions to 32-bit operations.
mdouble-float
Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(msoft-float)
Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
;; Base target models (implies ISA & tune parameters)
Enum
Name(cpu_type) Type(int)
LoongArch CPU types:
EnumValue
Enum(cpu_type) String(native) Value(CPU_NATIVE)
EnumValue
Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(la464) Value(CPU_LA464)
march=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPTION_NOT_SEEN)
-march=PROCESSOR Generate code for the given PROCESSOR ISA.
mtune=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) Init(M_OPTION_NOT_SEEN)
-mtune=PROCESSOR Generate optimized code for PROCESSOR.
; ABI related options
; (ISA constraints on ABI are handled dynamically)
;; Base ABI
Enum
Name(abi_base) Type(int)
Base ABI types for LoongArch:
EnumValue
Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D)
EnumValue
Enum(abi_base) String(lp64f) Value(ABI_BASE_LP64F)
EnumValue
Enum(abi_base) String(lp64s) Value(ABI_BASE_LP64S)
mabi=
Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_OPTION_NOT_SEEN)
-mabi=BASEABI Generate code that conforms to the given BASEABI.
;; ABI Extension
Variable
int la_opt_abi_ext = M_OPTION_NOT_SEEN
mbranch-cost=
Target RejectNegative Joined UInteger Var(loongarch_branch_cost)
-mbranch-cost=COST Set the cost of branches to roughly COST instructions.
mcheck-zero-division
Target Mask(CHECK_ZERO_DIV)
Trap on integer divide by zero.
mcond-move-int
Target Var(TARGET_COND_MOVE_INT) Init(1)
Conditional moves for integral are enabled.
mcond-move-float
Target Var(TARGET_COND_MOVE_FLOAT) Init(1)
Conditional moves for float are enabled.
mmemcpy
Target Mask(MEMCPY)
Prevent optimizing block moves, which is also the default behavior of -Os.
mstrict-align
Target Var(TARGET_STRICT_ALIGN) Init(0)
Do not generate unaligned memory accesses.
mmax-inline-memcpy-size=
Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024)
-mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024.
mexplicit-relocs
Target Var(TARGET_EXPLICIT_RELOCS) Init(HAVE_AS_EXPLICIT_RELOCS)
Use %reloc() assembly operators.
; The code model option names for -mcmodel.
Enum
Name(cmodel) Type(int)
The code model option names for -mcmodel:
EnumValue
Enum(cmodel) String(normal) Value(CMODEL_NORMAL)
EnumValue
Enum(cmodel) String(tiny) Value(CMODEL_TINY)
EnumValue
Enum(cmodel) String(tiny-static) Value(CMODEL_TINY_STATIC)
EnumValue
Enum(cmodel) String(large) Value(CMODEL_LARGE)
EnumValue
Enum(cmodel) String(extreme) Value(CMODEL_EXTREME)
mcmodel=
Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL)
Specify the code model.
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