path: root/gcc/ChangeLog

2024-01-11  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/thead.md: Add limits for splits.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

	PR middle-end/113322
	* expr.cc (do_store_flag): Don't try single bit tests with
	comparison on vector types.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/113301
	* match.pd (`1/x`): Delay signed case until late.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

	* doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
	and -msp8 to...
	(AVR Internal Options): ...this new @subsubsection.

2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/112918
	* lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
	(in_class_p): Restrict condition for narrowing class in case of
	allow_all_reload_class_changes_p.
	(process_alt_operands): Try to match operand without and with
	narrowing reg class.  Discourage narrowing the class.  Finish insn
	matching only if there is no class narrowing.
	(curr_insn_transform): Pass true to in_class_p for reg operand win.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112505
	* tree-vect-loop.cc (vectorizable_induction): Reject
	bit-precision induction.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113126
	* match.pd ((double)float CMP (double)float -> float CMP float):
	Make sure the boolean type is the same.
	* fold-const.cc (fold_binary_loc): Likewise.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/112636
	* tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
	estimate_numbers_of_iterations before querying
	get_max_loop_iterations_int.
	(pass_ch::execute): Initialize SCEV and loops appropriately.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

	* config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
	Reduced Tiny.
	* config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
	* doc/extend.texi (AVR Variable Attributes): Improve documentation
	of io, io_low and address attributes.
	* doc/invoke.texi (AVR Options): Add some anchors for external refs.
	* doc/avr-mmcu.texi: Rebuild.

2024-01-11  Yang Yujie  <yangyujie@loongson.cn>

	PR target/113233
	* config/loongarch/genopts/loongarch.opt.in: Mark options with
	the "Save" property.
	* config/loongarch/loongarch.opt: Same.
	* config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
	according to la_target.
	* config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
	RESTORE} for the la_target structure; Rename option conditions
	to have the same "la_" prefix.
	* config/loongarch/loongarch.h: Same.

2024-01-11  Pan Li  <pan2.li@intel.com>

	* loop-unroll.cc (insert_var_expansion_initialization): Leverage
	MODE_HAS_SIGNED_ZEROS for expansion variable initialization.

2024-01-11  Alex Coplan  <alex.coplan@arm.com>

	PR target/113077
	* config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
	fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
	(combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
	synthesize these if needed.  Update caller ...
	(ldp_bb_info::fuse_pair): ... here.
	(ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
	and either insn is frame-related.
	(find_trailing_add): Punt on frame-related insns.
	* config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
	REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.

2024-01-11  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc (mips_start_function_definition):
	Add ATTRIBUTE_UNUSED.

2024-01-11  Richard Biener  <rguenther@suse.de>

	PR middle-end/112740
	* expr.cc (store_constructor): Check the integer vector
	mask has a single bit per element before using sign-extension
	to expand an uniform vector.

2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
	preempt VLS on unknown NITERS loop.

2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>

	* doc/invoke.texi: Add -mevex512.

2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
	(*nor<mode>3): Likewise.
	(nor<mode>3): Likewise.
	(*negsi2_extended): New template.
	(*<optab>si3_internal): Likewise.
	(*one_cmplsi2_internal): Likewise.
	(*norsi3_internal): Likewise.
	(*<optab>nsi_internal): Likewise.
	(bytepick_w_<bytepick_imm>_extend): Modify this template according to the
	modified bit operation to make the optimization work.

2024-01-11  liuhongt  <hongtao.liu@intel.com>

	PR target/104401
	* match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
	(get_vector_costs): Ditto.
	(riscv_builtin_vectorization_cost): Ditto.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.

2024-01-10  Antoni Boucher  <bouanto@zoho.com>

	PR jit/111396
	* ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
	ipa_free_size_summary.
	* ipa-icf.cc (ipa_icf_cc_finalize): New function.
	* ipa-profile.cc (ipa_profile_cc_finalize): New function.
	* ipa-prop.cc (ipa_prop_cc_finalize): New function.
	* ipa-prop.h (ipa_prop_cc_finalize): New function.
	* ipa-sra.cc (ipa_sra_cc_finalize): New function.
	* ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
	ipa_sra_cc_finalize): New functions.
	* toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
	ipa_prop_cc_finalize, ipa_profile_cc_finalize and
	ipa_sra_cc_finalize
	Include ipa-utils.h.

2024-01-10  Jin Ma  <jinma@linux.alibaba.com>

	* config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
	(th_int_get_save_adjustment): Likewise.
	(th_int_adjust_cfi_prologue): Likewise.
	* config/riscv/riscv.cc (BITSET_P): Moved away from here.
	(TH_INT_INTERRUPT): New macro.
	(riscv_expand_prologue): Add the processing of XTheadInt.
	(riscv_expand_epilogue): Likewise.
	* config/riscv/riscv.h (BITSET_P): Moved to here.
	* config/riscv/riscv.md: New unspec.
	* config/riscv/thead.cc (th_int_get_mask): New function.
	(th_int_get_save_adjustment): Likewise.
	(th_int_adjust_cfi_prologue): Likewise.
	* config/riscv/thead.md (th_int_push): New pattern.
	(th_int_pop): new pattern.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/112468
	* doc/sourcebuild.texi: Document ifn_copysign.
	* match.pd: Only apply transformation if target supports the IFN.

2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/112581
	* gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
	mark_ssa_maybe_undefs.
	* tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
	variables can not be reassociated.
	(init_range_entry): Check for uninitialized variables too.
	(init_reassoc): Call mark_ssa_maybe_undefs.

2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>

	* config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
	Also handle sign extension.

2024-01-10  Alex Coplan  <alex.coplan@arm.com>

	* config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
	to 0.
	(-mlate-ldp-fusion): Likewise.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113287
	* tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
	instead of using BRANCH_EDGE to determine true edge.

2024-01-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113078
	* tree-vect-loop.cc (check_reduction_path): Canonicalize
	.COND_SUB to .COND_ADD.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
	Handle prefix mappings before calling find_opt.
	(selftest::gcc_urlifier_cc_tests): Add example of urlifying a
	"-fno-"-prefixed command-line option.
	* opts-common.cc (get_option_prefix_remapping): New.
	* opts.h (get_option_prefix_remapping): New decl.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic.cc (diagnostic_context::report_diagnostic): Pass
	m_urlifier to pp_output_formatted_text.
	* pretty-print.cc: Add #define of INCLUDE_VECTOR.
	(obstack_append_string): New overload, taking a length.
	(urlify_quoted_string): Pass in an obstack ptr, rather than using
	that of the pp's buffer.  Generalize to handle trailing text in
	the buffer beyond the run of quoted text.
	(class quoting_info): New.
	(on_begin_quote): New.
	(on_end_quote): New.
	(pp_format): Refactor phase 1 and phase 2 quoting support, moving
	it to calls to on_begin_quote and on_end_quote.
	(struct auto_obstack): New.
	(quoting_info::handle_phase_3): New.
	(pp_output_formatted_text): Add urlifier param.  Use it if there
	is deferred urlification.  Delete m_quotes.
	(selftest::pp_printf_with_urlifier): Pass urlifier to
	pp_output_formatted_text.
	(selftest::test_urlification): Update results for the existing
	case of quoted text stradding chunks; add more such test cases.
	* pretty-print.h (class quoting_info): New forward decl.
	(chunk_info::m_quotes): New field.
	(pp_output_formatted_text): Add optional urlifier param.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

	* pretty-print.cc (selftest::test_pp_format): Add selftest
	coverage for numbered args.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113144
	PR tree-optimization/113145
	* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
	Update all BB that the original exits dominated.

2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>

	* dwarf2out.cc (modified_type_die): Extend the support of reverse
	storage order to enumeration types if -gstrict-dwarf is not passed.
	(gen_enumeration_type_die): Add REVERSE parameter and generate the
	DIE immediately after the existing one if it is true.
	(gen_tagged_type_die): Add REVERSE parameter and pass it in the
	call to gen_enumeration_type_die.
	(gen_type_die_with_usage): Add REVERSE parameter and pass it in the
	first recursive call as well as the call to gen_tagged_type_die.
	(gen_type_die): Add REVERSE parameter and pass it in the call to
	gen_type_die_with_usage.

2024-01-10  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113120
	* tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
	with root->size TYPE_PRECISION don't build anything new.
	Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
	rather than build_nonstandard_integer_type.

2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/i386.opt: Adjust document.
	* doc/invoke.texi: Add description for
	-mapx-inline-asm-use-gpr32.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
	(avg<v_double_trunc>3_floor): New pattern.
	(<u>avg<v_double_trunc>3_ceil): Remove.
	(avg<v_double_trunc>3_ceil): New pattern.
	(uavg<mode>3_floor): Ditto.
	(uavg<mode>3_ceil): Ditto.
	* config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
	(enum insn_type): Ditto.
	* config/riscv/riscv-v.cc: Ditto.
	* config/riscv/vector-iterators.md (ashiftrt): Remove.
	(ASHIFTRT): Ditto.
	* config/riscv/vector.md: Add VLS modes.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR target/111480
	* config/rs6000/vsx.md (VCZLSBB): New int iterator.
	(vczlsbb_char): New int attribute.
	(vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
	(vc<vczlsbb_char>zlsbb_<mode>): ... this.
	(*vctzlsbb_zext_<mode>): Rename to ...
	(*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
	cover vclzlsbb.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR target/112606
	* config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
	of the last argument from altivec_register_operand to any_operand.  If
	operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
	otherwise if it doesn't satisfy altivec_register_operand, force it to
	REG using copy_to_mode_reg.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

	PR middle-end/113100
	* builtins.cc (expand_builtin_stack_address): Guard stack point
	adjustment with SPARC_STACK_BOUNDARY_HACK.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
	argument string definitions.
	* config/loongarch/loongarch-str.h: Same.
	* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
	as aliases to -mexplicit-relocs={always,none}
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch.cc: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/loongarch-def.h: Define constants with
	enums instead of Macros.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/loongarch-strings: Rename.
	* config/loongarch/genopts/loongarch.opt.in: Same.
	* config/loongarch/loongarch-cpu.cc: Same.
	* config/loongarch/loongarch-def.cc: Same.
	* config/loongarch/loongarch-def.h: Same.
	* config/loongarch/loongarch-opts.cc: Same.
	* config/loongarch/loongarch-opts.h: Same.
	* config/loongarch/loongarch-str.h: Same.
	* config/loongarch/loongarch.opt: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

	* config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
	variable with the common la_ prefix.
	* config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
	flags as saved using TargetVariable.
	* config/loongarch/loongarch.opt: Same.
	* config/loongarch/loongarch-def.h: Define evolution_set to
	mark changes to the -march default.
	* config/loongarch/loongarch-driver.cc: Same.
	* config/loongarch/loongarch-opts.cc: Same.
	* config/loongarch/loongarch-opts.h: Define and use ISA evolution
	conditions around the la_target structure.
	* config/loongarch/loongarch.cc: Same.
	* config/loongarch/loongarch.md: Same.
	* config/loongarch/loongarch-builtins.cc: Same.
	* config/loongarch/loongarch-c.cc: Same.
	* config/loongarch/lasx.md: Same.
	* config/loongarch/lsx.md: Same.
	* config/loongarch/sync.md: Same.

2024-01-09  Jeff Law  <jlaw@ventanamicro.com>

	* config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
	no less.

2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>

	* config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	* tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
	restart_loop.
	(vectorizable_live_operation): Likewise.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	PR tree-optimization/113199
	* tree-vect-loop.cc (vectorizable_live_operation_1): Use
	BIT_FIELD_REF.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR target/113270
	* config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
	* config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
	GTY(()) declaration before the definition, drop GTY(()) drom the
	definition.

2024-01-09  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113026
	* tree-vect-loop-manip.cc (vect_do_peeling): Remove
	redundant and wrong niter bound setting.  Move niter
	bound adjustment down.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

	PR middle-end/113163
	* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
	Reject non-linear inductions that aren't supported.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>

	* config/arc/arc.cc (arc_shift_alg): New enumerated type for
	left shift implementation strategies.
	(arc_shift_info): Type for each entry of the shift strategy table.
	(arc_shift_context_idx): Return a integer value for each code
	generation context, used as an index
	(arc_ashl_alg): Table indexed by context and shifted bit count.
	(arc_split_ashl): Use the arc_ashl_alg table to select SImode
	left shift implementation.
	(arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
	provide accurate costs, when optimizing for speed or size.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.

2024-01-09  Julian Brown  <julian@codesourcery.com>

	* gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
	processed out before gimplification.
	* tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
	* tree.def (OMP_ARRAY_SECTION): New tree code.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113210
	* tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
	value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
	INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
	minus 1.

2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>

	PR rtl-optimization/113140
	* reorg.cc (fill_slots_from_thread): If we are to branch after the
	last instruction of the function, create an end label.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
	    Hongtao Liu  <hongtao.liu@intel.com>

	PR target/112992
	* config/i386/i386-expand.cc
	(ix86_convert_const_wide_int_to_broadcast): Allow call to
	ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
	(ix86_broadcast_from_constant): Revert recent change; Return a
	suitable MEMREF independently of mode/target combinations.
	(ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
	to decide whether expansion is possible/preferrable.  Only try
	forcing DImode constants to memory (and trying again) if calling
	ix86_expand_vector_init_duplicate fails with an DImode immediate
	constant.
	(ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
	V4SImode for suitable immediate constants.
	<case E_V4DImode>: Try using V8SImode for suitable constants.
	<case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
	<case E_V2HImode>: Likewise.
	<case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
	<case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
	<label widen>: Handle CONT_INTs via simplify_binary_operation.
	Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
	<case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
	<case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
	(ix86_expand_vector_init): Move try using a broadcast for all_same
	with ix86_expand_vector_init_duplicate before using constant pool.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

	* doc/invoke.texi (Arm Options): Document Cortex-M52 options.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

	* config/arm/arm-cpus.in (cortex-m52): New cpu.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.

2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
	(vec_init<mode><lasxhalf>): .. this, and extend to mode.
	(@vec_concatz<mode>): New insn pattern.
	* config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
	Handle VALS containing two vectors.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
	(vundefined): Ditto.

2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>

	PR sanitizer/113251
	* varasm.cc (assemble_function_label_raw): Do not call
	asan_function_start () without the current function.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

	PR target/113225
	* btfout.cc (btf_collect_datasec): Skip creating BTF info for
	extern and kernel_helper attributed function decls.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

	* btfout.cc (output_btf_strs): Changed.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

	* config/gcn/mkoffload.cc (main): Handle gfx1100
	when setting the default XNACK.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

	* config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
	* config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
	(ASM_SPEC): Handle gfx1100.
	* config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
	(enum gcn_isa): Add ISA_RDNA3.
	(TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
	* config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	* config/gcn/gcn.cc (gcn_option_override,
	gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
	(gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
	TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	(gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
	with gfx1100.
	* config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
	(TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
	__gfx1100__.
	* config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
	* config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
	* config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
	(isa_has_combined_avgprs, main): Handle gfx1100.
	* config/gcn/t-omp-device (isa): Add gfx1100.

2024-01-08  Richard Biener  <rguenther@suse.de>

	* doc/invoke.texi (-mmovbe): Clarify.

2024-01-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/113026
	* tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
	Avoid an epilog in more cases.
	* tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
	epilogues niter upper bounds and estimates.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113228
	* gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113120
	* gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
	large _BitInt zero INTEGER_CST PHI argument.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113119
	* gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
	both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
	is before REALPART_EXPR.

2024-01-08  Georg-Johann Lay  <avr@gjlay.de>

	PR target/112952
	* config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
	range when diagnosing attribute "io" and "io_low" are out of range.
	(avr_eval_addr_attrib): Don't ICE on empty address at that place.
	(avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
	in contexts other than static storage.
	(avr_asm_output_aligned_decl_common): Move output of decls with
	attribute "address", "io", and "io_low" to...
	(avr_output_addr_attrib): ...this new function.
	(avr_asm_asm_output_aligned_bss): Remove output for decls with
	attribute "address", "io", and "io_low".
	(avr_encode_section_info): Rectify handling of decls with attribute
	"address", "io", and "io_low".

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

	* config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
	(elf_flags): Remove XNACK from the default value.
	(main): Set a default XNACK according to the arch.

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

	* config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
	(process_asm): Don't count avgprs.

2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>

	* config/i386/i386.opt: Add supported sub-features.
	* doc/extend.texi: Add description for target attribute.

2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.

2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
	    Uros Bizjak  <ubizjak@gmail.com>

	PR target/113231
	* config/i386/i386-features.cc (compute_convert_gain): Include
	the overhead of explicit load and store (movd) instructions when
	converting non-store scalar operations with memory destinations.
	Various indentation whitespace fixes.

2024-01-07  Tamar Christina  <tamar.christina@arm.com>

	* config/arm/neon.md (cbranch<mode>4): New.

2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vsetvl.cc: replace std::max by MAX.

2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>

	* config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113248
	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
	Update the MAX_SEW.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
	(variable_vectorized_p): Teach loop invariant.
	(has_unexpected_spills_p): Ditto.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
	* config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
	* config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.

2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>

	PR target/113104
	* doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
	(aarch64-vect-compare-costs): ...this.
	* config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
	Replace with...
	(-param=aarch64-vect-compare-costs=): ...this new param.
	* config/aarch64/aarch64.cc (aarch64_override_options_internal):
	Don't disable it when vectorizing for Advanced SIMD only.
	(aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
	whenever aarch64_vect_compare_costs is true.

2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>

	* config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
	Modify the method of determining the memory offset of [x]vld/[x]vst.
	(lasx_mxst_<lasxfmt_f>): Likewise.
	* config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
	(loongarch_address_insns): Likewise.
	* config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
	(lsx_st_<lsxfmt_f>): Likewise.
	* config/loongarch/predicates.md (aq10b_operand): Likewise.
	(aq10h_operand): Likewise.
	(aq10w_operand): Likewise.
	(aq10d_operand): Likewise.

2024-01-05  Alex Coplan  <alex.coplan@arm.com>

	PR target/113217
	* config/aarch64/aarch64-ldp-fusion.cc
	(ldp_bb_info::try_fuse_pair): If the second access can throw,
	narrow the move range to exactly that insn.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

	* asan.cc (asan_function_start): Drop switch_to_section ().
	(asan_emit_stack_protection): Set .LASANPC alignment.
	* config/i386/i386.cc: Use assemble_function_label_raw ()
	instead of ASM_OUTPUT_LABEL ().
	* config/s390/s390.cc (s390_asm_output_function_label):
	Likewise.
	* defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
	* final.cc (final_start_function_1): Drop
	asan_function_start ().
	* output.h (assemble_function_label_raw): New function.
	* varasm.cc (assemble_function_label_raw): Likewise.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/aarch64/aarch64.cc (aarch64_declare_function_name):
	Use ASM_OUTPUT_FUNCTION_LABEL ().
	* config/alpha/alpha.cc (alpha_start_function): Likewise.
	* config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
	* config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
	* config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
	* config/ia64/ia64.cc (ia64_start_function): Likewise.
	* config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
	Likewise.
	* config/microblaze/microblaze.cc (microblaze_function_prologue):
	Likewise.
	* config/mips/mips.cc (mips_start_unique_function): Return the
	tree.
	(mips_start_function_definition): Use
	ASM_OUTPUT_FUNCTION_LABEL ().
	(mips_finish_stub): Pass the tree to
	mips_start_function_definition ().
	(mips16_build_function_stub): Likewise.
	(mips16_build_call_stub): Likewise.
	(mips_output_function_prologue): Likewise.
	* config/pa/pa.cc (pa_output_function_label): Use
	ASM_OUTPUT_FUNCTION_LABEL ().
	* config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
	* config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
	Likewise.
	(rs6000_xcoff_declare_function_name): Likewise.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113201
	* tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
	replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/90693
	* tree-ssa-math-opts.cc (match_single_bit_test): If
	tree_expr_nonzero_p (arg), remember it in the second argument to
	IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
	arg ^ (arg - 1) > arg - 1.
	* internal-fn.cc (expand_POPCOUNT): If second argument to
	IFN_POPCOUNT suggests arg is non-zero, try to expand it as
	arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.

2024-01-05  Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv-v.cc (expand_load_store):
	Remove `value`.
	(expand_cond_len_op): Ditto.
	(expand_gather_scatter): Ditto.
	(expand_lanes_load_store): Ditto.
	(expand_fold_extract_last): Ditto.

2024-01-05  Pan Li  <pan2.li@intel.com>

	Revert:
	2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
				Add new function_base for crypto vector.
	(class bitmanip): Ditto.
	(class b_reverse):Ditto.
	(class vwsll):   Ditto.
	(class clmul):   Ditto.
	(class vg_nhab):  Ditto.
	(class crypto_vv):Ditto.
	(class crypto_vi):Ditto.
	(class vaeskf2_vsm3c):Ditto.
	(class vsm3me): Ditto.
	(BASE): Add BASE declaration for crypto vector.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
				Add crypto vector intrinsic definition.
	(vbrev): Ditto.
	(vclz): Ditto.
	(vctz): Ditto.
	(vwsll): Ditto.
	(vandn): Ditto.
	(vbrev8): Ditto.
	(vrev8): Ditto.
	(vrol): Ditto.
	(vror): Ditto.
	(vclmul): Ditto.
	(vclmulh): Ditto.
	(vghsh): Ditto.
	(vgmul): Ditto.
	(vaesef): Ditto.
	(vaesem): Ditto.
	(vaesdf): Ditto.
	(vaesdm): Ditto.
	(vaesz): Ditto.
	(vaeskf1): Ditto.
	(vaeskf2): Ditto.
	(vsha2ms): Ditto.
	(vsha2ch): Ditto.
	(vsha2cl): Ditto.
	(vsm4k): Ditto.
	(vsm4r): Ditto.
	(vsm3me): Ditto.
	(vsm3c): Ditto.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
				Add new function_shape for crypto vector.
	(struct crypto_vi_def): Ditto.
	(struct crypto_vv_no_op_type_def): Ditto.
	(SHAPE): Add SHAPE declaration of crypto vector.
	* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data type for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(vuint32mf2_t): Ditto.
	(vuint32m1_t): Ditto.
	(vuint32m2_t): Ditto.
	(vuint32m4_t): Ditto.
	(vuint32m8_t): Ditto.
	(vuint64m1_t): Ditto.
	(vuint64m2_t): Ditto.
	(vuint64m4_t): Ditto.
	(vuint64m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
				Add new data struct for crypto vector.
	(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
	(registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
	* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>

	PR tree-optimization/113186
	* gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
	Match `^` with the `==` for 1bit integral types.
	* match.pd (maybe_cmp): Allow for bit_xor for 1bit
	integral types.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* toplev.cc (general_init): Pass lang_mask to urlifier.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
	param.
	(diagnostic_context::make_option_url): Update for lang_mask param.
	* gcc-urlifier.cc: Include "opts.h" and "options.h".
	(gcc_urlifier::gcc_urlifier): Add lang_mask param.
	(gcc_urlifier::m_lang_mask): New field.
	(doc_urls): Make static.
	(gcc_urlifier::get_url_for_quoted_text): Use label_text.
	(gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
	Look for an option by name before trying a binary search in
	doc_urls.
	(gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
	(gcc_urlifier::get_url_suffix_for_option): New.
	(make_gcc_urlifier): Add lang_mask param.
	(selftest::gcc_urlifier_cc_tests): Update for above changes.
	Verify that a URL is found for "-fpack-struct".
	* gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
	* gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
	* gcc.cc (driver::global_initializations): Pass 0 for lang_mask
	to make_gcc_urlifier.
	* opts-diagnostic.h (get_option_url): Add lang_mask param.
	* opts.cc (get_option_html_page): Remove special-casing for
	analyzer and LTO.
	(get_option_url_suffix): New.
	(get_option_url): Reimplement.
	(selftest::test_get_option_html_page): Rename to...
	(selftest::test_get_option_url_suffix): ...this and update for
	above changes.
	(selftest::opts_cc_tests): Update for renaming.
	* opts.h: Include "rich-location.h".
	(get_option_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* Makefile.in (ALL_OPT_URL_FILES): New.
	(GCC_OBJS): Add options-urls.o.
	(OBJS): Likewise.
	(OBJS-libcommon): Likewise.
	(s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
	inputs to opt-gather.awk.
	(options-urls.cc): New Makefile target.
	* opt-functions.awk (url_suffix): New function.
	(lang_url_suffix): New function.
	* options-urls-cc-gen.awk: New file.
	* opts.h (get_opt_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* params.opt.urls: New file, autogenerated by
	regenerate-opt-urls.py.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* common.opt.urls: New file, autogenerated by
	regenerate-opt-urls.py.
	* config/aarch64/aarch64.opt.urls: Likewise.
	* config/alpha/alpha.opt.urls: Likewise.
	* config/alpha/elf.opt.urls: Likewise.
	* config/arc/arc-tables.opt.urls: Likewise.
	* config/arc/arc.opt.urls: Likewise.
	* config/arm/arm-tables.opt.urls: Likewise.
	* config/arm/arm.opt.urls: Likewise.
	* config/arm/vxworks.opt.urls: Likewise.
	* config/avr/avr.opt.urls: Likewise.
	* config/bpf/bpf.opt.urls: Likewise.
	* config/c6x/c6x-tables.opt.urls: Likewise.
	* config/c6x/c6x.opt.urls: Likewise.
	* config/cris/cris.opt.urls: Likewise.
	* config/cris/elf.opt.urls: Likewise.
	* config/csky/csky.opt.urls: Likewise.
	* config/csky/csky_tables.opt.urls: Likewise.
	* config/darwin.opt.urls: Likewise.
	* config/dragonfly.opt.urls: Likewise.
	* config/epiphany/epiphany.opt.urls: Likewise.
	* config/fr30/fr30.opt.urls: Likewise.
	* config/freebsd.opt.urls: Likewise.
	* config/frv/frv.opt.urls: Likewise.
	* config/ft32/ft32.opt.urls: Likewise.
	* config/fused-madd.opt.urls: Likewise.
	* config/g.opt.urls: Likewise.
	* config/gcn/gcn.opt.urls: Likewise.
	* config/gnu-user.opt.urls: Likewise.
	* config/h8300/h8300.opt.urls: Likewise.
	* config/hpux11.opt.urls: Likewise.
	* config/i386/cygming.opt.urls: Likewise.
	* config/i386/cygwin.opt.urls: Likewise.
	* config/i386/djgpp.opt.urls: Likewise.
	* config/i386/i386.opt.urls: Likewise.
	* config/i386/mingw-w64.opt.urls: Likewise.
	* config/i386/mingw.opt.urls: Likewise.
	* config/i386/nto.opt.urls: Likewise.
	* config/ia64/ia64.opt.urls: Likewise.
	* config/ia64/ilp32.opt.urls: Likewise.
	* config/ia64/vms.opt.urls: Likewise.
	* config/iq2000/iq2000.opt.urls: Likewise.
	* config/linux-android.opt.urls: Likewise.
	* config/linux.opt.urls: Likewise.
	* config/lm32/lm32.opt.urls: Likewise.
	* config/loongarch/loongarch.opt.urls: Likewise.
	* config/lynx.opt.urls: Likewise.
	* config/m32c/m32c.opt.urls: Likewise.
	* config/m32r/m32r.opt.urls: Likewise.
	* config/m68k/ieee.opt.urls: Likewise.
	* config/m68k/m68k-tables.opt.urls: Likewise.
	* config/m68k/m68k.opt.urls: Likewise.
	* config/m68k/uclinux.opt.urls: Likewise.
	* config/mcore/mcore.opt.urls: Likewise.
	* config/microblaze/microblaze.opt.urls: Likewise.
	* config/mips/mips-tables.opt.urls: Likewise.
	* config/mips/mips.opt.urls: Likewise.
	* config/mips/sde.opt.urls: Likewise.
	* config/mmix/mmix.opt.urls: Likewise.
	* config/mn10300/mn10300.opt.urls: Likewise.
	* config/moxie/moxie.opt.urls: Likewise.
	* config/msp430/msp430.opt.urls: Likewise.
	* config/nds32/nds32-elf.opt.urls: Likewise.
	* config/nds32/nds32-linux.opt.urls: Likewise.
	* config/nds32/nds32.opt.urls: Likewise.
	* config/netbsd-elf.opt.urls: Likewise.
	* config/netbsd.opt.urls: Likewise.
	* config/nios2/elf.opt.urls: Likewise.
	* config/nios2/nios2.opt.urls: Likewise.
	* config/nvptx/nvptx-gen.opt.urls: Likewise.
	* config/nvptx/nvptx.opt.urls: Likewise.
	* config/openbsd.opt.urls: Likewise.
	* config/or1k/elf.opt.urls: Likewise.
	* config/or1k/or1k.opt.urls: Likewise.
	* config/pa/pa-hpux.opt.urls: Likewise.
	* config/pa/pa-hpux1010.opt.urls: Likewise.
	* config/pa/pa-hpux1111.opt.urls: Likewise.
	* config/pa/pa-hpux1131.opt.urls: Likewise.
	* config/pa/pa.opt.urls: Likewise.
	* config/pa/pa64-hpux.opt.urls: Likewise.
	* config/pdp11/pdp11.opt.urls: Likewise.
	* config/pru/pru.opt.urls: Likewise.
	* config/riscv/riscv.opt.urls: Likewise.
	* config/rl78/rl78.opt.urls: Likewise.
	* config/rpath.opt.urls: Likewise.
	* config/rs6000/476.opt.urls: Likewise.
	* config/rs6000/aix64.opt.urls: Likewise.
	* config/rs6000/darwin.opt.urls: Likewise.
	* config/rs6000/linux64.opt.urls: Likewise.
	* config/rs6000/rs6000-tables.opt.urls: Likewise.
	* config/rs6000/rs6000.opt.urls: Likewise.
	* config/rs6000/sysv4.opt.urls: Likewise.
	* config/rtems.opt.urls: Likewise.
	* config/rx/elf.opt.urls: Likewise.
	* config/rx/rx.opt.urls: Likewise.
	* config/s390/s390.opt.urls: Likewise.
	* config/s390/tpf.opt.urls: Likewise.
	* config/sh/sh.opt.urls: Likewise.
	* config/sh/superh.opt.urls: Likewise.
	* config/sol2.opt.urls: Likewise.
	* config/sparc/long-double-switch.opt.urls: Likewise.
	* config/sparc/sparc.opt.urls: Likewise.
	* config/stormy16/stormy16.opt.urls: Likewise.
	* config/v850/v850.opt.urls: Likewise.
	* config/vax/elf.opt.urls: Likewise.
	* config/vax/vax.opt.urls: Likewise.
	* config/visium/visium.opt.urls: Likewise.
	* config/vms/vms.opt.urls: Likewise.
	* config/vxworks-smp.opt.urls: Likewise.
	* config/vxworks.opt.urls: Likewise.
	* config/xtensa/elf.opt.urls: Likewise.
	* config/xtensa/uclinux.opt.urls: Likewise.
	* config/xtensa/xtensa.opt.urls: Likewise.
	* config/bfin/bfin.opt.urls: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* Makefile.in (OPT_URLS_HTML_DEPS): New.
	(regenerate-opt-urls): New target.
	(regenerate-opt-urls-unit-test): New target.
	* doc/options.texi (Option properties): Add UrlSuffix and
	description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
	* doc/sourcebuild.texi (Anatomy of a Language Front End): Add
	reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
	and Makefile.in's OPT_URLS_HTML_DEPS.
	(Anatomy of a Target Back End): Add
	reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
	* regenerate-opt-urls.py: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

	* diagnostic-format-sarif.cc
	(sarif_builder::make_logical_location_object): Convert to...
	(make_sarif_logical_location_object): ...this.
	(sarif_builder::set_any_logical_locs_arr): Update for above
	change.
	(sarif_builder::make_thread_flow_location_object): Call
	maybe_add_sarif_properties on each diagnostic_event.
	* diagnostic-format-sarif.h (class logical_location): New forward
	decl.
	(make_sarif_logical_location_object): New decl.
	* diagnostic-path.h (class sarif_object): New forward decl.
	(diagnostic_event::maybe_add_sarif_properties): New vfunc.

2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
	    Patrick Lin  <patrick@andestech.com>
	    Rufus Chen  <rufus@andestech.com>
	    Monk Chiang  <monk.chiang@sifive.com>

	* config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
	with Nan-boxing value.
	* config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.

2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
	    Jeff Law  <jlaw@ventanamicro.com>

	PR rtl-optimization/104914
	* expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
	a sign or zero extension is only required if the modified field
	overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
	targets, don't refer to the temporarily incorrectly extended value
	using a SUBREG, but instead generate an explicit TRUNCATE rtx.

2024-01-04  Pan Li  <pan2.li@intel.com>

	Revert:
	2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
	offset of fcsr.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
	(compute_nregs_for_mode): Refine LMUL.
	(max_number_of_live_regs): Ditto.
	(compute_estimated_lmul): Ditto.
	(has_unexpected_spills_p): Ditto.

2024-01-04  Li Wei  <liwei@loongson.cn>

	* config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
	Remove useless forward declaration.
	(loongarch_is_even_extraction): Remove useless forward declaration.
	(loongarch_try_expand_lsx_vshuf_const): Removed.
	(loongarch_expand_vec_perm_const_1): Merged.
	(loongarch_is_double_duplicate): Removed.
	(loongarch_is_center_extraction): Ditto.
	(loongarch_is_reversing_permutation): Ditto.
	(loongarch_is_di_misalign_extract): Ditto.
	(loongarch_is_si_misalign_extract): Ditto.
	(loongarch_is_lasx_lowpart_extract): Ditto.
	(loongarch_is_op_reverse_perm): Ditto.
	(loongarch_is_single_op_perm): Ditto.
	(loongarch_is_divisible_perm): Ditto.
	(loongarch_is_triple_stride_extract): Ditto.
	(loongarch_expand_vec_perm_const_2): Merged.
	(loongarch_expand_vec_perm_const): New.
	(loongarch_vectorize_vec_perm_const): Adjust.

2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>

	* omp-general.cc: Fix comment typos and misplaced/confusing
	comments.  Delete redundant include of omp-general.h.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	PR rtl-optimization/104914
	* config/mips/mips.md (insqisi_extended): New patterns.
	(inshisi_extended): Ditto.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.cc (mips_insn_cost): New function.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

	* config/mips/mips.md (perf_ratio): New attribute.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113206
	PR target/113209
	* config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
	(pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
	blocks belong to infinite loop.
	(pre_vsetvl::emit_vsetvl): Remove fake edges.
	* config/riscv/t-riscv: Add a new include file.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/vector.md: Fix indent.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

	* tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
	OMP_CLAUSE__SIMDUID_.
	* tree.cc (omp_clause_num_ops): Update position of entry for
	OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
	(omp_clause_code_name): Likewise.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

	* config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
	printing of FUNC_MAP/IND_FUNC_MAP labels.

2024-01-03  Jakub Jelinek  <jakub@redhat.com>

	* gcc.cc (process_command): Update copyright notice dates.
	* gcov-dump.cc (print_version): Ditto.
	* gcov.cc (print_version): Ditto.
	* gcov-tool.cc (print_version): Ditto.
	* gengtype.cc (create_file): Ditto.
	* doc/cpp.texi: Bump @copying's copyright year.
	* doc/cppinternals.texi: Ditto.
	* doc/gcc.texi: Ditto.
	* doc/gccint.texi: Ditto.
	* doc/gcov.texi: Ditto.
	* doc/install.texi: Ditto.
	* doc/invoke.texi: Ditto.

2024-01-03  Xi Ruoyao  <xry111@xry111.site>

	* config/loongarch/simd.md (fmax<mode>3): New define_insn.
	(fmin<mode>3): Likewise.
	(reduc_fmax_scal_<mode>3): New define_expand.
	(reduc_fmin_scal_<mode>3): Likewise.

2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113112
	* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
	(max_number_of_live_regs): Ditto.
	(has_unexpected_spills_p): Ditto.

2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
	    Jin Ma  <jinma@linux.alibaba.com>
	    Xianmiao Qu  <cooper.qu@linux.alibaba.com>
	    Christoph Müllner  <christoph.muellner@vrull.eu>

	* config/riscv/vector.md:
	Use vector_length_operand for vsetvl patterns.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
	(expand_cond_len_op): Add simplification of dummy len and dummy mask.

2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>

	* config/aarch64/aarch64-tuning-flags.def
	(AARCH64_EXTRA_TUNING_OPTION): New tuning option
	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
	* config/aarch64/aarch64.cc
	(aarch64_override_options_internal): Set
	param_fully_pipelined_fma according to tuning option.
	* config/aarch64/tuning_models/ampere1.h: Add
	AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
	* config/aarch64/tuning_models/ampere1a.h: Likewise.
	* config/aarch64/tuning_models/ampere1b.h: Likewise.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/vector-crypto.md: Modify copyright year.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.

2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>

	* config.in: Regenerate.
	* config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
	* config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
	Added TLS Le Relax support.
	(loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
	* config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
	* configure: Regenerate.
	* configure.ac: Check if binutils supports TLS le relax.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

	* config/riscv/iterators.md: Add rotate insn name.
	* config/riscv/riscv.md: Add new insns name for crypto vector.
	* config/riscv/vector-iterators.md: Add new iterators for crypto vector.
	* config/riscv/vector.md: Add the corresponding attr for crypto vector.
	* config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

	PR target/113112
	* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
	pointer type liveness count.

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