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2020-10-17Daily bump.GCC Administrator1-0/+33
2020-10-16Inhibit support for C++0x threads on VxWorks < 6Rasmus Villemoes2-2/+6
As for condition variables, the C++0x threads support relies on VxWorks entry points not available in VxWorks versions prior to 6. We just expose absence of support for C++0x threads on such systems. 2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk> libgcc/ * config/gthr-vxworks.h: Condition the ___GTHREADS_CXX0X section on VxWorks >= 6. * config/gthr-vxworks-thread.c: Condition the entire implementation on __GTHREAD_CXX0X.
2020-10-16Inhibit support for gthread condvars on VxWorks < 6Rasmus Villemoes2-0/+12
The condition variables support relies on kernel entry points to enforce critical aspects of it's expected behavior. Some of these entry points are not available prior to VxWorks 6, so we just expose absence of support for condition variables on such systems. 2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk> libgcc/ * config/gthr-vxworks.h: Condition the __GTHREAD_HAS_COND section on VxWorks >= 6. * config/gthr-vxworks-cond.c: Condition the entire implementation on __GTHREAD_HAS_COND.
2020-10-16Add missing #include <taskLib.h> in gthr-vxworks.cRasmus Villemoes1-0/+1
This fixes an oversight and addresses a few build time warnings. 2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk> libgcc/ * config/gthr-vxworks.c: #include <taskLib.h>.
2020-10-16Fix leftover _VXW_PRE_69 in gthr-vxworks.hRasmus Villemoes1-1/+1
2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk> libgcc/ * config/gthr-vxworks.h: Rewrite remaining occurrence of _VXW_PRE_69 as _VXWORKS_PRE(6,9).
2020-10-16Stub out VX_ENTER_TLS_DTOR for VxWorks != 6Rasmus Villemoes1-7/+15
As of today, the __gthread_enter/leave entry points are only meaningful on VxWorks 6. Refactor the VX_ENTER_TLS_DTOR macros accordingly. 2020-10-15 Rasmus Villemoes <rv@rasmusvillemoes.dk> libgcc/ * config/gthr-vxworks-tls.c (VX_ENTER_TLS_DTOR): Nil except on VxWorks 6. Co-authored-by: Olivier Hainque <hainque@adacore.com>
2020-10-16Fix the vxworks crtstuff handling of kernel/rtp variationsOlivier Hainque1-6/+6
The ports that support RTPs achieve the kernel/rtp compilation and link distinction through the multilib mechanism. This patch just removes the bogus explicit extraneous materialization of this distinction in the common VxWorks configuration files and leaves the rtp specialization all to the multilib machinery. 2020-10-15 Olivier Hainque <hainque@adacore.com> libgcc/ * config/t-vxcrtstuff: Remove the -kernel/-rtp specialization. gcc/ * config/vxworks.h (VX_CRTBEGIN_SPEC): Likewise.
2020-10-15Daily bump.GCC Administrator1-0/+25
2020-10-14Rework the condition variables support for VxWorksAlexandre Oliva2-12/+47
This change reworks the condition variables support for VxWorks to address the very legit points raised by Rasmus in https://gcc.gnu.org/pipermail/gcc/2020-May/232524.html While some of the issues were taken care of by the use of semFlush, a few others were indeed calling for adjustments. We first considered resorting to the condvarLib library available in VxWorks7. Unfortunately, it is vx7 only and we wanted something working for at least vx 6.9 as well. It also turned out requiring the use of recursive mutexes for condVarWait, which seemed unnecessarily constraining. Instead, this change corrects the sequencing logic in a few places and leverages the semExchange API to ensure the key atomicity requirement on cond_wait operations. 2020-10-14 Alexandre Oliva <oliva@adacore.com> libgcc/ * config/gthr-vxworks-thread.c: Include stdlib.h. (tls_delete_hook): Prototype it. (__gthread_cond_signal): Return early if no waiters. Consume signal in case the semaphore got full. Use semInfoGet instead of kernel-mode-only semInfo. (__gthread_cond_timedwait): Use semExchange. Always take the mutex again before returning. * config/gthr-vxworks-cond.c (__ghtread_cond_wait): Likewise.
2020-10-14Honor $(MULTISUBDIR) in -I directives for libgcc on VxWorksOlivier Hainque2-2/+2
This is useful to handle ports where we might arrange to use different sets of fixed headers for different multilibs, typically for kernel vs rtp modes. 2020-10-14 Olivier Hainque <hainque@adacore.com> libgcc/ * config/t-vxworks (LIBGCC2_INCLUDES): Append $(MULTISUBDIR) to the -I path for fixed headers, as we arrange to have different sets of such headers for different multilibs when they are activated. * config/t-vxworks7: Likewise.
2020-10-14Add include-fixed to include search paths for libgcc on VxWorksOlivier Hainque2-0/+2
The special vxworks rules for the compilation of libgcc had -I.../gcc/include and not .../gcc/include-fixed, causing build failure of our arm-vxworks7r2 port because of indirect dependencies on limits.h. The omission was just an oversight and this change just adds the missing -I. 2020-10-14 Olivier Hainque <hainque@adacore.com> libgcc/ * config/t-vxworks: Add include-fixed to include search paths for libgcc on VxWorks. * config/t-vxworks7: Likewise.
2020-10-10Daily bump.GCC Administrator1-0/+6
2020-10-09x86: Add <x86gprintrin.h>H.J. Lu1-8/+1
For sources which can't use any vector instructions, <x86intrin.h> and <immintrin.h> cannot be included for compiler intrinsics: $ echo "#include <x86intrin.h>" | gcc -S -O2 -mno-sse -mno-mmx -x c - In file included from /usr/include/stdlib.h:1013, from /usr/lib/gcc/x86_64-redhat-linux/10/include/mm_malloc.h:27, from /usr/lib/gcc/x86_64-redhat-linux/10/include/xmmintrin.h:34, from /usr/lib/gcc/x86_64-redhat-linux/10/include/immintrin.h:29, from /usr/lib/gcc/x86_64-redhat-linux/10/include/x86intrin.h:32, from <stdin>:1: /usr/include/bits/stdlib-float.h: In function ‘atof’: /usr/include/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled 26 | { | ^ $ libgcc/config/i386/shadow-stack-unwind.h has a workaround: /* NB: We need _get_ssp and _inc_ssp from <cetintrin.h>. But we can't include <x86intrin.h> which ends up including <mm_malloc.h>, which includes <stdlib.h> and <errno.h> unconditionally. But we can't include any libc system headers unconditionally from libgcc. Avoid including <mm_malloc.h> here by defining _IMMINTRIN_H_INCLUDED. */ #define _IMMINTRIN_H_INCLUDED #include <cetintrin.h> #undef _IMMINTRIN_H_INCLUDED Add a standalone intrinsic header file, <x86gprintrin.h>, to provide integer only intrinsics. All integer only intrinsics are placed in <x86gprintrin.h>. <x86intrin.h> and <immintrin.h> simply include <x86gprintrin.h>. gcc/ PR target/97148 * config.gcc (extra_headers): Add x86gprintrin.h. * config/i386/adxintrin.h: Check _X86GPRINTRIN_H_INCLUDED for <x86gprintrin.h>. * config/i386/bmi2intrin.h: Likewise. * config/i386/bmiintrin.h: Likewise. * config/i386/cetintrin.h: Likewise. * config/i386/cldemoteintrin.h: Likewise. * config/i386/clflushoptintrin.h: Likewise. * config/i386/clwbintrin.h: Likewise. * config/i386/enqcmdintrin.h: Likewise. * config/i386/fxsrintrin.h: Likewise. * config/i386/ia32intrin.h: Likewise. * config/i386/lwpintrin.h: Likewise. * config/i386/lzcntintrin.h: Likewise. * config/i386/movdirintrin.h: Likewise. * config/i386/pconfigintrin.h: Likewise. * config/i386/pkuintrin.h: Likewise. * config/i386/rdseedintrin.h: Likewise. * config/i386/rtmintrin.h: Likewise. * config/i386/serializeintrin.h: Likewise. * config/i386/tbmintrin.h: Likewise. * config/i386/tsxldtrkintrin.h: Likewise. * config/i386/waitpkgintrin.h: Likewise. * config/i386/wbnoinvdintrin.h: Likewise. * config/i386/xsavecintrin.h: Likewise. * config/i386/xsaveintrin.h: Likewise. * config/i386/xsaveoptintrin.h: Likewise. * config/i386/xsavesintrin.h: Likewise. * config/i386/xtestintrin.h: Likewise. * config/i386/immintrin.h: Include <x86gprintrin.h> instead of <fxsrintrin.h>, <xsaveintrin.h>, <xsaveoptintrin.h>, <xsavesintrin.h>, <xsavecintrin.h>, <lzcntintrin.h>, <bmiintrin.h>, <bmi2intrin.h>, <xtestintrin.h>, <cetintrin.h>, <movdirintrin.h>, <sgxintrin.h, <pconfigintrin.h>, <waitpkgintrin.h>, <cldemoteintrin.h>, <enqcmdintrin.h>, <serializeintrin.h>, <tsxldtrkintrin.h>, <adxintrin.h>, <clwbintrin.h>, <clflushoptintrin.h>, <wbnoinvdintrin.h> and <pkuintrin.h>. (_wbinvd): Moved to config/i386/x86gprintrin.h. (_rdrand16_step): Likewise. (_rdrand32_step): Likewise. (_rdpid_u32): Likewise. (_readfsbase_u32): Likewise. (_readfsbase_u64): Likewise. (_readgsbase_u32): Likewise. (_readgsbase_u64): Likewise. (_writefsbase_u32): Likewise. (_writefsbase_u64): Likewise. (_writegsbase_u32): Likewise. (_writegsbase_u64): Likewise. (_rdrand64_step): Likewise. (_ptwrite64): Likewise. (_ptwrite32): Likewise. * config/i386/x86gprintrin.h: New file. * config/i386/x86intrin.h: Include <x86gprintrin.h>. Don't include <ia32intrin.h>, <lwpintrin.h>, <tbmintrin.h>, <popcntintrin.h>, <mwaitxintrin.h> and <clzerointrin.h>. gcc/testsuite/ * gcc.target/i386/avx-1.c (__builtin_ia32_lwpval32): New to support <lwpintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_lwpval64): Likewise. (__builtin_ia32_lwpins32): Likewise. (__builtin_ia32_lwpins64): Likewise. (__builtin_ia32_bextri_u32): New to support <tbmintrin.h> included in <x86gprintrin.h>. (__builtin_ia32_bextri_u64): Likewise. * gcc.target/i386/x86gprintrin-1.c: New test. * gcc.target/i386/x86gprintrin-2.c: Likewise. * gcc.target/i386/x86gprintrin-3.c: Likewise. * gcc.target/i386/x86gprintrin-4.c: Likewise. * gcc.target/i386/x86gprintrin-4a.c: Likewise. * gcc.target/i386/x86gprintrin-5.c: Likewise. * gcc.target/i386/x86gprintrin-5a.c: Likewise. * gcc.target/i386/x86gprintrin-5b.c: Likewise. * gcc.target/i386/x86gprintrin-6.c: Likewise. libgcc/ PR target/97148 * config/i386/shadow-stack-unwind.h: Include <x86gprintrin.h> instead of <cetintrin.h>.
2020-10-02Daily bump.GCC Administrator1-0/+9
2020-10-01[RS6000] Adjust gcc asm for power10Alan Modra2-9/+27
Generate assembly with .localentry,1 functions using @notoc calls. This patch makes libgcc.a asm look the same as power10 pcrel as far as toc/notoc is concerned. Otherwise calling between functions that advertise as using the TOC and those that don't, will require linker call stubs in statically linked code. gcc/ * config/rs6000/ppc-asm.h: Support __PCREL__ code. libgcc/ * config/rs6000/morestack.S, * config/rs6000/tramp.S: Support __PCREL__ code. libitm/ * config/powerpc/sjlj.S: Support __PCREL__ code.
2020-10-01[RS6000] -mno-minimal-toc vs. power10 pcrelativeAlan Modra1-1/+6
We've had this hack in the libgcc config to build libgcc with -mcmodel=small for powerpc64 for a long time. It wouldn't be a bad thing if someone who knows the multilib machinery well could arrange for -mcmodel=small to be passed just for ppc64 when building for earlier than power10. But for now, make -mno-minimal-toc do nothing when pcrel. Which will do the right thing for any project that has copied libgcc's trick. We want this if configuring using --with-cpu=power10 to build a power10 pcrel libgcc. --mcmodel=small turns off pcrel. gcc/ * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't set -mcmodel=small for -mno-minimal-toc when pcrel. libgcc/ * config/rs6000/t-linux: Document purpose of -mno-minimal-toc.
2020-09-30Daily bump.GCC Administrator1-0/+5
2020-09-29RISC-V/libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCSMaciej W. Rozycki1-0/+2
Use `-fasynchronous-unwind-tables' rather than `-fexceptions -fnon-call-exceptions' in LIB2_DIVMOD_FUNCS compilation flags so as to provide unwind tables for the affected functions while not pulling the unwinder proper, which is not required here. Beyond saving program space it fixes a RISC-V glibc build error due to unsatisfied `malloc' and `free' references from the unwinder causing link errors with `ld.so' where libgcc has been built at -O0. libgcc/ * config/riscv/t-elf (LIB2_DIVMOD_EXCEPTION_FLAGS): New variable.
2020-09-29Daily bump.GCC Administrator1-0/+5
2020-09-28aarch64: Add HF routines to libgcc_s.soRichard Sandiford2-0/+29
The libgcc HF support routines were being linked into libgcc_s.so, but weren't being exported. libgcc/ * config/aarch64/libgcc-softfp.ver: New file. * config/aarch64/t-softfp (SHLIB_MAPFILES): Add it.
2020-09-28Daily bump.GCC Administrator1-0/+4
2020-09-27aix: Use $(AR) without -X32_64 to build FAT libraries.Clément Chigot1-10/+11
AIX FAT libraries should be built with the version of AR chosen by configure. The GNU Make $(AR) variable includes the AIX -X32_64 option needed by the default Makefile rules to accept both 32 bit and 64 bit object files. The -X32_64 option conflicts with ar archiving objects of the same name used to build FAT libraries. This patch changes the Makefile fragments for AIX FAT libraries to use $(AR), but strips the -X32_64 option from the Make variable. libgcc/ChangeLog: 2020-09-27 Clement Chigot <clement.chigot@atos.net> * config/rs6000/t-slibgcc-aix: Use $(AR) without -X32_64. libatomic/ChangeLog: 2020-09-27 Clement Chigot <clement.chigot@atos.net> * config/t-aix: Use $(AR) without -X32_64. libgomp/ChangeLog: 2020-09-27 Clement Chigot <clement.chigot@atos.net> * config/t-aix: Use $(AR) without -X32_64. libstdc++-v3/ChangeLog: 2020-09-27 Clement Chigot <clement.chigot@atos.net> * config/os/aix/t-aix: Use $(AR) without -X32_64. libgfortran/ChangeLog: 2020-09-27 Clement Chigot <clement.chigot@atos.net> * config/t-aix: Use $(AR) without -X32_64.
2020-09-23Daily bump.GCC Administrator1-0/+6
2020-09-22gcov: fix TOPN streaming from shared librariesSergei Trofimovich1-1/+1
Before the change gcc did not stream correctly TOPN counters if counters belonged to a non-local shared object. As a result zero-section optimization generated TOPN sections in a form not recognizable by '__gcov_merge_topn'. The problem happens because in a case of multiple shared objects '__gcov_merge_topn' function is present in address space multiple times (once per each object). The fix is to never rely on function address and predicate on TOPN counter types. libgcc/ChangeLog: PR gcov-profile/96913 * libgcov-driver.c (write_one_data): Avoid function pointer comparison in TOP streaming decision.
2020-09-18Daily bump.GCC Administrator1-0/+14
2020-09-17libgcc/config/arm/fp16.c: Make _internal functions static inlineChristophe Lyon1-1/+9
This patch makes the *_internal functions 'static inline' to avoid these warnings during the build: /libgcc/config/arm/fp16.c:169:1: warning: no previous prototype for '__gnu_h2f_internal' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:194:1: warning: no previous prototype for '__gnu_f2h_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:200:1: warning: no previous prototype for '__gnu_h2f_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:206:1: warning: no previous prototype for '__gnu_f2h_alternative' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:212:1: warning: no previous prototype for '__gnu_h2f_alternative' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:218:1: warning: no previous prototype for '__gnu_d2h_ieee' [-Wmissing-prototypes] /libgcc/config/arm/fp16.c:224:1: warning: no previous prototype for '__gnu_d2h_alternative' [-Wmissing-prototypes] 2020-09-11 Torbjörn SVENSSON <torbjorn.svensson@st.com> Christophe Lyon <christophe.lyon@linaro.org> libgcc/ * config/arm/fp16.c (__gnu_h2f_internal): Add 'static inline' qualifier. (__gnu_f2h_ieee, __gnu_h2f_ieee, __gnu_f2h_alternative) (__gnu_h2f_alternative,__gnu_d2h_ieee, __gnu_d2h_alternative): Add missing prototypes.
2020-09-17aarch64: Fixed unused variable warning in aarch64-unwind.hWei Wentao1-1/+2
libgcc/ * config/aarch64/aarch64-unwind.h (aarch64_demangle_return_addr): Fix unused variable warning.
2020-09-17Daily bump.GCC Administrator1-0/+4
2020-09-16C-SKY: Enable crtbegin/crtend.o of libgcc for elf targetJojo R1-1/+1
libgcc/ChangeLog: * config.host (C-SKY): Enable crtbegin/crtend.o of libgcc for elf target.
2020-09-10Daily bump.GCC Administrator1-0/+5
2020-09-09[nvptx, libgcc] Fix Wbuiltin-declaration-mismatch in atomic.cTom de Vries1-4/+8
When building for target nvptx, we get this and similar warnings for libgcc: ... src/libgcc/config/nvptx/atomic.c:39:1: warning: conflicting types for \ built-in function ‘__sync_val_compare_and_swap_1’; expected \ ‘unsigned char(volatile void *, unsigned char, unsigned char)’ \ [-Wbuiltin-declaration-mismatch] ... Fix this by making sure in atomic.c that the pointers used are of type 'volatile void *'. Tested by rebuilding atomic.c. libgcc/ChangeLog: * config/nvptx/atomic.c (__SYNC_SUBWORD_COMPARE_AND_SWAP): Fix Wbuiltin-declaration-mismatch.
2020-08-27Daily bump.GCC Administrator1-0/+6
2020-08-26MSP430: Simplify and extend shift instruction patternsJozef Lawrynowicz3-0/+46
The implementation of define_expand and define_insn patterns to handle shifts in the MSP430 backend is inconsistent, resulting in missed opportunities to make best use of the architecture's features. There's now a single define_expand used as the entry point for all valid shifts, and the decision to either use a helper function to perform the shift (often required for the 430 ISA), or fall through to the define_insn patterns can be made from that expander function. Shifts by a constant amount have been grouped into one define_insn for each type of shift, instead of having different define_insn patterns for shifts by different amounts. A new target option "-mmax-inline-shift=" has been added to allow tuning of the number of shift instructions to emit inline, instead of using a library helper function. gcc/ChangeLog: * config/msp430/constraints.md (K): Change unused constraint to constraint to a const_int between 1 and 19. (P): New constraint. * config/msp430/msp430-protos.h (msp430x_logical_shift_right): Remove. (msp430_expand_shift): New. (msp430_output_asm_shift_insns): New. * config/msp430/msp430.c (msp430_rtx_costs): Remove shift costs. (CSH): Remove. (msp430_expand_helper): Remove hard-coded generation of some inline shift insns. (use_helper_for_const_shift): New. (msp430_expand_shift): New. (msp430_output_asm_shift_insns): New. (msp430_print_operand): Add new 'W' operand selector. (msp430x_logical_shift_right): Remove. * config/msp430/msp430.md (HPSI): New define_mode_iterator. (HDI): Likewise. (any_shift): New define_code_iterator. (shift_insn): New define_code_attr. Adjust unnamed insn patterns searched for by combine. (ashlhi3): Remove. (slli_1): Remove. (430x_shift_left): Remove. (slll_1): Remove. (slll_2): Remove. (ashlsi3): Remove. (ashldi3): Remove. (ashrhi3): Remove. (srai_1): Remove. (430x_arithmetic_shift_right): Remove. (srap_1): Remove. (srap_2): Remove. (sral_1): Remove. (sral_2): Remove. (ashrsi3): Remove. (ashrdi3): Remove. (lshrhi3): Remove. (srli_1): Remove. (430x_logical_shift_right): Remove. (srlp_1): Remove. (srll_1): Remove. (srll_2x): Remove. (lshrsi3): Remove. (lshrdi3): Remove. (<shift_insn><mode>3): New define_expand. (<shift_insn>hi3_430): New define_insn. (<shift_insn>si3_const): Likewise. (ashl<mode>3_430x): Likewise. (ashr<mode>3_430x): Likewise. (lshr<mode>3_430x): Likewise. (*bitbranch<mode>4_z): Replace renamed predicate msp430_bitpos with const_0_to_15_operand. * config/msp430/msp430.opt: New option -mmax-inline-shift=. * config/msp430/predicates.md (const_1_to_8_operand): New predicate. (const_0_to_15_operand): Rename msp430_bitpos predicate. (const_1_to_19_operand): New predicate. * doc/invoke.texi: Document -mmax-inline-shift=. libgcc/ChangeLog: * config/msp430/slli.S (__gnu_mspabi_sllp): New. * config/msp430/srai.S (__gnu_mspabi_srap): New. * config/msp430/srli.S (__gnu_mspabi_srlp): New. gcc/testsuite/ChangeLog: * gcc.target/msp430/emulate-srli.c: Fix expected assembler text. * gcc.target/msp430/max-inline-shift-430-no-opt.c: New test. * gcc.target/msp430/max-inline-shift-430.c: New test. * gcc.target/msp430/max-inline-shift-430x.c: New test.
2020-08-14Daily bump.GCC Administrator1-0/+5
2020-08-13nvptx: Add support for subword compare-and-swapKwok Cheung Yeung2-1/+75
This adds support for __sync_val_compare_and_swap and __sync_bool_compare_and_swap for 1-byte and 2-byte long values, which are not natively supported on nvptx. Build and reg-tested on nvptx. Build and reg-tested libgomp on x86_64 with nvptx accelerator. 2020-07-16 Kwok Cheung Yeung <kcy@codesourcery.com> libgcc/ * config/nvptx/atomic.c: New. * config/nvptx/t-nvptx (LIB2ADD): Add atomic.c. gcc/testsuite/ * gcc.target/nvptx/ia64-sync-5.c: New. libgomp/ * testsuite/libgomp.c-c++-common/reduction-16.c: New.
2020-08-04Daily bump.GCC Administrator1-0/+10
2020-08-03libgcc: increase required stack space for x86_64 -fsplit-stackIan Lance Taylor1-1/+1
This accomodates increased space required by use of the xsavec instruction in the dynamic linker trampoline. libgcc/ChangeLog: * config/i386/morestack.S (BACKOFF) [x86_64]: Add 2048 bytes.
2020-08-03aarch64: Fix up __aarch64_cas16_acq_rel fallbackJakub Jelinek1-1/+1
As mentioned in the PR, the fallback path when LSE is unavailable writes incorrect registers to the memory if the previous content compares equal to x0, x1 - it writes copy of x0, x1 from the start of function, but it should write x2, x3. 2020-08-03 Jakub Jelinek <jakub@redhat.com> PR target/96402 * config/aarch64/lse.S (__aarch64_cas16_acq_rel): Use x2, x3 instead of x(tmp0), x(tmp1) in STXP arguments. * gcc.target/aarch64/pr96402.c: New test.
2020-08-01Daily bump.GCC Administrator1-0/+14
2020-07-31RISC-V/libgcc: Reduce the size of RV64 millicode by 6 bytesMaciej W. Rozycki1-6/+7
Rewrite code sequences throughout the 64-bit RISC-V `__riscv_save_*' routines replacing `li t1, -48', `li t1, -64', and `li t1, -80', instructions, which do not have a compressed encoding, respectively with `li t1, 3', `li t1, 4', and `li t1, 4', which do, and then adjusting the remaining code accordingly observing that `sub sp, sp, t1' takes the same amount of space as an `slli t1, t1, 4'/`add sp, sp, t1' instruction pair does, again due to the use of compressed encodings, saving 6 bytes total. This change does increase code size by 4 bytes for RISC-V processors lacking the compressed instruction set, however their users couldn't care about the code size or they would have chosen an implementation that does have the compressed instructions, wouldn't they? libgcc/ * config/riscv/save-restore.S [__riscv_xlen == 64] (__riscv_save_10, __riscv_save_8, __riscv_save_6, __riscv_save_4) (__riscv_save_2): Replace negative immediates used for the final stack pointer adjustment with positive ones, right-shifted by 4.
2020-07-31libgcov: support overloaded mallocMartin Liska2-2/+53
gcc/ChangeLog: * gcov-io.h (GCOV_PREALLOCATED_KVP): New. libgcc/ChangeLog: * libgcov-driver.c: Add __gcov_kvp_pool and __gcov_kvp_pool_index variables. * libgcov.h (allocate_gcov_kvp): New. (gcov_topn_add_value): Use it. gcc/testsuite/ChangeLog: * gcc.dg/tree-prof/indir-call-prof-malloc.c: New test.
2020-07-25Daily bump.GCC Administrator1-0/+4
2020-07-24aarch64: add PAC GNU property note to libgcc lse.SSzabolcs Nagy1-2/+15
This note is not used anywhere currently but it is supposed to mark objects if the return address is protected with PAC on the stack. Since lse.S only has leaf functions the return address is never saved on the stack so we can add the note. The note is only added if pac-ret is enabled because it can cause problems with old linkers and we don't have checks for that. This can be changed later to be unconditional, for now it is consistent with how gcc generates the notes. libgcc/ChangeLog: * config/aarch64/lse.S: Add PAC property note.
2020-07-24Daily bump.GCC Administrator1-0/+6
2020-07-23gcov: create folders with 0777.Martin Liska1-1/+1
libgcc/ChangeLog: PR gcov-profile/96035 * libgcov-driver-system.c: Create gcov folders with 0777 so that it respects a system umask.
2020-07-15Daily bump.GCC Administrator1-0/+4
2020-07-14aix: FAT libraries: test native compiler mode directlyDavid Edelsohn1-1/+1
The FAT libraries config fragments need to know which library is native and which is a multilib to choose the correct multilib from which to append the additional object file or shared object file. Testing the top-level archive is fragile because it will fail if rebuilding. This patch tests the compiler preprocessing macros for the 64 bit AIX specific __64BIT__ to determine the native mode of the compiler in MULTILIBTOP. 2020-07-14 David Edelsohn <dje.gcc@gmail.com> libatomic/ChangeLog * config/t-aix: Set BITS from compiler cpp macro. libgcc/ChangeLog * config/rs6000/t-slibgcc-aix: Set BITS from compiler cpp macro. libgfortran/ChangeLog * config/t-aix: Set BITS from compiler cpp macro. libgomp/ChangeLog * config/t-aix: Set BITS from compiler cpp macro. libstdc++-v3/ChangeLog * config/os/aix/t-aix: Set BITS from compiler cpp macro.
2020-07-14Daily bump.GCC Administrator1-0/+13
2020-07-13libgcc: fix the handling of return address mangling [PR94891]Szabolcs Nagy2-58/+16
Mangling, currently only used on AArch64 for return address signing, is an internal representation that should not be exposed via __builtin_return_address return value, __builtin_eh_return handler argument, _Unwind_DebugHook handler argument. Note that a mangled address might not even fit into a void *, e.g. with AArch64 ilp32 ABI the return address is stored as 64bit, so the mangled return address cannot be accessed via _Unwind_GetPtr. This patch changes the unwinder hooks as follows: MD_POST_EXTRACT_ROOT_ADDR is removed: root address comes from __builtin_return_address which is not mangled. MD_POST_EXTRACT_FRAME_ADDR is renamed to MD_DEMANGLE_RETURN_ADDR, it now operates on _Unwind_Word instead of void *, so the hook should work when return address signing is enabled on AArch64 ilp32. (But for that __builtin_aarch64_autia1716 should be fixed to operate on 64bit input instead of a void *.) MD_POST_FROB_EH_HANDLER_ADDR is removed: it is the responsibility of __builtin_eh_return to do the mangling if necessary. 2020-07-13 Szabolcs Nagy <szabolcs.nagy@arm.com> libgcc/ChangeLog: PR target/94891 * config/aarch64/aarch64-unwind.h (MD_POST_EXTRACT_ROOT_ADDR): Remove. (MD_POST_FROB_EH_HANDLER_ADDR): Remove. (MD_POST_EXTRACT_FRAME_ADDR): Rename to ... (MD_DEMANGLE_RETURN_ADDR): This. (aarch64_post_extract_frame_addr): Rename to ... (aarch64_demangle_return_addr): This. (aarch64_post_frob_eh_handler_addr): Remove. * unwind-dw2.c (uw_update_context): Demangle return address. (uw_frob_return_addr): Remove.
2020-07-10Daily bump.GCC Administrator1-0/+10
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