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2024-07-31diagnostics: SARIF output: eliminate some uses of "line_table" globalDavid Malcolm3-3/+16
No functional change intended. gcc/ChangeLog: * diagnostic-format-sarif.cc (sarif_builder::sarif_builder): Assert that m_line_maps is nonnull. (diagnostic_output_format_init_sarif_stderr): Add "line_maps" param and pass to format ctor. (diagnostic_output_format_init_sarif_file): Likewise. (diagnostic_output_format_init_sarif_stream): Likewise. * diagnostic.cc (diagnostic_output_format_init): Pass "line_table" as line_maps param to the above. * diagnostic.h (diagnostic_output_format_init_sarif_stderr): Add "line_maps" param. (diagnostic_output_format_init_sarif_file): Likewise. (diagnostic_output_format_init_sarif_stream): Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-07-31diagnostics: SARIF output: tweak ASCII art in commentDavid Malcolm1-6/+6
gcc/ChangeLog: * diagnostic-format-sarif.cc: Tweak ASCII art in comment to show edges for both directions in the digraph. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-08-01Daily bump.GCC Administrator4-1/+299
2024-07-31Fortran: Add newline character to test input.Jerry DeLisle1-1/+1
gcc/testsuite/ChangeLog: PR libfortran/105361 * gfortran.dg/pr105361.f90: Add newline character to test input to provide more compliant test.
2024-07-31match: Fix types matching for `(?:) !=/== (?:)` [PR116134]Andrew Pinski2-4/+15
The problem here is that in generic types of comparisons don't need to be boolean types (or vector boolean types). And fixes that by making sure the types of the conditions match before doing the optimization. Bootstrapped and tested on x86_64-linux-gnu with no regressions. PR middle-end/116134 gcc/ChangeLog: * match.pd (`(a ? x : y) eq/ne (b ? x : y)`): Check that a and b types match. (`(a ? x : y) eq/ne (b ? y : x)`): Likewise. gcc/testsuite/ChangeLog: * gcc.dg/torture/pr116134-1.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-07-31[target/116104] Fix more rtl-checking failures in ext-dceJeff Law1-4/+4
More enable-rtl-checking fixes for ext-dce. Very similar to the one recently posted, this time covering more of the shift ops. I checked all instances of CONSTANT_P guarding [U]INTVAL and fixed all that looked wrong. I also created a dummy assembler/linker so that I could run the GCC testsuite on gcn and verified that wasn't tripping any rtl-checking bugs in ext-dce anymore. Obviously this has also gone through x86 bootstrap and regression tested. Pushing to the trunk. pr target/116104 gcc/ * ext-dce.cc (carry_backpropagate): Change more guards of [U]INTVAL to test CONST_INT_P rather than CONSTANT_P, fixing rtl-checking failures.
2024-07-31pru: Enable section anchoring by defaultDimitar Dimitrov4-0/+46
Loading an arbitrary constant address in a register is expensive for PRU. So enable section anchoring by default to utilize the unsigned byte constant offset operand of load/store instructions. gcc/ChangeLog: * common/config/pru/pru-common.cc (TARGET_OPTION_OPTIMIZATION_TABLE): New definition. * config/pru/pru.cc (TARGET_MIN_ANCHOR_OFFSET): Set minimal anchor offset. (TARGET_MAX_ANCHOR_OFFSET): Set maximum anchor offset. gcc/testsuite/ChangeLog: * gcc.target/pru/section-anchors-1.c: New test. * gcc.target/pru/section-anchors-2.c: New test. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-07-31testsuite: Fix for targets not passing argc/argv [PR116154]Dimitar Dimitrov1-1/+3
PRU and other simulator targets do not pass any argv arguments to main. Instead of erroneously relying on argc==0, use a volatile variable instead. I reverted the fix for PR67947 in r6-3891-g8a18fcf4aa1d5c, and made sure that the updated test case still fails for x86_64: $ make check-gcc-c RUNTESTFLAGS="dg-torture.exp=pr67947.c" ... FAIL: gcc.dg/torture/pr67947.c -O1 execution test ... # of expected passes 8 # of unexpected failures 8 Fix was suggested by Andrew Pinski in PR116154. Committed as obvious. PR testsuite/116154 gcc/testsuite/ChangeLog: * gcc.dg/torture/pr67947.c: Use volatile variable instead of argc. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-07-31[PR rtl-optimization/116136] Fix previously latent SUBREG simplification bugJeff Law1-2/+3
This fixes a testsuite regression seen on m68k after some of the recent ext-dce changes. Ultimately Richard S and I have concluded the bug was a latent issue in subreg simplification. Essentially when simplifying something like (set (target:M1) (subreg:M1 (subreg:M2 (reg:M1) 0) 0)) Where M1 > M2. We'd simplify to: (set (target:M1) (reg:M1)) The problem is on a big endian target that's wrong. Consider if M1 is DI and M2 is SI. The original should extract bits 32..63 from the source register and store them into bits 0..31 of the target register. In the simplified form it's just a copy, so bits 0..63 of the source end up bits 0..63 of the target. This shows up as the following regressions on the m68k: > Tests that now fail, but worked before (3 tests): > > gcc: gcc.c-torture/execute/960416-1.c -O2 execution test > gcc: gcc.c-torture/execute/960416-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test > gcc: gcc.c-torture/execute/960416-1.c -Os execution test The fix is pretty trivial, instead of hardcoding "0" as the byte offset in the test for the simplification, instead we need to use the subreg_lowpart_offset. Anyway, bootstrapped and regression tested on m68k and x86_64 and tested on the other embedded targets as well without regressions. Naturally it fixes the regression noted above. I haven't see other testsuite improvements when I spot checked some of the big endian crosses. PR rtl-optimization/116136 gcc/ * simplify-rtx.cc (simplify_context::simplify_subreg): Check that we're working with the lowpart offset rather than byte 0.
2024-07-31testsuite: fix dg-require-* order vs dg-additional-sourcesSam James2-2/+2
Per gccint, 'dg-require-*' must come before any 'dg-additional-sources' directives. Fix a handful of deviant cases. * gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c: Fix dg-require-profiling directive order. * gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c: Likewise.
2024-07-31testsuite: fix dg-require-effective-target order vs dg-additional-sourcesSam James3-3/+3
Per gccint, 'dg-require-effective-target' must come before any 'dg-additional-sources' directives. Fix a handful of deviant cases. gcc/testsuite/ChangeLog: * gcc.target/aarch64/aapcs64/func-ret-3.c: Fix dg-require-effective-target directive order. * gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise. * gfortran.dg/PR100914.f90: Likewise. libgomp/ChangeLog: * testsuite/libgomp.c++/pr24455.C: Fix dg-require-effective-target directive order. * testsuite/libgomp.c/pr24455.c: Likewise.
2024-07-31testsuite: fix 'dg-do-preprocess' typoSam James1-1/+1
We want 'dg-do preprocess', not 'dg-do-preprocess'. Fix that. PR target/106828 * g++.target/loongarch/pr106828.C: Fix 'dg-do compile' typo.
2024-07-31testsuite: fix 'dg-do-compile' typosSam James4-4/+4
We want 'dg-do compile', not 'dg-do-compile'. Fix that. PR target/69194 PR c++/92024 PR c++/110057 * c-c++-common/Wshadow-1.c: Fix 'dg-do compile' typo. * g++.dg/tree-ssa/devirt-array-destructor-1.C: Likewise. * g++.dg/tree-ssa/devirt-array-destructor-2.C: Likewise. * gcc.target/arm/pr69194.c: Likewise.
2024-07-31aarch64: Add fpm register helper functions.Claudio Bantaloukas7-1/+160
The ACLE declares several helper types and functions to facilitate construction of `fpm` arguments. These are available when one of the arm_neon.h, arm_sve.h, or arm_sme.h headers is included. These helpers don't map to specific FP8 instructions and there's no expectation that they will produce a given code sequence, they're just an abstraction and an aid to the programmer. Thus they are implemented in a new header file arm_private_fp8.h Users are not expected to include this file, as it is a mere implementation detail, subject to change. A check is included to guard against direct inclusion. gcc/ChangeLog: * config.gcc (extra_headers): Install arm_private_fp8.h. * config/aarch64/arm_neon.h: Include arm_private_fp8.h. * config/aarch64/arm_sve.h: Likewise. * config/aarch64/arm_private_fp8.h: New file (fpm_t): New type representing fpmr values. (enum __ARM_FPM_FORMAT): New enum representing valid fp8 formats. (enum __ARM_FPM_OVERFLOW): New enum representing how some fp8 calculations work. (__arm_fpm_init): New. (__arm_set_fpm_src1_format): Likewise. (__arm_set_fpm_src2_format): Likewise. (__arm_set_fpm_dst_format): Likewise. (__arm_set_fpm_overflow_cvt): Likewise. (__arm_set_fpm_overflow_mul): Likewise. (__arm_set_fpm_lscale): Likewise. (__arm_set_fpm_lscale2): Likewise. (__arm_set_fpm_nscale): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/fp8-helpers-neon.c: New test of fpmr helper functions. * gcc.target/aarch64/acle/fp8-helpers-sve.c: New test of fpmr helper functions presence. * gcc.target/aarch64/acle/fp8-helpers-sme.c: New test of fpmr helper functions presence.
2024-07-31aarch64: Add support for moving fpm system registerClaudio Bantaloukas5-14/+142
Unlike most system registers, fpmr can be heavily written to in code that exercises the fp8 functionality. That is because every fp8 instrinsic call can potentially change the value of fpmr. Rather than just use an unspec, we treat the fpmr system register like all other registers and use a move operation to read and write to it. We introduce a new class of moveable system registers that, currently, only accepts fpmr and a new constraint, Umv, that allows us to selectively use mrs and msr instructions when expanding rtl for them. Given that there is code that depends on "real" registers coming before "fake" ones, we introduce a new constant FPM_REGNUM that uses an existing value and renumber registers below that. This requires us to update the bitmaps that describe which registers belong to each register class. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_hard_regno_nregs): Add support for MOVEABLE_SYSREGS class. (aarch64_hard_regno_mode_ok): Allow reads and writes to fpmr. (aarch64_regno_regclass): Support MOVEABLE_SYSREGS class. (aarch64_class_max_nregs): Likewise. * config/aarch64/aarch64.h (FIXED_REGISTERS): add fpmr. (CALL_REALLY_USED_REGISTERS): Likewise. (REGISTER_NAMES): Likewise. (enum reg_class): Add MOVEABLE_SYSREGS class. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Update class bitmaps to deal with fpmr, the new MOVEABLE_REGS class and renumbering of registers. * config/aarch64/aarch64.md: (FPM_REGNUM): added new register number, reusing old value. (FFR_REGNUM): Renumber. (FFRT_REGNUM): Likewise. (LOWERING_REGNUM): Likewise. (TPIDR2_BLOCK_REGNUM): Likewise. (SME_STATE_REGNUM): Likewise. (TPIDR2_SETUP_REGNUM): Likewise. (ZA_FREE_REGNUM): Likewise. (ZA_SAVED_REGNUM): Likewise. (ZA_REGNUM): Likewise. (ZT0_REGNUM): Likewise. (*mov<mode>_aarch64): Add support for moveable sysregs. (*movsi_aarch64): Likewise. (*movdi_aarch64): Likewise. * config/aarch64/constraints.md (MOVEABLE_SYSREGS): New constraint. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/fp8.c: New tests.
2024-07-31aarch64: Add march flags for +fp8 arch extensionsClaudio Bantaloukas4-0/+27
This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (fp8): New. * config/aarch64/aarch64.h (TARGET_FP8): Likewise. * doc/invoke.texi (AArch64 Options): Document new -march flags and extensions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/fp8.c: New test.
2024-07-31c++: array new with value-initialization, again [PR115645]Marek Polacek2-1/+42
Unfortunately, my r15-1946 fix broke the attached testcase; the constexpr evaluation reported an error about not being able to evaluate the code emitted by build_vec_init. Jason figured out it's because we were wrongly setting try_const to false, where in fact it should have been true. Value-initialization of scalars is constexpr, so we should check that alongside of type_has_constexpr_default_constructor. PR c++/115645 gcc/cp/ChangeLog: * init.cc (build_vec_init): When initializing a scalar type, try to create a constant initializer. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/constexpr-new23.C: New test.
2024-07-31testsuite: Adjust switch-exp-transform-3.c for 32bitFilip Kastl1-1/+6
32bit x86 CPUs won't natively support the FFS operation on a 64 bit type. Therefore, I'm setting the long long int part of the switch-exp-transform-3.c test to only execute with 64bit targets. gcc/testsuite/ChangeLog: * gcc.target/i386/switch-exp-transform-3.c: Set the long long int test to only execute with 64bit targets. Signed-off-by: Filip Kastl <fkastl@suse.cz>
2024-07-31LoongArch: Rework bswap{hi,si,di}2 definitionXi Ruoyao2-36/+104
Per a gcc-help thread we are generating sub-optimal code for __builtin_bswap{32,64}. To fix it: - Use a single revb.d instruction for bswapdi2. - Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT, revb.2h + rotri.w for !TARGET_64BIT. - Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single revb.2w instruction for bswapdi2 (x) r>> 32. Unfortunately I cannot figure out a way to make the compiler generate revb.4h or revh.{2w,d} instructions. gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H, UNSPEC_REVH_D): Remove UNSPECs. (revb_4h, revh_d): Remove define_insn. (revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of an UNSPEC. (revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn. (bswapsi2): Change to define_expand. Only expand to revb.2h + rotri.w if !TARGET_64BIT. (bswapdi2): Change to define_insn of which the output is just a revb.d instruction. gcc/testsuite/ChangeLog: * gcc.target/loongarch/revb.c: New test.
2024-07-31LoongArch: Relax ins_zero_bitmask_operand and remove and<mode>3_alignXi Ruoyao4-28/+11
In r15-1207 I was too stupid to realize we just need to relax ins_zero_bitmask_operand to allow using bstrins for aligning, instead of adding a new split. And, "> 12" in ins_zero_bitmask_operand also makes no sense: it rejects bstrins for things like "x & ~4l" with no good reason. So fix my errors now. gcc/ChangeLog: * config/loongarch/predicates.md (ins_zero_bitmask_operand): Cover more cases that bstrins can benefit. (high_bitmask_operand): Remove. * config/loongarch/constraints.md (Yy): Remove. * config/loongarch/loongarch.md (and<mode>3_align): Remove. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bstrins-4.c: New test.
2024-07-31middle-end/101478 - ICE with degenerate address during gimplificationRichard Biener2-1/+13
When we gimplify &MEM[0B + 4] we are re-folding the address in case types are not canonical which ends up with a constant address that recompute_tree_invariant_for_addr_expr ICEs on. Properly guard that call. PR middle-end/101478 * gimplify.cc (gimplify_addr_expr): Check we still have an ADDR_EXPR before calling recompute_tree_invariant_for_addr_expr. * gcc.dg/pr101478.c: New testcase.
2024-07-31i386: Mark target option with optimization when enabled with opt level ↵Hongyu Wang2-1/+25
[PR116065] When introducing munroll-only-small-loops, the option was marked as Target Save and added to -O2 default which makes attribute(optimize) resets target option and causing error when cmdline has O1 and funciton attribute has O2 and other target options. Mark this option as Optimization to fix. gcc/ChangeLog PR target/116065 * config/i386/i386.opt (munroll-only-small-loops): Mark as Optimization instead of Save. gcc/testsuite/ChangeLog PR target/116065 * gcc.target/i386/pr116065.c: New test.
2024-07-31recog: Disallow subregs in mode-punned value [PR115881]Richard Sandiford2-0/+37
In g:9d20529d94b23275885f380d155fe8671ab5353a, I'd extended insn_propagation to handle simple cases of hard-reg mode punning. The punned "to" value was created using simplify_subreg rather than simplify_gen_subreg, on the basis that hard-coded subregs aren't generally useful after RA (where hard-reg propagation is expected to happen). This PR is about a case where the subreg gets pushed into the operands of a plus, but the subreg on one of the operands cannot be simplified. Specifically, we have to generate (subreg:SI (reg:DI sp) 0) rather than (reg:SI sp), since all references to the stack pointer must be via stack_pointer_rtx. However, code in x86 (reasonably) expects no subregs of registers to appear after RA, except for special cases like strict_low_part. This leads to an awkward situation where we can't ban subregs of sp (because of the strict_low_part use), can't allow direct references to sp in other modes (because of the stack_pointer_rtx requirement), and can't allow rvalue uses of the subreg (because of the "no subregs after RA" assumption). It all seems a bit of a mess... I sat on this for a while in the hope that a clean solution might become apparent, but in the end, I think we'll just have to check manually for nested subregs and punt on them. gcc/ PR rtl-optimization/115881 * recog.cc: Include rtl-iter.h. (insn_propagation::apply_to_rvalue_1): Check that the result of simplify_subreg does not include nested subregs. gcc/testsuite/ PR rtl-optimization/115881 * gcc.c-torture/compile/pr115881.c: New test.
2024-07-30rs6000: Relax some FLOAT128 expander condition for FLOAT128_IEEE_P [PR105359]Kewen Lin2-14/+18
As PR105359 shows, we disable some FLOAT128 expanders for 64-bit long double, but in fact IEEE float128 types like __ieee128 are only guarded with TARGET_FLOAT128_TYPE and TARGET_LONG_DOUBLE_128 is only checked when determining if we can reuse long_double_type_node. So this patch is to relax all affected FLOAT128 expander conditions for FLOAT128_IEEE_P. By the way, currently IBM double double type __ibm128 is guarded by TARGET_LONG_DOUBLE_128, so we have to use TARGET_LONG_DOUBLE_128 for it. IMHO, it's not necessary and can be enhanced later. Btw, for all test cases mentioned in PR105359, I removed the xfails and tested them with explicit -mlong-double-64, both pr79004.c and float128-hw.c are tested well and float128-hw4.c isn't tested (unsupported due to 64 bit long double conflicts with -mabi=ieeelongdouble). PR target/105359 gcc/ChangeLog: * config/rs6000/rs6000.md (@extenddf<FLOAT128:mode>2): Don't check TARGET_LONG_DOUBLE_128 for FLOAT128_IEEE_P modes. (extendsf<FLOAT128:mode>2): Likewise. (trunc<FLOAT128:mode>df2): Likewise. (trunc<FLOAT128:mode>sf2): Likewise. (floatsi<FLOAT128:mode>2): Likewise. (fix_trunc<FLOAT128:mode>si2): Likewise. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr79004.c: Remove xfails.
2024-07-30rs6000: Use standard name uabd for absdu insnsKewen Lin4-18/+77
r14-1832 adds recognition pattern, ifn and optab for ABD (ABsolute Difference), we have some vector absolute difference unsigned instructions since ISA 3.0, as the associated test cases shown, they are not exploited well as we don't define it (them) with a standard name. So this patch is to rename it with standard name first. And it merges both define_expand and define_insn as a separated define_expand isn't needed. Besides, it adjusts the RTL pattern by using generic umax and umin rather than UNSPEC_VADU, it's more meaningful and can catch umin/umax opportunity. gcc/ChangeLog: * config/rs6000/altivec.md (p9_vadu<mode>3): Rename to ... (uabd<mode>3): ... this. Update RTL pattern with umin and umax rather than UNSPEC_VADU. (vadu<mode>3): Remove. (UNSPEC_VADU): Remove. (usadv16qi): Replace gen_p9_vaduv16qi3 with gen_uabdv16qi3. (usadv8hi): Replace gen_p9_vaduv8hi3 with gen_uabdv8hi3. * config/rs6000/rs6000-builtins.def (__builtin_altivec_vadub): Replace expander with uabdv16qi3. (__builtin_altivec_vaduh): Adjust expander with uabdv8hi3. (__builtin_altivec_vaduw): Adjust expander with uabdv4si3. gcc/testsuite/ChangeLog: * gcc.target/powerpc/abd-vectorize-1.c: New test. * gcc.target/powerpc/abd-vectorize-2.c: New test.
2024-07-31LoongArch: Expand some SImode operations through "si3_extend" instructions ↵Xi Ruoyao2-22/+154
if TARGET_64BIT We already had "si3_extend" insns and we hoped the fwprop or combine passes can use them to remove unnecessary sign extensions. But this does not always work: for cases like x << 1 | y, the compiler tends to do (sign_extend:DI (ior:SI (ashift:SI (reg:SI $r4) (const_int 1)) (reg:SI $r5))) instead of (ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1))) (sign_extend:DI (reg:SI $r5))) So we cannot match the ashlsi3_extend instruction here and we get: slli.w $r4,$r4,1 or $r4,$r5,$r4 slli.w $r4,$r4,0 # <= redundant jr $r1 To eliminate this redundant extension we need to turn SImode shift etc. to DImode "si3_extend" operations earlier, when we expand the SImode operation. We are already doing this for addition, now do it for shifts, rotates, substract, multiplication, division, and modulo as well. The bytepick.w definition for TARGET_64BIT needs to be adjusted so it won't be undone by the shift expanding. gcc/ChangeLog: * config/loongarch/loongarch.md (optab): Add (rotatert "rotr"). (<optab:any_shift><mode>3, <optab:any_div><mode>3, sub<mode>3, rotr<mode>3, mul<mode>3): Add a "*" to the insn name so we can redefine the names with define_expand. (*<optab:any_shift>si3_extend): Remove "*" so we can use them in expanders. (*subsi3_extended, *mulsi3_extended): Likewise, also remove the trailing "ed" for consistency. (*<optab:any_div>si3_extended): Add mode for sign_extend to prevent an ICE using it in expanders. (shift_w, arith_w): New define_code_iterator. (<optab:any_w><mode>3): New define_expand. Expand with <optab:any_w>si3_extend for SImode if TARGET_64BIT. (<optab:arith_w><mode>3): Likewise. (mul<mode>3): Expand to mulsi3_extended for SImode if TARGET_64BIT and ISA_HAS_DIV32. (<optab:any_div><mode>3): Expand to <optab:any_div>si3_extended for SImode if TARGET_64BIT. (rotl<mode>3): Expand to rotrsi3_extend for SImode if TARGET_64BIT. (bytepick_w_<bytepick_imm>): Add mode for lshiftrt and ashift. (bitsize, bytepick_imm, bytepick_w_ashift_amount): New define_mode_attr. (bytepick_w_<bytepick_imm>_extend): Adjust for the RTL change caused by 32-bit shift expanding. Now bytepick_imm only covers 2 and 3, separate one remaining case to ... (bytepick_w_1_extend): ... here, new define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bitwise_extend.c: New test.
2024-07-31Daily bump.GCC Administrator5-1/+335
2024-07-30testsuite: fix 'dg-compile' typosSam James32-32/+32
'dg-compile' is not a thing, replace it with 'dg-do compile'. PR target/68015 PR c++/83979 * c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo. * g++.dg/pr83979.C: Likewise. * g++.target/aarch64/sve/acle/general-c++/attributes_2.C: Likewise. * gcc.dg/tree-ssa/builtin-sprintf-7.c: Likewise. * gcc.dg/tree-ssa/builtin-sprintf-8.c: Likewise. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Likewise. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: Likewise. * gcc.target/s390/20181024-1.c: Likewise. * gcc.target/s390/addr-constraints-1.c: Likewise. * gcc.target/s390/arch12/aghsghmgh-1.c: Likewise. * gcc.target/s390/arch12/mul-1.c: Likewise. * gcc.target/s390/arch13/bitops-1.c: Likewise. * gcc.target/s390/arch13/bitops-2.c: Likewise. * gcc.target/s390/arch13/fp-signedint-convert-1.c: Likewise. * gcc.target/s390/arch13/fp-unsignedint-convert-1.c: Likewise. * gcc.target/s390/arch13/popcount-1.c: Likewise. * gcc.target/s390/pr68015.c: Likewise. * gcc.target/s390/vector/fp-signedint-convert-1.c: Likewise. * gcc.target/s390/vector/fp-unsignedint-convert-1.c: Likewise. * gcc.target/s390/vector/reverse-elements-1.c: Likewise. * gcc.target/s390/vector/reverse-elements-2.c: Likewise. * gcc.target/s390/vector/reverse-elements-3.c: Likewise. * gcc.target/s390/vector/reverse-elements-4.c: Likewise. * gcc.target/s390/vector/reverse-elements-5.c: Likewise. * gcc.target/s390/vector/reverse-elements-6.c: Likewise. * gcc.target/s390/vector/reverse-elements-7.c: Likewise. * gnat.dg/alignment15.adb: Likewise. * gnat.dg/debug4.adb: Likewise. * gnat.dg/inline21.adb: Likewise. * gnat.dg/inline22.adb: Likewise. * gnat.dg/opt37.adb: Likewise. * gnat.dg/warn13.adb: Likewise.
2024-07-30i386/testsuite: Add testcase for fixed PR [PR51492]Uros Bizjak1-0/+19
PR target/51492 gcc/testsuite/ChangeLog: * gcc.target/i386/pr51492.c: New test.
2024-07-30RISC-V: Add configure check for B extention supportEdwin Lu4-0/+50
Binutils 2.42 and before don't recognize the b extension in the march strings even though it supports zba_zbb_zbs. Add a configure check to ignore the b in the march string if found. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip b in march string * config.in: Regenerate. * configure: Regenerate. * configure.ac: Add B assembler check Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-07-30testsuite: fix whitespace in dg-require-effective-target directivesSam James3-3/+3
PR middle-end/54400 PR target/98161 * gcc.dg/vect/bb-slp-layout-18.c: Fix whitespace in dg directive. * gcc.dg/vect/bb-slp-pr54400.c: Likewise. * gcc.target/i386/pr98161.c: Likewise.
2024-07-30gimple ssa: Teach switch conversion to optimize powers of 2 switchesFilip Kastl6-6/+555
Sometimes a switch has case numbers that are powers of 2. Switch conversion usually isn't able to optimize these switches. This patch adds "exponential index transformation" to switch conversion. After switch conversion applies this transformation on the switch the index variable of the switch becomes the exponent instead of the whole value. For example: switch (i) { case (1 << 0): return 0; case (1 << 1): return 1; case (1 << 2): return 2; ... case (1 << 30): return 30; default: return 31; } gets transformed roughly into switch (log2(i)) { case 0: return 0; case 1: return 1; case 2: return 2; ... case 30: return 30; default: return 31; } This enables switch conversion to further optimize the switch. This patch only enables this transformation if there are optabs for FFS so that the base 2 logarithm can be computed efficiently at runtime. gcc/ChangeLog: * tree-switch-conversion.cc (can_log2): New static function to check if gen_log2 can be used on current target. (gen_log2): New static function to generate efficient GIMPLE code for taking an exact base 2 log. (gen_pow2p): New static function to generate efficient GIMPLE code for checking if a value is a power of 2. (switch_conversion::switch_conversion): Track if the transformation happened. (switch_conversion::is_exp_index_transform_viable): New function to decide whether the transformation should be applied. (switch_conversion::exp_index_transform): New function to execute the transformation. (switch_conversion::gen_inbound_check): Don't remove the default BB if the transformation happened. (switch_conversion::expand): Execute the transform if it is viable. Skip the "sufficiently small case range" test if the transformation is going to be executed. * tree-switch-conversion.h: Add is_exp_index_transform_viable and exp_index_transform. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/switch-3.c: Disable switch conversion. * gcc.target/i386/switch-exp-transform-1.c: New test. * gcc.target/i386/switch-exp-transform-2.c: New test. * gcc.target/i386/switch-exp-transform-3.c: New test. Signed-off-by: Filip Kastl <fkastl@suse.cz>
2024-07-30testsuite: fix whitespace in dg-do assemble directiveSam James1-1/+1
* gcc.target/aarch64/simd/vmmla.c: Fix whitespace in dg directive.
2024-07-30testsuite: fix whitespace in dg-do preprocess directiveSam James1-1/+1
PR preprocessor/90581 * c-c++-common/cpp/fmax-include-depth.c: Fix whitespace in dg directive.
2024-07-30testsuite: fix whitespace in dg-do compile directivesSam James29-29/+29
Nothing seems to change here in reality at least on x86_64-pc-linux-gnu, but important to fix nonetheless in case people copy it. PR rtl-optimization/48633 PR tree-optimization/83072 PR tree-optimization/83073 PR tree-optimization/96542 PR tree-optimization/96707 PR tree-optimization/97567 PR target/69225 PR target/89929 PR target/96562 * g++.dg/pr48633.C: Fix whitespace in dg directive. * g++.dg/pr96707.C: Likewise. * g++.target/i386/mv28.C: Likewise. * gcc.dg/Warray-bounds-flex-arrays-1.c: Likewise. * gcc.dg/pr83072-2.c: Likewise. * gcc.dg/pr83073.c: Likewise. * gcc.dg/pr96542.c: Likewise. * gcc.dg/pr97567-2.c: Likewise. * gcc.target/i386/avx512fp16-11a.c: Likewise. * gcc.target/i386/avx512fp16-13.c: Likewise. * gcc.target/i386/avx512fp16-14.c: Likewise. * gcc.target/i386/avx512fp16-conjugation-1.c: Likewise. * gcc.target/i386/avx512fp16-neg-1a.c: Likewise. * gcc.target/i386/avx512fp16-set1-pch-1a.c: Likewise. * gcc.target/i386/avx512fp16vl-conjugation-1.c: Likewise. * gcc.target/i386/avx512fp16vl-neg-1a.c: Likewise. * gcc.target/i386/avx512fp16vl-set1-pch-1a.c: Likewise. * gcc.target/i386/avx512vlfp16-11a.c: Likewise. * gcc.target/i386/pr69225-1.c: Likewise. * gcc.target/i386/pr69225-2.c: Likewise. * gcc.target/i386/pr69225-3.c: Likewise. * gcc.target/i386/pr69225-4.c: Likewise. * gcc.target/i386/pr69225-5.c: Likewise. * gcc.target/i386/pr69225-6.c: Likewise. * gcc.target/i386/pr69225-7.c: Likewise. * gcc.target/i386/pr96562-1.c: Likewise. * gcc.target/riscv/rv32e_stack.c: Likewise. * gfortran.dg/c-interop/removed-restrictions-3.f90: Likewise. * gnat.dg/renaming1.adb: Likewise.
2024-07-30RISC-V: Add basic support for the Zacas extensionGianluca Guida49-13/+901
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q (64/128 bit cas for rv32/64) will be added in a future patch. Extension: https://github.com/riscv/riscv-zacas Ratification: https://jira.riscv.org/browse/RVS-680 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zacas extension. * config/riscv/arch-canonicalize: Make zacas imply zaamo. * config/riscv/riscv.opt: Add zacas. * config/riscv/sync.md (zacas_atomic_cas_value<mode>): New pattern. (atomic_compare_and_swap<mode>): Use new pattern for compare-and-swap ops. (zalrsc_atomic_cas_value_strong<mode>): Rename atomic_cas_value_strong. * doc/sourcebuild.texi: Add Zacas documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zacas testsuite infra support. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Remove zacas to continue to test the lr/sc pairs. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test. * gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test. Co-authored-by: Patrick O'Neill <patrick@rivosinc.com> Tested-by: Andrea Parri <andrea@rivosinc.com> Signed-Off-By: Gianluca Guida <gianluca@rivosinc.com>
2024-07-30RISC-V: Remove configure check for zabhaPatrick O'Neill4-51/+3
This patch removes the zabha configure check since it's not a breaking change and updates the existing zaamo/zalrsc comment. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Remove zabha configure check handling and clarify zaamo/zalrsc comment. * config.in: Regenerate. * configure: Regenerate. * configure.ac: Remove zabha configure check. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2024-07-30c++: diagnose usage of co_await and co_yield in default args [PR115906]Arsen Arsenović5-3/+80
This is a partial fix for PR115906. Per [expr.await] 2s3, "An await-expression shall not appear in a default argument ([dcl.fct.default])". This patch introduces the diagnostic in that case, and in the case of a co_yield (as co_yield is defined in terms of co_await, so prerequisites of co_await hold). PR c++/115906 - [coroutines] missing diagnostic and ICE when co_await used as default argument in function declaration gcc/cp/ChangeLog: PR c++/115906 * parser.cc (cp_parser_unary_expression): Reject await expressions if use of local variables is currently forbidden. (cp_parser_yield_expression): Reject yield expressions if use of local variables is currently forbidden. gcc/testsuite/ChangeLog: PR c++/115906 * g++.dg/coroutines/pr115906-yield.C: New test. * g++.dg/coroutines/pr115906.C: New test. * g++.dg/coroutines/co-await-syntax-02-outside-fn.C: Don't rely on default arguments. * g++.dg/coroutines/co-yield-syntax-01-outside-fn.C: Ditto.
2024-07-30c++: fix ICE on FUNCTION_DECLs inside coroutines [PR115906]Arsen Arsenovic2-2/+21
When register_local_var_uses iterates a BIND_EXPRs BIND_EXPR_VARS, it fails to account for the fact that FUNCTION_DECLs might be present, and later passes it to DECL_HAS_VALUE_EXPR_P. This leads to a tree check failure in DECL_HAS_VALUE_EXPR_P: tree check: expected var_decl or parm_decl or result_decl, have function_decl in register_local_var_uses We only care about PARM_DECL and VAR_DECL, so select only those. PR c++/115906 - [coroutines] missing diagnostic and ICE when co_await used as default argument in function declaration gcc/cp/ChangeLog: PR c++/115906 * coroutines.cc (register_local_var_uses): Only process PARM_DECL and VAR_DECLs. gcc/testsuite/ChangeLog: PR c++/115906 * g++.dg/coroutines/coro-function-decl.C: New test.
2024-07-30SVE intrinsics: Add strength reduction for division by constant.Jennifer Schmitz6-57/+1031
This patch folds SVE division where all divisor elements are the same power of 2 to svasrd (signed) or svlsr (unsigned). Tests were added to check 1) whether the transform is applied (existing test harness was amended), and 2) correctness using runtime tests for all input types of svdiv; for signed and unsigned integers, several corner cases were covered. The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. OK for mainline? Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com> gcc/ * config/aarch64/aarch64-sve-builtins-base.cc (svdiv_impl::fold): Implement strength reduction. gcc/testsuite/ * gcc.target/aarch64/sve/div_const_run.c: New test. * gcc.target/aarch64/sve/acle/asm/div_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u64.c: Likewise.
2024-07-30c++: make source_location follow DECL_RAMP_FNArsen Arsenović2-1/+69
This fixes the value of current_function in compiler generated coroutine code. PR c++/110855 - std::source_location doesn't work with C++20 coroutine gcc/cp/ChangeLog: PR c++/110855 * cp-gimplify.cc (fold_builtin_source_location): Use the name of the DECL_RAMP_FN of the current function if present. gcc/testsuite/ChangeLog: PR c++/110855 * g++.dg/coroutines/pr110855.C: New test.
2024-07-30testsuite: fix dg-do run whitespaceSam James5-5/+5
This caused the tests to not be run. I may do further passes for non-run next. Tested on x86_64-pc-linux-gnu and checked test logs before/after. PR c/53548 PR target/101529 PR tree-optimization/102359 * c-c++-common/fam-in-union-alone-in-struct-1.c: Fix whitespace in dg directive. * c-c++-common/fam-in-union-alone-in-struct-2.c: Likewise. * c-c++-common/torture/builtin-shufflevector-2.c: Likewise. * g++.dg/pr102359_2.C: Likewise. * g++.target/i386/mvc1.C: Likewise.
2024-07-30Fix warnings for tree formats in gfc_errorPaul-Antoine Arras1-0/+4
This enables proper warnings for formats like %qD. gcc/c-family/ChangeLog: * c-format.cc (gcc_gfc_char_table): Add formats for tree objects.
2024-07-30gfortran.dg/compiler-directive_2.f: Update dg-errorTobias Burnus1-1/+1
This is a fallout of commit r15-2378-g29b1587e7d3466 OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause [PR115559] where the '!GCC$' attributes were added in reverse order. Result: The error diagnostic for the stdcall/fastcall was reversed. Solution: Swap the order in dg-error. gcc/testsuite/ChangeLog: * gfortran.dg/compiler-directive_2.f: Update dg-error.
2024-07-30AVR: Propose to use attribute signal(n) via AVR-LibC's ISR_N.Georg-Johann Lay1-7/+23
gcc/ * doc/extend.texi (AVR Function Attributes): Propose to use attribute signal(n) via AVR-LibC's ISR_N from avr/interrupt.h
2024-07-30RISC-V: Take Xmode instead of Pmode for ussub expandingPan Li1-12/+12
The Pmode is designed for pointer, thus leverage the Xmode instead for the expanding of the ussub. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_ussub): Promote to Xmode instead of Pmode. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-29xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COSTTakayuki 'January June' Suwa1-0/+1
According to the implemented pipeline model, this cost can be assumed to be 1 clock cycle. gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_insn_cost): Add a case statement for TYPE_FARITH.
2024-07-29xtensa: Fix suboptimal loading of pooled constant value into hardware ↵Takayuki 'January June' Suwa1-5/+5
single-precision FP register We would like to implement the following to store a single-precision FP constant in a hardware FP register: - Load the bit-exact integer image of the pooled single-precision FP constant into an address (integer) register - Then, assign from that address register to a hardware single-precision FP register .literal_position .literal .LC1, 0x3f800000 ... l32r a9, .LC1 wfr f0, a9 However, it was emitted as follows: - Load the address of the FP constant entry in litpool into an address register - Then, dereference the address via that address register into a hardware single-precision FP register .literal_position .literal .LC1, 0x3f800000 .literal .LC2, .LC1 ... l32r a9, .LC2 lsi f0, a9, 0 It is obviously inefficient to read the pool twice. gcc/ChangeLog: * config/xtensa/xtensa.md (movsf_internal): Reorder alternative that corresponds to L32R machine instruction, and prefix alternatives that correspond to LSI/SSI instructions with the constraint character '^' so that they are disparaged by reload/LRA.
2024-07-29xtensa: Fix the regression introduce by r15-959-gbe9b3f4375e7Takayuki 'January June' Suwa3-14/+7
It is not wrong but also not optimal to specify that sibcalls require register A0 in RTX generation pass, by misleading DFA into thinking it is being used in function body. It would be better to specify it in pro_and_epilogue as with 'return' insn in order to avoid incorrect removing load that restores A0 in subsequent passes, but since it is not possible to modify each sibcall there, as a workaround we will preface it with a 'use' as before. This patch effectively reverts commit r15-959-gbe9b3f4375e7 gcc/ChangeLog: * config/xtensa/xtensa-protos.h (xtensa_expand_call): Remove the third argument. * config/xtensa/xtensa.cc (xtensa_expand_call): Remove the third argument and the code that uses it. * config/xtensa/xtensa.md (call, call_value, sibcall, sibcall_value): Remove each Boolean constant specified in the third argument of xtensa_expand_call. (sibcall_epilogue): Add emitting '(use A0_REG)' after calling xtensa_expand_epilogue.
2024-07-30Refine constraint "Bk" to define_special_memory_constraint.liuhongt2-1/+34
For below pattern, RA may still allocate r162 as v/k register, try to reload for address with leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rsi which result a linker error. (set (reg:DI 162) (mem/u/c:DI (const:DI (unspec:DI [(symbol_ref:DI ("a") [flags 0x60] <var_decl 0x7f621f6e1c60 a>)] UNSPEC_GOTNTPOFF)) Quote from H.J for why linker issue an error. >What do these do: > > leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rax > vmovq (%rax), %xmm0 > >From x86-64 TLS psABI: > >The assembler generates for the x@gottpoff(%rip) expressions a R X86 >64 GOTTPOFF relocation for the symbol x which requests the linker to >generate a GOT entry with a R X86 64 TPOFF64 relocation. The offset of >the GOT entry relative to the end of the instruction is then used in >the instruction. The R X86 64 TPOFF64 relocation is pro- cessed at >program startup time by the dynamic linker by looking up the symbol x >in the modules loaded at that point. The offset is written in the GOT >entry and later loaded by the addq instruction. > >The above code sequence looks wrong to me. gcc/ChangeLog: PR target/116043 * config/i386/constraints.md (Bk): Refine to define_special_memory_constraint. gcc/testsuite/ChangeLog: * gcc.target/i386/pr116043.c: New test.
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