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Copy the location info from the passed in call stmt
to the newly built gimple call stmt.
2020-12-07 Bernd Edlinger <bernd.edlinger@hotmail.de>
* ipa-param-manipulation.c
(ipa_param_body_adjustments::modify_call_stmt): Set location info.
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gcc/ChangeLog:
* doc/extend.texi (used function attribute): Document saving
the declaration from linker garbage collection.
(used variable attribute): Likewise.
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This adds the capability to handle a sequence of vector BIT_INSERT_EXPRs
to be vectorized similar as to how we vectorize vector constructors.
2020-12-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/98113
* tree-vectorizer.h (struct slp_root): New.
(_bb_vec_info::roots): New member.
* tree-vect-slp.c (vect_analyze_slp): Also walk BB info
roots.
(_bb_vec_info::_bb_vec_info): Adjust.
(_bb_vec_info::~_bb_vec_info): Likewise.
(vld_cmp): New.
(vect_slp_is_lane_insert): Likewise.
(vect_slp_check_for_constructors): Match a series of
BIT_INSERT_EXPRs as vector constructor.
(vect_slp_analyze_bb_1): Continue if BB info roots is
not empty.
(vect_slp_analyze_bb_1): Mark the whole BIT_INSERT_EXPR root
sequence as pure_slp.
* gcc.dg/vect/bb-slp-70.c: New testcase.
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This avoids the degenerate case of a TYPE_MAX_VALUE latch iteration
count value causing wrong range info for the vector IV. There's
still the case of VF == 1 where if we don't know whether we hit the
above case we cannot emit a range.
2020-12-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/98117
* tree-vect-loop-manip.c (vect_gen_vector_loop_niters):
Properly handle degenerate niter when setting the vector
loop IV range.
* gcc.dg/torture/pr98117.c: New testcase.
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gcc/ada/ChangeLog:
* gcc-interface/Make-lang.in: Remove ^L characters.
* gcc-interface/decl.c (create_concat_name): Add cast.
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The compiler aborts on the local extension of a tagged type declared
at library level, with a progenitor given by an interface type having
a primitive that is a homograph of a primitive of the tagged type.
gcc/ada/ChangeLog:
* gcc-interface/trans.c (maybe_make_gnu_thunk): Return false if the
target is local and thunk and target do not have the same context.
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Gigi uses a dummy global variable to register global types for debug
info purposes and its name can now collide with user variables.
gcc/ada/ChangeLog:
* gcc-interface/trans.c (lvalue_for_aggregate_p): Also return true
for return statements.
* gcc-interface/utils.c (gnat_write_global_declarations): Use the
maximum index for the dummy object to avoid a name collision.
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gcc/ada/ChangeLog:
* gcc-interface/decl.c (gnat_to_gnu_entity) <Fixed_Point_Type>: Put
back the "else" unduly removed.
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The compiler generates code that writes too much data into a component
of a record subject to a representation clause, when the source of the
assignment is a call to a function that returns a discriminated record
type with default discriminants, variable size and a statically known
upper bound for this size, and the size of the component given by the
representation clause is lower than the value of this bound rounded up
to the alignment.
gcc/ada/ChangeLog:
* gcc-interface/trans.c (Call_to_gnu): Also create a temporary for
the return value if the LHS is a bit-field and the return type is
a type padding a self-referential type.
(gnat_to_gnu): Do not remove the padding on the result if it is too
small with regard to the natural padding size.
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The new ranger exposed a problematic conversion to boolean type.
gcc/ada/ChangeLog:
* gcc-interface/utils.c (convert) <INTEGER_TYPE>: Call fold_convert
in the cases where convert_to_integer is not called.
<BOOLEAN_TYPE>: Call fold_convert instead of convert_to_integer.
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In s390.c we are still using Pmode for the stack probes. This breaks
with -m31 -mzarch where Pmode != word_mode.
The patch also adds a new target check to s390.exp which allows us to
implement zarch specific checks in the testcases.
gcc/ChangeLog:
* config/s390/s390.c (s390_emit_stack_probe): Change Pmode to
word_mode.
gcc/testsuite/ChangeLog:
* gcc.target/s390/s390.exp: New target check s390_zarch.
* gcc.target/s390/stack-clash-1.c: Use s390_zarch instead of lp64.
* gcc.target/s390/stack-clash-2.c: Likewise.
* gcc.target/s390/stack-clash-3.c: Likewise.
* gcc.target/s390/stack-clash-5.c: New test.
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2020-12-07 Matthias Klose <doko@ubuntu.com>
PR ada/97504
* Makefile.rtl (LIBGNAT_TARGET_PAIRS) <mips*-*-linux*>: Use wraplf
version of Aux_Long_Long_Float.
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When looking at the testcase of PR 97816 I realized that the reason
why we were hitting overflows in size growth estimates in IPA-CP is
not because the chains of how lattices feed values to each other are
so long but mainly because we add estimates in callee lattices to
caller lattices for each value source, which roughly corresponds to a
call graph edge, and therefore if there are multiple calls between two
functions passing the same value in a parameter we end up doing it
more than once, sometimes actually quite many times.
This patch avoids it by using a has_set to remember the source values
we have already updated and not increasing their size again.
Furhtermore, to improve estimation of times we scale the propagated
time benefits with edge frequencies as we accumulate them.
This should make any overflows very unlikely but not impossible, so I
still included checks for overflows but decided to restructure the
code to only need it in the propagate_effects function and modified it
so that it does not need to perform the check before each sum.
This is because I decided to add local estimates to propagated
estimates already in propagate_effects and not at the evaluation time.
The function can then do the sums in a wide type and discard them in
the unlikely case of an overflow. I also decided to use the
opportunity to make propagated effect stats now include stats from
other values in the same SCCs. In the dumps I have seen this tended
to increase size cost a tiny bit more than the estimated time benefit
but both increases were small.
Martin
gcc/ChangeLog:
2020-11-20 Martin Jambor <mjambor@suse.cz>
PR ipa/97816
* ipa-cp.c (safe_add): Removed.
(good_cloning_opportunity_p): Remove special handling of INT_MAX.
(value_topo_info<valtype>::propagate_effects): Take care not to
propagate from size one value to another through more sources. Scale
propagated times with edge frequencies. Include local time and size
in propagates ones here. Take care not to overflow size.
(decide_about_value): Do not add local and propagated effects when
passing them to good_cloning_opportunity_p.
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As seen in PR98144, building insn-extract.o with rtl checking takes some memory,
and it doesn't work on 32bit architectures at all (PR97314). Richard suggested
on irc to disable rtl checking for this auto-generated file, like it's already
done for genconditions.c. Patching it like done for genconditons.c.
2020-12-07 Matthias Klose <doko@ubuntu.com>
* genextract.c (print_header): Undefine ENABLE_RTL_CHECKING
and ENABLE_RTL_FLAG_CHECKING.
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split_constant_offset currently gives up looking at ranges when
dealing with possibly wrapping operations for looking through
conversions when the downstream analysis does not yield a SSA name.
That's overly conservative and we have a nice helper that can
deal with arbitrary expresssions. Use that. This helps data
reference group analysis so the testcase is fully SLP vectorized,
making use of the whole-function "BB" vectorization capabilities
we now have.
2020-12-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/98137
* tree-data-ref.c (split_constant_offset_1): Use
determine_value_range instead of get_range_info to handle
arbitrary expressions.
* gcc.dg/vect/bb-slp-pr98137.c: New testcase.
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-mcet was removed by
commit 231baae28ef7ff784683fa5a80df119da2b9a99b
Author: H.J. Lu <hongjiu.lu@intel.com>
Date: Tue Apr 24 16:56:04 2018 +0000
x86/CET: Remove the -mcet command-lint option
PR target/98162
* doc/extend.texi: Remove -mcet.
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commit 266f44a91c0c9705d3d18e82d7c5bab32927a18f
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Sun May 17 10:10:34 2020 -0700
x86: Allow V1TI vector register pushes
Add V1TI vector register push and split it after reload to a sequence
of:
(set (reg:P SP_REG) (plus:P SP_REG) (const_int -8)))
(set (match_dup 0) (match_dup 1))
added a pseudo register push check. But
(insn 13 12 14 3 (set (mem:SI (pre_dec:SI (reg/f:SI 7 sp)) [0 S4 A32])
(reg/v:SI 87 [ srclen ])) "x.c":37:16 54 {*pushsi2}
(expr_list:REG_DEAD (reg/v:SI 87 [ srclen ])
(expr_list:REG_ARGS_SIZE (const_int 4 [0x4])
(nil))))
is not a pseudo register push. In 64-bit mode, mode of pseudo register
push is TImode. In 32-bit mode, it is DImode. Add pseudo register push
mode check to pseudo_reg_set.
gcc/
PR target/98161
* config/i386/i386-features.c (pseudo_reg_set): Check mode of
pseudo register push.
gcc/testsuite/
* gcc.target/i386/pr98161.c: New test.
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The following patch improves code generation on the included testcase by
enabling two_value_replacement on booleans. It does that only for arg0/arg1
values that conditional_replacement doesn't handle. Additionally
it limits two_value_replacement optimization to the late phiopt like
conditional_replacement.
2020-12-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/96232
* tree-ssa-phiopt.c (two_value_replacement): Optimize even boolean lhs
cases as long as arg0 has wider precision and conditional_replacement
doesn't handle that case.
(tree_ssa_phiopt_worker): Don't call two_value_replacement during
early phiopt.
* gcc.dg/tree-ssa/pr96232-2.c: New test.
* gcc.dg/tree-ssa/pr88676-2.c: Check phiopt2 dump rather than phiopt1.
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As mentioned in the PR, for boolean x we currently optimize
in phiopt x ? 0 : -1 into -(int)!x but it can be optimized as
(int) x - 1 which is one less operation both in GIMPLE and in x86 assembly.
This patch optimizes it in match.pd, by optimizing -(type)!x when
x has boolean range into (type)x - 1.
2020-12-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/96232
* match.pd (-(type)!A -> (type)A - 1): New optimization.
* gcc.dg/tree-ssa/pr96232-1.c: New test.
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gcc/testsuite/ChangeLog:
PR testsuite/98156
* gfortran.dg/coarray/alloc_comp_1.f90: Upper cobound is
determined by num_images(), not this_image().
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Fixes
FAIL: gcc.target/powerpc/signbit-1.c scan-assembler-not stxvd2x
FAIL: gcc.target/powerpc/signbit-1.c scan-assembler-times mfvsrd 3
FAIL: gcc.target/powerpc/signbit-1.c scan-assembler-times srdi 3
FAIL: gcc.target/powerpc/signbit-2.c scan-assembler-times ld 1
FAIL: gcc.target/powerpc/signbit-2.c scan-assembler-times srdi 1
on powerpc-linux (or powerpc64-linux biarch -m32).
signbit-1.c is quite obviously a 64-bit only testcase given the
scan-assembler directives, and the purpose of the testcase to verify
the 64-bit only UNSPEC_SIGNBIT patterns. It could be made to pass for
-m32 by adding -mpowerpc64, but that option that isn't very effective
when bi-arch testing and results in errors on rs6000-aix. And it is
pointless to match -m32 stores to the stack followed by loads, which
is what we do at the moment.
signbit-2.c on the other hand has more reasonable 32-bit output.
* gcc.target/powerpc/signbit-1.c: Reinstate lp64 condition.
* gcc.target/powerpc/signbit-2.c: Match 32-bit output too.
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ASM_OUTPUT_DEF is used by GCC as a proxy to enable alias support. But
the macro does not provide the necessary implementation for symbol aliasing
on AIX, which uses a different implementation. On AIX, the macro was empty.
Because the macro is empty, none of the macro argument are used, which
means that some of the variables in the function that calls the macro are
never used. This causes a warning when building varasm.c, and -Werror
converts that into a fatal error.
This patch references the macro arguments as (void) to prevent the
warning.
2020-12-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
David Edelsohn <dje.gcc@gmail.com>
gcc/ChangeLog:
* config/rs6000/xcoff.h (ASM_OUTPUT_DEF): Reference macro arguments.
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The re-normalization performed from diagnose_nested_requirement doesn't
always work because we may have already lost the necessary template
context that determines the set of in-scope template parameters used by
the nested-requirement. This leads to normalization producing atoms
that have incomplete/bogus parameter mappings, which breaks satisfaction.
To fix this, we could just use the normal form that we previously
computed at parse time, but this normal form lacks the diagnostic
information that leads to good error messages.
Instead, this patch makes diagnose_nested_requirement normalize twice at
parse time -- once without diagnostic information and once with -- so
that routines can use the "regular" normal form when performing
satisfaction quietly and the "diagnostic" normal form when performing
satisfaction noisily. Moreover, this patch makes tsubst_nested_requirement
always first perform satisfaction quietly so that the satisfaction cache
can get consistently utilized.
This patch also adds some sanity checks to build_parameter_mapping that
would have caught the underlying bug sooner (and deterministically).
gcc/cp/ChangeLog:
PR c++/97093
* constraint.cc (parameter_mapping_equivalent_p): Add some
sanity checks. Clarify comment.
(tsubst_nested_requirement): Always perform satisfaction
quietly first. If that yields an erroneous result, emit a
context message and replay satisfaction noisily with the
diagnostic normal form.
(finish_nested_requirement): Normalize the constraint-expression
twice, once with diagnostic information and once without. Store
them in a TREE_LIST within the TREE_TYPE.
(diagnose_nested_requirement): When replaying satisfaction, use
the diagnostic normal form instead of renormalizing on the spot.
gcc/testsuite/ChangeLog:
PR c++/97093
* g++.dg/cpp2a/concepts-requires22.C: New test.
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During satisfaction, the flag info.noisy() controls three things:
whether to diagnose ill-formed satisfaction (such as the satisfaction
value of an atom being non-bool or non-constant); whether to diagnose
unsatisfaction; and whether to bypass the satisfaction cache.
The flag turns out to be too coarse however, because in some cases we
want to diagnose ill-formed satisfaction (and bypass the satisfaction
cache) but not diagnose unsatisfaction, for instance when replaying an
erroneous satisfaction result from constraint_satisfaction_value,
evaluate_concept_check and tsubst_nested_requirement.
And when noisily evaluating a disjunction, we want to first evaluate its
branches noisily (bypassing the satisfaction cache) but suppress
unsatisfaction diagnostics. We currently work around this by instead
first evaluating each branch quietly, but that means the recursive calls
to satisfy_atom will use the satisfaction cache.
To fix this, this patch adds the info.diagnose_unsatisfaction_p() flag,
which refines the info.noisy() flag as part of a new sat_info class that
derives from subst_info. During satisfaction, info.noisy() now controls
whether to diagnose ill-formed satisfaction, and
info.diagnose_unsatisfaction_p() controls whether to additionally
diagnose unsatisfaction. This enables us to address the above two
issues straightforwardly.
Incidentally, the change to satisfy_disjunction suppresses the ICE in
the PR97093 testcase because we no longer insert atoms into the
satisfaction cache that have been incorrectly re-normalized in
diagnose_nested_requirement (after losing the necessary template
context). But the underlying re-normalization issue remains, and will
be fixed in a subsequent patch.
gcc/cp/ChangeLog:
PR c++/97093
* constraint.cc (struct sat_info): Define.
(tsubst_nested_requirement): Pass a sat_info object to
satisfy_constraint.
(satisfy_constraint_r): Take a sat_info argument instead of
subst_info.
(satisfy_conjunction): Likewise.
(satisfy_disjunction): Likewise. Instead of first evaluating
each branch quietly, evaluate each branch only with
unsatisfaction diagnostics disabled. Exit early if evaluation
of a branch returns error_mark_node.
(satisfy_atom): Take a sat_info argument instead of subst_info.
Fix a comment. Check diagnose_unsatisfaction_p() instead of
noisy() before replaying a substitution failure.
(satisfy_constraint): Take a sat_info argument instead of
subst_info.
(satisfy_associated_constraints): Likewise.
(satisfy_constraint_expression): Likewise.
(satisfy_declaration_constraints): Likewise.
(constraint_satisfaction_value): Likewise and adjust
accordingly. Fix formatting.
(constraints_satisfied_p): Pass a sat_info object to
constraint_satisfaction_value.
(evaluate_concept_check): Pass a sat_info object to
satisfy_constraint_expression.
(diagnose_nested_requirement): Likewise.
(diagnose_constraints): Pass an appropriate sat_info object to
constraint_satisfaction_value.
gcc/testsuite/ChangeLog:
PR c++/97093
* g++.dg/concepts/pr94252.C: Verify we no longer issue a
spurious unsatisfaction note when diagnosing ill-formed
satisfaction.
* g++.dg/cpp2a/concepts-requires18.C: No longer expect a
spurious unsatisfaction diagnostic when evaluating the
nested-requirement subst<void&> of a requires-expression that
appears outside of a template.
* g++.dg/cpp2a/concepts-requires21.C: Verify we no longer issue
a spurious unsatisfaction note when evaluating a
nested-requirement of a requires-expression that appears outside
of a template.
* g++.dg/cpp2a/concepts-nonbool3.C: New test.
* g++.dg/cpp2a/concepts-pr97093.C: New test.
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gcc/testsuite/
PR target/95294
* gcc.target/vax/cmpelim-eq-adddf.c: New test.
* gcc.target/vax/cmpelim-eq-addhi.c: New test.
* gcc.target/vax/cmpelim-eq-addqi.c: New test.
* gcc.target/vax/cmpelim-eq-addsf.c: New test.
* gcc.target/vax/cmpelim-eq-addsi.c: New test.
* gcc.target/vax/cmpelim-eq-andhi.c: New test.
* gcc.target/vax/cmpelim-eq-andqi.c: New test.
* gcc.target/vax/cmpelim-eq-andsi.c: New test.
* gcc.target/vax/cmpelim-eq-ashlsi.c: New test.
* gcc.target/vax/cmpelim-eq-ashrsi.c: New test.
* gcc.target/vax/cmpelim-eq-divdf.c: New test.
* gcc.target/vax/cmpelim-eq-divhi.c: New test.
* gcc.target/vax/cmpelim-eq-divqi.c: New test.
* gcc.target/vax/cmpelim-eq-divsf.c: New test.
* gcc.target/vax/cmpelim-eq-divsi.c: New test.
* gcc.target/vax/cmpelim-eq-extendhisi.c: New test.
* gcc.target/vax/cmpelim-eq-extendqisi.c: New test.
* gcc.target/vax/cmpelim-eq-extvsi.c: New test.
* gcc.target/vax/cmpelim-eq-extzvsi.c: New test.
* gcc.target/vax/cmpelim-eq-fixdfhi.c: New test.
* gcc.target/vax/cmpelim-eq-fixdfqi.c: New test.
* gcc.target/vax/cmpelim-eq-fixdfsi.c: New test.
* gcc.target/vax/cmpelim-eq-fixsfhi.c: New test.
* gcc.target/vax/cmpelim-eq-fixsfqi.c: New test.
* gcc.target/vax/cmpelim-eq-fixsfsi.c: New test.
* gcc.target/vax/cmpelim-eq-floatsisf.c: New test.
* gcc.target/vax/cmpelim-eq-insvsi.c: New test.
* gcc.target/vax/cmpelim-eq-iorhi.c: New test.
* gcc.target/vax/cmpelim-eq-iorqi.c: New test.
* gcc.target/vax/cmpelim-eq-iorsi.c: New test.
* gcc.target/vax/cmpelim-eq-mova.c: New test.
* gcc.target/vax/cmpelim-eq-movdf.c: New test.
* gcc.target/vax/cmpelim-eq-movhi.c: New test.
* gcc.target/vax/cmpelim-eq-movqi.c: New test.
* gcc.target/vax/cmpelim-eq-movsf.c: New test.
* gcc.target/vax/cmpelim-eq-movsi.c: New test.
* gcc.target/vax/cmpelim-eq-muldf.c: New test.
* gcc.target/vax/cmpelim-eq-mulhi.c: New test.
* gcc.target/vax/cmpelim-eq-mulqi.c: New test.
* gcc.target/vax/cmpelim-eq-mulsf.c: New test.
* gcc.target/vax/cmpelim-eq-mulsi.c: New test.
* gcc.target/vax/cmpelim-eq-nothi.c: New test.
* gcc.target/vax/cmpelim-eq-notqi.c: New test.
* gcc.target/vax/cmpelim-eq-notsi.c: New test.
* gcc.target/vax/cmpelim-eq-rotlsi.c: New test.
* gcc.target/vax/cmpelim-eq-rotrsi.c: New test.
* gcc.target/vax/cmpelim-eq-subdf.c: New test.
* gcc.target/vax/cmpelim-eq-subhi.c: New test.
* gcc.target/vax/cmpelim-eq-subqi.c: New test.
* gcc.target/vax/cmpelim-eq-subsf.c: New test.
* gcc.target/vax/cmpelim-eq-subsi.c: New test.
* gcc.target/vax/cmpelim-eq-truncdfsf.c: New test.
* gcc.target/vax/cmpelim-eq-trunchiqi.c: New test.
* gcc.target/vax/cmpelim-eq-truncsihi.c: New test.
* gcc.target/vax/cmpelim-eq-truncsiqi.c: New test.
* gcc.target/vax/cmpelim-eq-zextendhisi.c: New test.
* gcc.target/vax/cmpelim-eq-zextendqihi.c: New test.
* gcc.target/vax/cmpelim-eq-zextendqisi.c: New test.
* gcc.target/vax/cmpelim-le-adddf.c: New test.
* gcc.target/vax/cmpelim-le-addhi.c: New test.
* gcc.target/vax/cmpelim-le-addqi.c: New test.
* gcc.target/vax/cmpelim-le-addsf.c: New test.
* gcc.target/vax/cmpelim-le-addsi.c: New test.
* gcc.target/vax/cmpelim-le-andhi.c: New test.
* gcc.target/vax/cmpelim-le-andqi.c: New test.
* gcc.target/vax/cmpelim-le-andsi.c: New test.
* gcc.target/vax/cmpelim-le-ashlsi.c: New test.
* gcc.target/vax/cmpelim-le-ashrsi.c: New test.
* gcc.target/vax/cmpelim-le-divdf.c: New test.
* gcc.target/vax/cmpelim-le-divhi.c: New test.
* gcc.target/vax/cmpelim-le-divqi.c: New test.
* gcc.target/vax/cmpelim-le-divsf.c: New test.
* gcc.target/vax/cmpelim-le-divsi.c: New test.
* gcc.target/vax/cmpelim-le-extendhisi.c: New test.
* gcc.target/vax/cmpelim-le-extendqisi.c: New test.
* gcc.target/vax/cmpelim-le-extvsi.c: New test.
* gcc.target/vax/cmpelim-le-extzvsi.c: New test.
* gcc.target/vax/cmpelim-le-fixdfhi.c: New test.
* gcc.target/vax/cmpelim-le-fixdfqi.c: New test.
* gcc.target/vax/cmpelim-le-fixdfsi.c: New test.
* gcc.target/vax/cmpelim-le-fixsfhi.c: New test.
* gcc.target/vax/cmpelim-le-fixsfqi.c: New test.
* gcc.target/vax/cmpelim-le-fixsfsi.c: New test.
* gcc.target/vax/cmpelim-le-floatsisf.c: New test.
* gcc.target/vax/cmpelim-le-insvsi.c: New test.
* gcc.target/vax/cmpelim-le-iorhi.c: New test.
* gcc.target/vax/cmpelim-le-iorqi.c: New test.
* gcc.target/vax/cmpelim-le-iorsi.c: New test.
* gcc.target/vax/cmpelim-le-movdf.c: New test.
* gcc.target/vax/cmpelim-le-movhi.c: New test.
* gcc.target/vax/cmpelim-le-movqi.c: New test.
* gcc.target/vax/cmpelim-le-movsf.c: New test.
* gcc.target/vax/cmpelim-le-movsi.c: New test.
* gcc.target/vax/cmpelim-le-muldf.c: New test.
* gcc.target/vax/cmpelim-le-mulhi.c: New test.
* gcc.target/vax/cmpelim-le-mulqi.c: New test.
* gcc.target/vax/cmpelim-le-mulsf.c: New test.
* gcc.target/vax/cmpelim-le-mulsi.c: New test.
* gcc.target/vax/cmpelim-le-nothi.c: New test.
* gcc.target/vax/cmpelim-le-notqi.c: New test.
* gcc.target/vax/cmpelim-le-notsi.c: New test.
* gcc.target/vax/cmpelim-le-rotlsi.c: New test.
* gcc.target/vax/cmpelim-le-rotrsi.c: New test.
* gcc.target/vax/cmpelim-le-subdf.c: New test.
* gcc.target/vax/cmpelim-le-subhi.c: New test.
* gcc.target/vax/cmpelim-le-subqi.c: New test.
* gcc.target/vax/cmpelim-le-subsf.c: New test.
* gcc.target/vax/cmpelim-le-subsi.c: New test.
* gcc.target/vax/cmpelim-le-truncdfsf.c: New test.
* gcc.target/vax/cmpelim-le-xorhi.c: New test.
* gcc.target/vax/cmpelim-le-xorqi.c: New test.
* gcc.target/vax/cmpelim-le-xorsi.c: New test.
* gcc.target/vax/cmpelim-leu-subhi.c: New test.
* gcc.target/vax/cmpelim-leu-subqi.c: New test.
* gcc.target/vax/cmpelim-leu-subsi.c: New test.
* gcc.target/vax/cmpelim-lt-adddf.c: New test.
* gcc.target/vax/cmpelim-lt-addhi.c: New test.
* gcc.target/vax/cmpelim-lt-addqi.c: New test.
* gcc.target/vax/cmpelim-lt-addsf.c: New test.
* gcc.target/vax/cmpelim-lt-addsi.c: New test.
* gcc.target/vax/cmpelim-lt-andhi.c: New test.
* gcc.target/vax/cmpelim-lt-andqi.c: New test.
* gcc.target/vax/cmpelim-lt-andsi.c: New test.
* gcc.target/vax/cmpelim-lt-ashlsi.c: New test.
* gcc.target/vax/cmpelim-lt-ashrsi.c: New test.
* gcc.target/vax/cmpelim-lt-divdf.c: New test.
* gcc.target/vax/cmpelim-lt-divhi.c: New test.
* gcc.target/vax/cmpelim-lt-divqi.c: New test.
* gcc.target/vax/cmpelim-lt-divsf.c: New test.
* gcc.target/vax/cmpelim-lt-divsi.c: New test.
* gcc.target/vax/cmpelim-lt-extendhisi.c: New test.
* gcc.target/vax/cmpelim-lt-extendqisi.c: New test.
* gcc.target/vax/cmpelim-lt-extvsi.c: New test.
* gcc.target/vax/cmpelim-lt-extzvsi.c: New test.
* gcc.target/vax/cmpelim-lt-fixdfhi.c: New test.
* gcc.target/vax/cmpelim-lt-fixdfqi.c: New test.
* gcc.target/vax/cmpelim-lt-fixdfsi.c: New test.
* gcc.target/vax/cmpelim-lt-fixsfhi.c: New test.
* gcc.target/vax/cmpelim-lt-fixsfqi.c: New test.
* gcc.target/vax/cmpelim-lt-fixsfsi.c: New test.
* gcc.target/vax/cmpelim-lt-floatsisf.c: New test.
* gcc.target/vax/cmpelim-lt-insvsi.c: New test.
* gcc.target/vax/cmpelim-lt-iorhi.c: New test.
* gcc.target/vax/cmpelim-lt-iorqi.c: New test.
* gcc.target/vax/cmpelim-lt-iorsi.c: New test.
* gcc.target/vax/cmpelim-lt-movdf.c: New test.
* gcc.target/vax/cmpelim-lt-movhi.c: New test.
* gcc.target/vax/cmpelim-lt-movqi.c: New test.
* gcc.target/vax/cmpelim-lt-movsf.c: New test.
* gcc.target/vax/cmpelim-lt-movsi.c: New test.
* gcc.target/vax/cmpelim-lt-muldf.c: New test.
* gcc.target/vax/cmpelim-lt-mulhi.c: New test.
* gcc.target/vax/cmpelim-lt-mulqi.c: New test.
* gcc.target/vax/cmpelim-lt-mulsf.c: New test.
* gcc.target/vax/cmpelim-lt-mulsi.c: New test.
* gcc.target/vax/cmpelim-lt-nothi.c: New test.
* gcc.target/vax/cmpelim-lt-notqi.c: New test.
* gcc.target/vax/cmpelim-lt-notsi.c: New test.
* gcc.target/vax/cmpelim-lt-rotlsi.c: New test.
* gcc.target/vax/cmpelim-lt-rotrsi.c: New test.
* gcc.target/vax/cmpelim-lt-subdf.c: New test.
* gcc.target/vax/cmpelim-lt-subhi.c: New test.
* gcc.target/vax/cmpelim-lt-subqi.c: New test.
* gcc.target/vax/cmpelim-lt-subsf.c: New test.
* gcc.target/vax/cmpelim-lt-subsi.c: New test.
* gcc.target/vax/cmpelim-lt-truncdfsf.c: New test.
* gcc.target/vax/cmpelim-lt-xorhi.c: New test.
* gcc.target/vax/cmpelim-lt-xorqi.c: New test.
* gcc.target/vax/cmpelim-lt-xorsi.c: New test.
* gcc.target/vax/cmpelim-ltu-subhi.c: New test.
* gcc.target/vax/cmpelim-ltu-subqi.c: New test.
* gcc.target/vax/cmpelim-ltu-subsi.c: New test.
* gcc.target/vax/cmpelim-xx-addsi.c: New test.
* gcc.target/vax/cmpelim-xx-insvsi.c: New test.
* gcc.target/vax/cmpelim-xxu-subsi.c: New test.
* gcc.target/vax/peephole2-eq-andhi.c: New test.
* gcc.target/vax/peephole2-eq-andqi.c: New test.
* gcc.target/vax/peephole2-eq-andsi.c: New test.
* gcc.target/vax/peephole2-eq-cmpvsi.c: New test.
* gcc.target/vax/peephole2-eq-cmpzvsi.c: New test.
* gcc.target/vax/peephole2-eq-ctzhi-0.c: New test.
* gcc.target/vax/peephole2-eq-ctzhi-1.c: New test.
* gcc.target/vax/peephole2-eq-ctzqi-0.c: New test.
* gcc.target/vax/peephole2-eq-ctzqi-1.c: New test.
* gcc.target/vax/peephole2-eq-ctzsi-0.c: New test.
* gcc.target/vax/peephole2-eq-ctzsi-1.c: New test.
* gcc.target/vax/peephole2-eq-ffshi.c: New test.
* gcc.target/vax/peephole2-eq-ffsqi.c: New test.
* gcc.target/vax/peephole2-eq-ffssi.c: New test.
* gcc.target/vax/peephole2-le-andhi.c: New test.
* gcc.target/vax/peephole2-le-andqi.c: New test.
* gcc.target/vax/peephole2-le-andsi.c: New test.
* gcc.target/vax/peephole2-le-cmpvsi.c: New test.
* gcc.target/vax/peephole2-le-cmpzvsi.c: New test.
* gcc.target/vax/peephole2-leu-cmpvsi.c: New test.
* gcc.target/vax/peephole2-leu-cmpzvsi.c: New test.
* gcc.target/vax/peephole2-lt-andhi.c: New test.
* gcc.target/vax/peephole2-lt-andqi.c: New test.
* gcc.target/vax/peephole2-lt-andsi.c: New test.
* gcc.target/vax/peephole2-lt-cmpvsi.c: New test.
* gcc.target/vax/peephole2-lt-cmpzvsi.c: New test.
* gcc.target/vax/peephole2-ltu-cmpvsi.c: New test.
* gcc.target/vax/peephole2-ltu-cmpzvsi.c: New test.
|
|
In the VAX ISA INSV bit-field insert instruction is the only computational
operation that keeps the condition codes, held in the PSL or Processor
Status Longword register, intact. The instruction is flexible enough it
could potentially be used for data moves post-reload, but then reportedly
it is not the best choice performance-wise, and then we have no addition
operation available that would keep the condition codes unchanged.
Futhermore, as usually with a complex CISC ISA, for many operations we
have several machine instructions or instruction sequences to choose
from that set condition codes in a different manner.
Use the approach then where the condition codes only get introduced by
reload, by definining instruction splitters for RTL insns that change
condition codes in some way, by default considering them clobbered.
Then to prevent code generated from regressing too much provide insns
that include a `compare' operation setting the condition codes in
parallel to the main operation. The manner condition codes are set by
each insn is supposed to be provided by the whatever the SELECT_CC_MODE
macro expands to.
Given that individual patterns provided for the same RTL basic operation
may set the condion codes differently keeping the information away from
the insn patterns themselves would cause a maintenance nightmare and
would be bound to fail in a horrible way sooner or later. Therefore
instead let the patterns themselves choose which condition modes they
support, by having one or more subst iterators applied and then have
individual comparison operators require the specific condition mode each
according to the codes used by the operation.
While subst iterators only support one alternative each, there is
actually no problem with applying multiple ones to a single insn with
the result as intended, and if the corresponding subst attribute
supplies an empty NO-SUBST-VALUE, then no mess results even. Make use
of this observation.
Add appropriate subst iterators to all the computational patterns then,
according to the condition codes they usably set, including DImode ones
and a substitute DImode comparison instruction in the absence of a CMPQ
machine instruction, however do not provide a `cbranchdi4' named pattern
as without a further development it regresses code quality by resorting
to the `__cmpdi2' libcall where a simpler operation would do, e.g. to
check for negativity the TSTL machine instruction may be executed over
the upper longword only. This is good material for further work.
Do not apply subst iterators to the increment- or decrement-and-branch
patterns at this time; these may yet have to be reviewed, in particular
whether `*jsobneq_minus_one' is still relevant in the context of the
recent integer constant cost review.
Also add a couple of peepholes to help eliminating comparisons in some
problematic cases, such as with the BIT instruction which is bitwise-AND
for condition codes only that has no direct counterpart for the actual
calculation, because the BIC instruction which does do bitwise-AND and
produces a result implements the operation with a bitwise negation of
its input `mask' operand. Or the FFS instruction which sets the Z
condition code according to its `field' input operand rather than the
result produced. Or the bit-field comparisons we don't have generic
middle-end support for.
Code size stats are as follows, obtained from 17640 and 9086 executables
built in `check-c' and `check-c++' GCC testing respectively:
check-c check-c++
samples average median samples average median
---------------------------------------------------------------
regressions 1813 0.578% 0.198% 289 0.349% 0.175%
unchanged 15160 0.000% 0.000% 8662 0.000% 0.000%
progressions 667 -0.589% -0.194% 135 -0.944% -0.191%
----------------------------------------------------------------
total 17640 0.037% 0.000% 9086 -0.003% 0.000%
Outliers:
old new change %change filename
----------------------------------------------------
2406 2950 +544 +22.610 20111208-1.exe
4314 5329 +1015 +23.528 pr39417.exe
2235 3055 +820 +36.689 990404-1.exe
2631 4213 +1582 +60.129 pr57521.exe
3063 5579 +2516 +82.142 20000422-1.exe
and:
old new change %change filename
----------------------------------------------------
6317 4845 -1472 -23.302 vector-compare-1.exe
6313 4845 -1468 -23.254 vector-compare-1.exe
6474 5002 -1472 -22.737 vector-compare-1.exe
6470 5002 -1468 -22.689 vector-compare-1.exe
We have some code quality regressions like:
10861: 9e ef d9 12 movab 11b40 <p>,r0
10865: 00 00 50
10868: 90 a0 03 a0 movb 0x3(r0),0x2(r0)
1086c: 02
1086d: d1 60 8f 61 cmpl (r0),$0x64646261
10871: 62 64 64
10874: 13 07 beql 1087d <main_test+0x21>
to:
10861: 9e ef e1 12 movab 11b48 <p>,r0
10865: 00 00 50
10868: 90 a0 03 a0 movb 0x3(r0),0x2(r0)
1086c: 02
1086d: d1 ef d5 12 cmpl 11b48 <p>,$0x64646261
10871: 00 00 8f 61
10875: 62 64 64
10878: 13 07 beql 10881 <main_test+0x25>
(from `memmove-2.x2') due to the constant propagation passes eagerly
replacing pseudo registers with direct symbol references where possible,
which does not happen with CC0 even though the passes do run regardless.
There are further code quality regressions due to earlier compilation
stages trying to push expression evaluation earlier where possible so
as to make data dependencies further apart from each other. This works
well for computations and architectures that do not involve condition
codes set as a side effect of calculations. However for integer
negation that makes assembly code produced like:
movb *8(%ap),%r0
mnegb %r0,%r1
tstb %r0
jeql .L2
the RTL equibvalent of which the comparison elimination pass cannot
really do anything about, because the comparison is made on the source
rather than the target operand of the negation (we could add a peephole
for this, but this seems futile an effort, as one'd have to iterate over
all the possible such cases), even though this is really equivalent to:
movb *8(%ap),%r0
mnegb %r0,%r1
jeql .L2
or, if R0 is dead at the conclusion of the branch, even:
mnegb *8(%ap),%r1
jeql .L2
Since the compiler insists on doing the comparison on the source of the
negation it obviously has to load it into a temporary so as to avoid
accessing the original memory location twice, hence the sequence of
three instructions rather than just a single one. A similar phenomenon
can be observed with the XOR operation and in other cases.
In some cases a comparison does get eliminated, however useless moves
into registers done in preparation to it remain, such as with:
movb *8(%ap),%r2
movb *12(%ap),%r1
subb3 %r1,%r2,%r0
jlssu .L2
where R1 and R2 are both dead at conclusion and therefore:
subb3 *12(%ap),*8(%ap),%r0
jlssu .L2
would obviously do, but there was to be a comparison before the branch:
cmpb %r2,%r1
All this looks like material for future improvement.
Test cases for comparison elimination and the peepholes will be supplied
separately.
gcc/
PR target/95294
* config/vax/elf.h (REGISTER_NAMES): Append `%psl'.
* config/vax/vax-modes.def (CCN, CCNZ, CCZ): New modes.
* config/vax/vax-protos.h (vax_select_cc_mode): New prototype.
(vax_maybe_split_dimode_move): Likewise.
(vax_notice_update_cc): Remove prototype.
* config/vax/vax.c (TARGET_FLAGS_REGNUM): New macro.
(TARGET_CC_MODES_COMPATIBLE): Likewise.
(TARGET_MD_ASM_ADJUST): Likewise.
(vax_select_cc_mode): New function
(vax_cc_modes_compatible): Likewise.
(vax_md_asm_adjust): Likewise.
(vax_notice_update_cc): Remove function.
(vax_output_int_move): Factor out code checking if a DImode move
may have to be split...
(vax_maybe_split_dimode_move): ... into this new function.
* config/vax/vax.h (FIRST_PSEUDO_REGISTER): Bump up.
(FIXED_REGISTERS): Append an entry for PSL.
(CALL_USED_REGISTERS): Likewise.
(NOTICE_UPDATE_CC, OUTPUT_JUMP): Remove macros.
(SELECT_CC_MODE): New macro.
(REGISTER_NAMES): Append `psl'.
* config/vax/predicates.md (const_zero_operand)
(vax_cc_comparison_operator, vax_ccn_comparison_operator)
(vax_ccnz_comparison_operator, vax_ccz_comparison_operator):
New predicates.
* config/vax/builtins.md: Rewrite for MODE_CC representation.
* config/vax/vax.md: Likewise.
|
|
Fix a testsuite failure:
/tmp/ccL65Mmt.s: Assembler messages:
/tmp/ccL65Mmt.s:36: Warning: Symbol n used as immediate operand in PIC mode.
FAIL: gcc.dg/lto/pr55660 c_lto_pr55660_0.o-c_lto_pr55660_1.o link, -O0 -flto -flto-partition=none -fuse-linker-plugin
where non-PIC code is substituted by the LTO compiler at the link stage
for what used to be PIC code in the original compilation. This happens
because in the de-facto VAX ELF psABI we rely on code being PIC for GOT
support in dynamic executables and arrange that by having `-fPIC' passed
to the compiler by default by means of a specs recipe.
That is however canceled where the LTO wrapper is used, by an internal
arrangement in the LTO compiler that clears the PIC flag whenever the
`-flinker-output=exec' option has been used. This has been deliberately
introduced with commit 1ff9ed6fb282 ("re PR lto/67548 (LTO drops weak
binding with "ld -r")")[1]:
"In the log of PR67548 HJ actually pointed out that we do have API at
linker plugin side which says what type of output is done. This is cool
because we can also use it to drop -fpic when building static binary.
This is common in Firefox, where some objects are built with -fpic and
linked to both binaries and libraries."
with this code:
case LTO_LINKER_OUTPUT_EXEC: /* Normal executable */
flag_pic = 0;
flag_pie = 0;
flag_shlib = 0;
break;
Consequently code like:
.L6:
addl3 -8(%fp),$n,%r0
pushl %r0
calls $1,foo
addl2 %r0,-12(%fp)
incl -8(%fp)
.L5:
is produced by the LTO compiler, where a reference to `n' is used that
is invalid in PIC code, because it uses the immediate addressing mode,
denoted by the `$' prefix.
For that not to happen we must never pass `-flinker-output=exec' to the
LTO compiler unless non-PIC code has been explicitly requested. Using
`-flinker-output=dyn' except for relocatable output would seem the
simplest approach, as it does not fiddle with any of the internal code
model settings beyond what the command-line options have arranged and
therefore lets them remain the same as with the original compilation,
but it breaks as well causing PR lto/69866 to retrigger, as that code
seems sensitive to `flag_shlib':
lto1: internal compiler error: in add_symbol_to_partition_1, at lto/lto-partition.c:152
0x105be1cb add_symbol_to_partition_1
.../gcc/lto/lto-partition.c:152
0x105be443 add_symbol_to_partition_1
.../gcc/lto/lto-partition.c:194
0x105be80f add_symbol_to_partition
.../gcc/lto/lto-partition.c:270
0x105bee6f add_sorted_nodes
.../gcc/lto/lto-partition.c:395
0x105c0903 lto_balanced_map(int, int)
.../gcc/lto/lto-partition.c:815
0x105aa91f do_whole_program_analysis
.../gcc/lto/lto.c:499
0x105aac97 lto_main()
.../gcc/lto/lto.c:637
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
lto-wrapper: fatal error: .../gcc/xgcc returned 1 exit status
compilation terminated.
.../usr/bin/vax-netbsdelf-ld: error: lto-wrapper failed
collect2: error: ld returned 1 exit status
compiler exited with status 1
FAIL: gcc.dg/lto/pr69866 c_lto_pr69866_0.o-c_lto_pr69866_1.o link, -O0 -flto -fuse-linker-plugin -fno-fat-lto-objects (internal compiler error)
Substitute `-flinker-output=pie' for `-flinker-output=exec' in the specs
then unless `-no-pie' has also been used, preserving the original intent
of emitting PIC code by default for executables while keeping the linker
arrangement unchanged. The LTO compiler uses the `cc1' spec, so keep
`cc1plus' unmodified.
This makes code like:
.L6:
movab n,%r0
addl2 -8(%fp),%r0
pushl %r0
calls $1,foo
addl2 %r0,-12(%fp)
incl -8(%fp)
.L5:
be produced instead corresponding to the fragment quoted above, which is
valid PIC code as it uses the PC-relative addressing mode denoted by the
absence of a prefix to `n' (which can be redirected to GOT as required,
by changing the addressing mode to PC-relative indirect in the operand
specifier).
Ideally we would instead default to the PIE model for executables, but
that triggers a BFD bug where for a change the LTO wrapper is not used:
.../usr/bin/vax-netbsdelf-ld: /tmp/ccV2sWQt.ltrans0.ltrans.o: warning: GOT addend of 3 to `n' does not match previous GOT addend of 0
FAIL: gcc.dg/lto/pr55660 c_lto_pr55660_0.o-c_lto_pr55660_1.o link, -O2 -flto -flto-partition=1to1 -fno-use-linker-plugin
which is due to assembly code like:
main:
.word 0
subl2 $4,%sp
movab n,%r0
movab n+3,%r2
clrl %r3
movb $98,%r1
.L4:
and consequently object code like:
00000000 <main>:
0: 00 00 .word 0x0000 # Entry mask: < >
2: c2 04 5e subl2 $0x4,sp
5: 9e ef 00 00 movab b <main+0xb>,r0
9: 00 00 50
7: R_VAX_GOT32 n
c: 9e ef 00 00 movab 12 <main+0x12>,r2
10: 00 00 52
e: R_VAX_GOT32 n+0x3
13: d4 53 clrf r3
15: 90 8f 62 51 movb $0x62,r1
being produced. This would be problematic for external `n', because we
do not support multiple GOT entries for the same symbol referred to with
different offsets in a single link unit. In this case however the LTO
compiler correctly observes that `n' is defined by the executable and
not preemptible and therefore no GOT entry will be made for it.
Indeed a valid executable is produced:
00010548 <main>:
10548: 00 00 .word 0x0000 # Entry mask: < >
1054a: c2 04 5e subl2 $0x4,sp
1054d: 9e ef dd 14 movab 11a30 <n>,r0
10551: 00 00 50
10554: 9e ef d9 14 movab 11a33 <__bss_start>,r2
10558: 00 00 52
1055b: d4 53 clrf r3
1055d: 90 8f 62 51 movb $0x62,r1
despite the warning, but it would be rather bad to have users annoyed
with this message from BFD, however harmless, especially as it triggers
outside LTO compilations as well.
Therefore this change is the best we can do until binutils have been
fixed.
References:
[1] Jan Hubicka, "Getting LTO incremental linking work",
<https://gcc.gnu.org/ml/gcc-patches/2015-11/msg02986.html>
gcc/
* config/vax/elf.h (VAX_CC1_SPEC, VAX_CC1PLUS_SPEC): New macros.
* config/vax/netbsd-elf.h (CC1_SPEC): Use VAX_CC1_SPEC rather
than VAX_CC1_AND_CC1PLUS_SPEC.
(CC1PLUS_SPEC): Use VAX_CC1PLUS_SPEC rather than
VAX_CC1_AND_CC1PLUS_SPEC.
|
|
We do not define a comparison operation between floating-point and
integer data, including integer zero constant. Consequently the RTL
instruction stream presented to the post-reload comparison elimination
pass will include, where applicable, floating-point comparison insns
against `const_double:DF 0.0 [0x0.0p+0]' rather than `const_int 0 [0]',
meaning that the latter expression will not match when used in machine
description.
Use `const_double_zero' then for the relevant patterns to match the
intended RTL instructions.
gcc/
* config/pdp11/pdp11.md (fcc_cc, fcc_ccnz): Use
`const_double_zero' to express double zero constant.
|
|
The use of a constant double zero is required for post-reload compare
elimination to be able to discard redundant floating-point comparisons,
for example with a VAX RTL instruction stream like:
(insn 34 4 3 2 (parallel [
(set (reg/v:DF 0 %r0 [orig:24 x ] [24])
(mem/c:DF (plus:SI (reg/f:SI 12 %ap)
(const_int 4 [0x4])) [1 x+0 S8 A32]))
(clobber (reg:CC 16 %psl))
]) ".../gcc/testsuite/gcc.target/vax/cmpelim-eq-movdf.c":9:1 37 {*movdf}
(nil))
(note 3 34 35 2 NOTE_INSN_FUNCTION_BEG)
(insn 35 3 36 2 (set (reg:CCZ 16 %psl)
(compare:CCZ (reg/v:DF 0 %r0 [orig:24 x ] [24])
(const_double:DF 0.0 [0x0.0p+0]))) ".../gcc/testsuite/gcc.target/vax/cmpelim-eq-movdf.c":10:6 21 {*cmpdf_ccz}
(nil))
(jump_insn 36 35 9 2 (set (pc)
(if_then_else (eq (reg:CCZ 16 %psl)
(const_int 0 [0]))
(label_ref 11)
(pc))) ".../gcc/testsuite/gcc.target/vax/cmpelim-eq-movdf.c":10:6 537 {*branch_ccz}
(int_list:REG_BR_PROB 536870916 (nil))
-> 11)
that we want to transform into:
(insn 34 4 3 2 (parallel [
(set (reg:CCZ 16 %psl)
(compare:CCZ (mem/c:DF (plus:SI (reg/f:SI 12 %ap)
(const_int 4 [0x4])) [1 x+0 S8 A32])
(const_double:DF 0.0 [0x0.0p+0])))
(set (reg/v:DF 0 %r0 [orig:24 x ] [24])
(mem/c:DF (plus:SI (reg/f:SI 12 %ap)
(const_int 4 [0x4])) [1 x+0 S8 A32]))
]) ".../gcc/testsuite/gcc.target/vax/cmpelim-eq-movdf.c":9:1 40 {*movdf_ccz}
(nil))
(note 3 34 36 2 NOTE_INSN_FUNCTION_BEG)
(jump_insn 36 3 9 2 (set (pc)
(if_then_else (eq (reg:CCZ 16 %psl)
(const_int 0 [0]))
(label_ref 11)
(pc))) ".../gcc/testsuite/gcc.target/vax/cmpelim-eq-movdf.c":10:6 537 {*branch_ccz}
(int_list:REG_BR_PROB 536870916 (nil))
-> 11)
with the upcoming MODE_CC representation.
For this we need to express the `const_double:DF 0.0 [0x0.0p+0]' rtx as
recorded above in the relevant pattern(s) in machine description. The
way we represent double constants, as a host-dependent number of wide
integers, however means that we currently have no portable way to encode
a double zero constant in machine description.
Define a syntactic rtx alias then to represent `(const_double 0 0 ...)'
as if the suitable number of zeros have been supplied according to the
host-specific definition of CONST_DOUBLE_FORMAT.
gcc/
* read-rtl.c (rtx_reader::read_rtx_code): Handle syntactic
`const_double_zero' rtx.
* doc/rtl.texi (Constant Expression Types): Document it.
|
|
Use a double colon to introduce the comments like elsewhere throughout
the VAX machine description.
gcc/
* config/vax/vax.md (divmoddisi4, *amulsi4): Make the comment
notation consistent with the rest of the file.
|
|
Correct issues with commented-out insns, which fail to build if enabled:
.../gcc/config/vax/vax.md:503:1: repeated operand number 1
.../gcc/config/vax/vax.md:503:1: repeated operand number 2
and then when the issue with the repeated operands has been corrected:
.../gcc/config/vax/vax.md:107:1: destination operand 0 allows non-lvalue
.../gcc/config/vax/vax.md:503:1: destination operand 0 allows non-lvalue
.../gcc/config/vax/vax.md:503:1: destination operand 3 allows non-lvalue
.../gcc/config/vax/vax.md:744:1: destination operand 0 allows non-lvalue
Fix the RTL with the repeated operands and change the relevant output
operand predicates not to allow immediates.
Also emit MOVO rather than MOVH assembly instruction with the `movti'
insn so that the condition codes are set according to the integer rather
than floating-point interpretation of the datum moved, as expected with
the operation associated with the pattern.
Finally give `*amulsi4' a name, for easier reference here and elsewhere.
We may eventually want to have some of these insns enabled at `-Os'.
gcc/
* config/vax/vax.md (movti): Fix output predicate. Emit `movo'
rather than `movh'.
(divmoddisi4): Fix output predicates, correct RTL.
(*amulsi4): Name insn. Fix output predicate.
|
|
It makes no sense for insn operand predicates, as long as they accept a
register operand, to be more restrictive than the set of the associated
constraints, because expand will choose the insn based on the relevant
operand being a pseudo register then and reload will keep it happily as
an immediate if a constraint permits it. So the restriction posed by
such a predicate will be happily ignored, and moreover if a splitter is
added, such as required for MODE_CC support, the new instructions will
reject the original operands supplied, causing an ICE like below:
.../gcc/testsuite/gfortran.dg/graphite/PR67518.f90:44:0: Error: could not split insn
(insn 90 662 663 (set (reg:DI 10 %r10 [orig:97 _235 ] [97])
(mult:DI (sign_extend:DI (mem/c:SI (plus:SI (reg/f:SI 13 %fp)
(const_int -800 [0xfffffffffffffce0])) [14 %sfp+-800 S4 A32]))
(sign_extend:DI (const_int -51 [0xffffffffffffffcd])))) 299 {mulsidi3}
(expr_list:REG_EQUAL (mult:DI (sign_extend:DI (subreg:SI (mem/c:DI (plus:SI (reg/f:SI 13 %fp)
(const_int -800 [0xfffffffffffffce0])) [14 %sfp+-800 S8 A32]) 0))
(const_int -51 [0xffffffffffffffcd]))
(nil)))
during RTL pass: final
.../gcc/testsuite/gfortran.dg/graphite/PR67518.f90:44:0: internal compiler error: in final_scan_insn_1, at final.c:3073
Please submit a full bug report,
with preprocessed source if appropriate.
See <https://gcc.gnu.org/bugs/> for instructions.
Change the predicates used with the widening multiply and multiply-add
insns to allow immediates then, just as the constraints and the machine
instructions produced permit.
Also give the insns names, for easier reference here and elsewhere.
gcc/
* config/vax/vax.md (mulsidi3): Fix the multiplicand predicates.
(*maddsidi4, *maddsidi4_const): Likewise. Name insns.
|
|
It makes no sense for insn operand predicates, as long as they accept a
register operand, to be more restrictive than the set of the associated
constraints, because expand will choose the insn based on the relevant
operand being a pseudo register then and reload keep it happily as a
memory reference if a constraint permits it. So the restriction posed
by such a predicate will be happily ignored, and moreover if a splitter
is added, such as required for MODE_CC support, the new instructions
will reject the original operands supplied, causing an ICE. An actual
example will be given with a subsequent change.
Therefore, similarly to EXTV/EXTZV/INSV insns, remove inconsistencies
with predicates and constraints of bit-field comparison insns, observing
that a bit-field located in memory is byte-addressed by the respective
machine instructions and therefore SImode may only be used with a
register or an offsettable memory operand (i.e. not an indexed,
pre-decremented, or post-incremented one).
Also give the insns names, for easier reference here and elsewhere.
gcc/
* config/vax/vax.md (*cmpv_2): Name insn.
(*cmpv, *cmpzv, *cmpzv_2): Likewise. Fix location predicate and
constraint.
|
|
We have matching insns defined for `sign_extract' and `zero_extract'
expressions, so make the three named patterns for bit-field operations
consistent and make `extv' an expander rather than an insn taking a
SImode, a QImode, and a SImode general operand for the LOC, SIZE, and
POS operands respectively, like with the `extzv' and `insv' patterns,
matching the machine instructions and giving the middle end more choice
as to which actual insn to choose in a given situation.
Given this program:
typedef struct
{
int f0:1;
int f1:7;
int f8:8;
int f16:16;
} bit_t;
typedef struct
{
unsigned int f0:1;
unsigned int f1:7;
unsigned int f8:8;
unsigned int f16:16;
} ubit_t;
typedef union
{
bit_t b;
int i;
} bit_u;
typedef union
{
ubit_t b;
unsigned int i;
} ubit_u;
int
ins1 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f1 = y;
return x.i;
}
int
ext1 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f1;
}
unsigned int
extz1 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f1;
}
int
ins8 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f8 = y;
return x.i;
}
int
ext8 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f8;
}
unsigned int
extz8 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f8;
}
int
ins16 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f16 = y;
return x.i;
}
int
ext16 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f16;
}
unsigned int
extz16 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f16;
}
this results in the following code change:
@@ -16,12 +16,12 @@ ins1:
.globl ext1
.type ext1, @function
ext1:
- .word 0 # 19 [c=0] procedure_entry_mask
- subl2 $4,%sp # 20 [c=32] addsi3
+ .word 0 # 18 [c=0] procedure_entry_mask
+ subl2 $4,%sp # 19 [c=32] addsi3
movl 4(%ap),%r0 # 2 [c=16] movsi_2
- cvtbl %r0,%r0 # 7 [c=4] extendqisi2
- ashl $-1,%r0,%r0 # 14 [c=40] *vax.md:624
- ret # 24 [c=0] return
+ extv $1,$7,%r0,%r0 # 7 [c=60] *extv_non_const
+ cvtbl %r0,%r0 # 13 [c=4] extendqisi2
+ ret # 23 [c=0] return
.size ext1, .-ext1
.align 1
.globl extz1
@@ -49,12 +49,12 @@ ins8:
.globl ext8
.type ext8, @function
ext8:
- .word 0 # 20 [c=0] procedure_entry_mask
- subl2 $4,%sp # 21 [c=32] addsi3
+ .word 0 # 18 [c=0] procedure_entry_mask
+ subl2 $4,%sp # 19 [c=32] addsi3
movl 4(%ap),%r0 # 2 [c=16] movsi_2
- cvtwl %r0,%r0 # 7 [c=4] extendhisi2
- ashl $-8,%r0,%r0 # 15 [c=40] *vax.md:624
- ret # 25 [c=0] return
+ rotl $24,%r0,%r0 # 13 [c=60] *extv_non_const
+ cvtbl %r0,%r0
+ ret # 23 [c=0] return
.size ext8, .-ext8
.align 1
.globl extz8
If there is a performance degradation with the replacement sequences,
then it can and should be sorted within `extv_non_const'.
gcc/
* config/vax/vax.md (extv): Rename insn to...
(*extv): ... this.
(extv): New expander.
|
|
With the `*insv_aligned', `*extzv_aligned' and `*extv_aligned' insns we
are going to adjust the bit-field location if it is in memory, so only
allow such location addresses that can be offset, excluding external
symbol references in the PIC mode in particular.
This fixes an ICE like:
during RTL pass: final
In file included from .../gcc/testsuite/gcc.dg/torture/vshuf-v16qi.c:11:
.../gcc/testsuite/gcc.dg/torture/vshuf-main.inc: In function 'test_13':
.../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:27:1: internal compiler error: in change_address_1, at emit-rtl.c:2275
.../gcc/testsuite/gcc.dg/torture/vshuf-16.inc:16:1: note: in expansion of macro 'T'
.../gcc/testsuite/gcc.dg/torture/vshuf-main.inc:28:1: note: in expansion of macro 'TESTS'
0x10a34b33 change_address_1
.../gcc/emit-rtl.c:2275
0x10a358af adjust_address_1(rtx_def*, machine_mode, poly_int<1u, long>, int, int, int, poly_int<1u, long>)
.../gcc/emit-rtl.c:2409
0x11d2505f output_97
.../gcc/config/vax/vax.md:806
0x10adec4b get_insn_template(int, rtx_insn*)
.../gcc/final.c:2070
0x10ae1c5b final_scan_insn_1
.../gcc/final.c:3039
0x10ae2257 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
.../gcc/final.c:3152
0x10ade9a3 final_1
.../gcc/final.c:2020
0x10ae6157 rest_of_handle_final
.../gcc/final.c:4658
0x10ae6697 execute
.../gcc/final.c:4736
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
compiler exited with status 1
FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error)
triggered by an RTL instruction like:
(insn 97 96 98 (set (reg:SI 5 %r5 [88])
(zero_extract:SI (mem/c:SI (symbol_ref:SI ("b") <var_decl 0x7ffff7f801b0 b>) [0 b+0 S4 A128])
(const_int 8 [0x8])
(const_int 24 [0x18]))) ".../gcc/testsuite/gcc.dg/torture/vshuf-main.inc":28:1 97 {*extzv_aligned}
(nil))
and removes these regressions:
FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (internal compiler error)
FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 (test for excess errors)
FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (internal compiler error)
FAIL: gcc.dg/torture/vshuf-v4hi.c -O2 (test for excess errors)
FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (internal compiler error)
FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 (test for excess errors)
FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (internal compiler error)
FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 (test for excess errors)
However expand typically presents pseudo-registers rather than memory
references to these insns, so a further rework is required to make a
better use of the code variant they are supposed to produce. This at
least fixes the problem at hand.
gcc/
* config/vax/vax.md (*insv_aligned, *extzv_aligned)
(*extv_aligned): Also make sure the memory address of a bit-field
location can be adjusted in the PIC mode.
|
|
The INSV machine instruction is the only computational operation in the
VAX ISA that keeps condition codes intact. In preparation to MODE_CC
transition keep patterns apart then that make or do not make use of said
instruction. For consistency update EXTV and EXTZV instruction uses
accordingly. In expand SUBREGs will be presented as operands, so handle
that possibility in the insn condition.
This actually yields better code by avoiding EXTV/EXTZV instructions in
pseudo-aligned register cases previously resorting to those instructions:
@@ -42,7 +42,7 @@ ins8:
subl2 $4,%sp # 21 [c=32] addsi3
movl 4(%ap),%r0 # 2 [c=16] movsi_2
movl 8(%ap),%r1 # 17 [c=16] movsi_2
- insv %r1,$8,$8,%r0 # 9 [c=4] *insv_aligned
+ insv %r1,$8,$8,%r0 # 9 [c=4] *insv_2
ret # 25 [c=0] return
.size ins8, .-ins8
.align 1
@@ -60,12 +60,12 @@ ext8:
.globl extz8
.type extz8, @function
extz8:
- .word 0 # 19 [c=0] procedure_entry_mask
- subl2 $4,%sp # 20 [c=32] addsi3
+ .word 0 # 18 [c=0] procedure_entry_mask
+ subl2 $4,%sp # 19 [c=32] addsi3
movl 4(%ap),%r0 # 2 [c=16] movsi_2
- extzv $8,$8,%r0,%r1 # 13 [c=60] *extzv_aligned
- movl %r1,%r0 # 18 [c=4] movsi_2
- ret # 24 [c=0] return
+ rotl $24,%r0,%r0 # 13 [c=60] *extzv_non_const
+ movzbl %r0,%r0
+ ret # 23 [c=0] return
.size extz8, .-extz8
.align 1
.globl ins16
@@ -75,7 +75,7 @@ ins16:
subl2 $4,%sp # 21 [c=32] addsi3
movl 4(%ap),%r0 # 2 [c=16] movsi_2
movl 8(%ap),%r1 # 17 [c=16] movsi_2
- insv %r1,$16,$16,%r0 # 9 [c=4] *insv_aligned
+ insv %r1,$16,$16,%r0 # 9 [c=4] *insv_2
ret # 25 [c=0] return
.size ins16, .-ins16
.align 1
@@ -94,8 +94,9 @@ ext16:
extz16:
.word 0 # 18 [c=0] procedure_entry_mask
subl2 $4,%sp # 19 [c=32] addsi3
- movl 4(%ap),%r1 # 2 [c=16] movsi_2
- extzv $16,$16,%r1,%r0 # 7 [c=60] *extzv_aligned
+ movl 4(%ap),%r0 # 2 [c=16] movsi_2
+ rotl $16,%r0,%r0 # 7 [c=60] *extzv_non_const
+ movzwl %r0,%r0
movzwl %r0,%r0 # 13 [c=4] zero_extendhisi2
ret # 23 [c=0] return
.size extz16, .-extz16
demonstrated with this program:
typedef struct
{
int f0:1;
int f1:7;
int f8:8;
int f16:16;
} bit_t;
typedef struct
{
unsigned int f0:1;
unsigned int f1:7;
unsigned int f8:8;
unsigned int f16:16;
} ubit_t;
typedef union
{
bit_t b;
int i;
} bit_u;
typedef union
{
ubit_t b;
unsigned int i;
} ubit_u;
int
ins1 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f1 = y;
return x.i;
}
int
ext1 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f1;
}
unsigned int
extz1 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f1;
}
int
ins8 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f8 = y;
return x.i;
}
int
ext8 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f8;
}
unsigned int
extz8 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f8;
}
int
ins16 (bit_u x, int y)
{
asm volatile ("" : "+r" (x), "+r" (y));
x.b.f16 = y;
return x.i;
}
int
ext16 (bit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f16;
}
unsigned int
extz16 (ubit_u x)
{
asm volatile ("" : "+r" (x));
return x.b.f16;
}
It also papers over a regression:
FAIL: gcc.dg/pr83623.c (internal compiler error)
FAIL: gcc.dg/pr83623.c (test for excess errors)
from an ICE like:
during RTL pass: final
.../gcc/testsuite/gcc.dg/pr83623.c: In function 'foo':
.../gcc/testsuite/gcc.dg/pr83623.c:13:1: internal compiler error: in change_address_1, at emit-rtl.c:2275
0x10a056e3 change_address_1
.../gcc/emit-rtl.c:2275
0x10a0645f adjust_address_1(rtx_def*, machine_mode, poly_int<1u, long>, int, int, int, poly_int<1u, long>)
.../gcc/emit-rtl.c:2409
0x11cb588f output_97
.../gcc/config/vax/vax.md:808
0x10aafb2f get_insn_template(int, rtx_insn*)
.../gcc/final.c:2070
0x10ab2b3f final_scan_insn_1
.../gcc/final.c:3039
0x10ab313b final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
.../gcc/final.c:3152
0x10aaf887 final_1
.../gcc/final.c:2020
0x10ab703b rest_of_handle_final
.../gcc/final.c:4658
0x10ab757b execute
.../gcc/final.c:4736
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
compiler exited with status 1
FAIL: gcc.dg/pr83623.c (internal compiler error)
triggered by an RTL instruction like:
(insn 17 14 145 (set (reg:SI 1 %r1)
(zero_extract:SI (mem/c:SI (symbol_ref:SI ("x") <var_decl 0x7ffff7f80120 x>) [1 x+0 S4 A128])
(const_int 16 [0x10])
(const_int 16 [0x10]))) ".../gcc/testsuite/gcc.dg/pr83623.c":12:9 97 {*extzv_aligned}
(nil))
(where the address cannot be adjusted by 2 for PIC code as requested
here as it would create an offset external symbol reference) otherwise
caused by the patterns modified here, addressed next. This indicates
a further rework is warranted here, but at least problems at hand have
been fixed.
gcc/
* config/vax/vax.md (*insv_aligned, *extzv_aligned)
(*extv_aligned): Reject register bit-field locations that are not
aligned to the least significant bit; update output statement
accordingly.
|
|
It makes no sense for insn operand predicates, as long as they accept a
register operand, to be more restrictive than the set of the associated
constraints, because expand will choose the insn based on the relevant
operand being a pseudo register then and reload keep it happily as a
memory reference if a constraint permits it. So the restriction posed
by such a predicate will be happily ignored, and moreover if a splitter
is added, such as required for MODE_CC support, the new instructions
will reject the original operands supplied, causing an ICE. An actual
example will be given with a subsequent change.
Remove such inconsistencies we have with the EXTV/EXTZV/INSV insns then,
observing that a bit-field located in memory is byte-addressed by the
respective machine instructions and therefore SImode may only be used
with a register or an offsettable memory operand (i.e. not an indexed,
pre-decremented, or post-incremented one), which has already been taken
into account with the constraints currently used, except for `*insv_2'.
The QI machine mode may be used for the bit-field location with any kind
of memory operand, but we got the constraint wrong, although harmlessly
in reality, with `*insv'. Fix that for consistency though.
Also give the insns names, for easier reference here and elsewhere.
gcc/
* config/vax/vax.md (*insv_aligned, *extzv_aligned)
(*extv_aligned, *extv_non_const, *extzv_non_const): Name insns.
Fix location predicate.
(*extzv): Name insn.
(*insv): Likewise. Fix location constraint.
(*insv_2): Likewise, and the predicate.
|
|
The MOVC3 machine instruction has `memmove' semantics[1]:
"The operation of the instruction is such that overlap of the source and
destination strings does not affect the result."
so use it to provide the `movmemhi' instruction as well.
References:
[1] DEC STD 032-0 "VAX Architecture Standard", Digital Equipment
Corporation, A-DS-EL-00032-00-0 Rev J, December 15, 1989, Section
3.10 "Character-String Instructions", p. 3-162
gcc/
* config/vax/vax.md (cpymemhi1): Rename insn to...
(movmemhi1): ... this.
(cpymemhi): Update accordingly. Remove constraints.
(movmemhi): New expander.
gcc/testsuite/
* gcc.target/vax/movmem.c: New test.
|
|
gcc/testsuite/
* gcc.target/vax/cpymem.c: New test.
|
|
The middle end does not refer to `ctzqi2'/`ctzhi2' or `ffsqi2'/`ffshi2'
patterns by name where `__builtin_ctz' or `__builtin_ffs' respectively
is invoked for an argument of the QImode or HImode type, and instead it
extends the data type before passing it to `ctzsi2' or `ffssi2'.
Avoid the redundant operation and use a peephole2 to convert it to the
right RTL expression that will collapse the two operations into a single
machine instruction instead unless we need the extended intermediate
result for another purpose.
gcc/
* config/vax/builtins.md: Add a peephole2 for QImode and HImode
`ctz' operations.
(any_extend): New code iterator.
gcc/testsuite/
* gcc.target/vax/ctzhi.c: New test.
* gcc.target/vax/ctzqi.c: New test.
* gcc.target/vax/ffshi.c: New test.
* gcc.target/vax/ffsqi.c: New test.
|
|
The FFS machine instruction provides for arbitrary input bit-field widths
so take advantage of this and convert `ffssi2' and `ctzsi2' to templates
for all the three of QI, HI, SI machine modes.
Test cases will be added separately.
gcc/
* config/vax/builtins.md (width): New mode attribute.
(ffssi2): Rework expander into...
(ffs<mode>2): ... this.
(ctzsi2): Rework insn into...
(ctz<mode>2): ... this.
|
|
Our `ffssi2_internal' pattern and the machine FFS instruction, which
technically is a bit-field operation, match the `ctz' operation exactly,
with the result produced for the bit-field source operand of zero equal
to its width as specified with another machine instruction operand, not
directly expressed in RTL and currently hardcoded in the assembly code
produced. In our terms this is the bit size of the machine mode used,
and although it's SImode now let's be flexible for an upcoming change.
The operation also sets the Z condition code according to the value of
the source operand.
gcc/
* config/vax/builtins.md (ffssi2_internal): Rename insn to...
(ctzsi2): ... this. Update the RTL operation.
(ffssi2): Update accordingly.
* config/vax/vax.c (vax_notice_update_cc): Handle CTZ.
* config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.
gcc/testsuite/
* gcc.target/vax/ctzsi.c: New test.
|
|
Based on gcc.dg/pr61756.c.
gcc/testsuite/
* gcc.target/vax/bbcci.c: New test.
* gcc.target/vax/bbssi.c: New test.
|
|
gcc/testsuite/
* gcc.target/vax/ffssi.c: New test.
|
|
Test cases will follow.
gcc/
* config/vax/vax.md: Include `builtins.md'.
|
|
Remove an ICE like:
during RTL pass: expand
.../libatomic/tas_n.c: In function 'libat_test_and_set_1':
.../libatomic/tas_n.c:39:1: internal compiler error: in patch_jump_insn, at cfgrtl.c:1298
39 | }
| ^
0x108a09ff patch_jump_insn
.../gcc/cfgrtl.c:1298
0x108a0b07 redirect_branch_edge
.../gcc/cfgrtl.c:1325
0x108a124b rtl_redirect_edge_and_branch
.../gcc/cfgrtl.c:1458
0x1087f6d3 redirect_edge_and_branch(edge_def*, basic_block_def*)
.../gcc/cfghooks.c:373
0x11d6264b try_forward_edges
.../gcc/cfgcleanup.c:562
0x11d6b0eb try_optimize_cfg
.../gcc/cfgcleanup.c:2960
0x11d6ba4f cleanup_cfg(int)
.../gcc/cfgcleanup.c:3174
0x10870b3f execute
.../gcc/cfgexpand.c:6763
triggered with an RTL pattern like:
(jump_insn 8 7 20 2 (parallel [
(set (pc)
(if_then_else (ne (zero_extract:SI (mem/v:QI (mem/f/c:SI (reg/f:SI 16 virtual-incoming-args) [1 mptr+0 S4 A32]) [-1 S1 A8])
(const_int 1 [0x1])
(const_int 0 [0]))
(const_int 0 [0]))
(label_ref 10)
(pc)))
(set (zero_extract:SI (mem/v:QI (mem/f/c:SI (reg/f:SI 16 virtual-incoming-args) [1 mptr+0 S4 A32]) [-1 S1 A8])
(const_int 1 [0x1])
(const_int 0 [0]))
(const_int 1 [0x1]))
]) ".../libatomic/tas_n.c":38:12 -1
(nil)
-> 10)
caused by a volatile memory reference used that is not accepted by the
`memory_operand' predicate of the `jbbssiqi' insn explicitly referred
from the `sync_lock_test_and_setqi' expander. Also seen with:
FAIL: gcc.dg/pr61756.c (internal compiler error)
Define a new `any_memory_operand' predicate accepting both ordinary and
volatile memory references and use it with the `jbb<ccss>i<mode>' insn,
so as to address the ICE.
Also remove useless operations from the `sync_lock_test_and_set<mode>'
and `sync_lock_release<mode>' expanders as those always either complete
or fail and therefore never fall through to using their template other
than to match operands. Wrap `jbb<ccss>i<mode>' into `unspec_volatile'
instead so that the jump does not get removed or reordered. Share one
index to avoid a complication around the iterators since the index is
nowhere referred to anyway and the pattern required pulled by its name.
Test cases will be added separately.
gcc/
* config/vax/predicates.md (volatile_mem_operand)
(any_memory_operand): New predicates.
* config/vax/builtins.md (VUNSPEC_UNLOCK): Remove constant.
(sync_lock_test_and_set<mode>): Remove `set' and `unspec'
operations, match operands only. Reformat.
(sync_lock_release<mode>): Likewise. Remove cruft.
(jbb<ccss>i<mode>): Wrap into `unspec_volatile', use
`any_memory_operand' predicate.
|
|
With mode-specific interlocked branch insns already folded into iterated
templates now fold the two templates into one too, observing that the
only difference between them is the value of the bit branched on, which
is of course reflected both in the RTL expression and the instruction
produced. Use an int iterator to iterate over the bit value, making use
of the newly-added wide integer support, and substituting patterns as
necessary to produce equivalent individual insns. No functional change.
gcc/
* config/vax/builtins.md (bit): New int iterator.
(ccss): New int attribute.
(jbbssi<mode>, jbbcci<mode>): Fold insns into...
(jbb<ccss>i<mode>): ... this.
|
|
Regardless of the machine mode all the interlocked branches of the same
kind, one of the two provided by the ISA, use the same RTL patterns and
machine instructions, except for the memory operand's constraint.
Remove code duplication then and make use of a mode iterator combined
with an attribute to expand the same insn patterns with the constraint
suitably substituted from a single template. No functional change.
gcc/
* config/vax/builtins.md (bb_mem): New mode attribute.
(jbbssiqi, jbbssihi, jbbssisi): Fold insns into...
(jbbssi<mode>): ... this.
(jbbcciqi, jbbccihi, jbbccisi): Likewise...
(jbbcci<mode>): ... this.
|
