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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:25 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:25 +0000 |
| commit | 273ffa3a6fef82738dd86522374fae69ab0e2651 (patch) | |
| tree | 34272370d708f9e9e9f66af1f22087f281935e15 /gcc | |
| parent | a17ab4b6add6a7b7cedbef39af442ca99f7cb3f8 (diff) | |
| download | gcc-273ffa3a6fef82738dd86522374fae69ab0e2651.zip gcc-273ffa3a6fef82738dd86522374fae69ab0e2651.tar.gz gcc-273ffa3a6fef82738dd86522374fae69ab0e2651.tar.bz2 | |
VAX: Also provide QImode and HImode `ctz' and `ffs' operations
The FFS machine instruction provides for arbitrary input bit-field widths
so take advantage of this and convert `ffssi2' and `ctzsi2' to templates
for all the three of QI, HI, SI machine modes.
Test cases will be added separately.
gcc/
* config/vax/builtins.md (width): New mode attribute.
(ffssi2): Rework expander into...
(ffs<mode>2): ... this.
(ctzsi2): Rework insn into...
(ctz<mode>2): ... this.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/vax/builtins.md | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index e8cefe7..b7ed976 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -23,14 +23,15 @@ ] ) +(define_mode_attr width [(QI "8") (HI "16") (SI "32")]) (define_mode_attr bb_mem [(QI "m") (HI "Q") (SI "Q")]) (define_int_iterator bit [0 1]) (define_int_attr ccss [(0 "cc") (1 "ss")]) -(define_expand "ffssi2" +(define_expand "ffs<mode>2" [(set (match_operand:SI 0 "nonimmediate_operand" "") - (ffs:SI (match_operand:SI 1 "general_operand" "")))] + (ffs:SI (match_operand:VAXint 1 "general_operand" "")))] "" " { @@ -39,22 +40,22 @@ rtx cond = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx); rtx target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label_ref, pc_rtx); - emit_insn (gen_ctzsi2 (operands[0], operands[1])); + emit_insn (gen_ctz<mode>2 (operands[0], operands[1])); emit_jump_insn (gen_rtx_SET (pc_rtx, target)); - emit_insn (gen_negsi2 (operands[0], const1_rtx)); + emit_insn (gen_neg<mode>2 (operands[0], const1_rtx)); emit_label (label); - emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx)); + emit_insn (gen_add<mode>3 (operands[0], operands[0], const1_rtx)); DONE; }") -(define_insn "ctzsi2" +(define_insn "ctz<mode>2" [(set (match_operand:SI 0 "nonimmediate_operand" "=rQ") - (ctz:SI (match_operand:SI 1 "general_operand" "nrQT"))) + (ctz:SI (match_operand:VAXint 1 "general_operand" "nrQT"))) (set (cc0) (compare (match_dup 1) (const_int 0)))] "" - "ffs $0,$32,%1,%0") + "ffs $0,$<width>,%1,%0") (define_expand "sync_lock_test_and_set<mode>" [(match_operand:VAXint 0 "nonimmediate_operand" "=&g") |