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2018-05-10re PR fortran/85735 (f951 crashes on empty input)Marek Polacek2-0/+6
PR fortran/85735 * options.c (gfc_post_options): Set main_input_filename. From-SVN: r260120
2018-05-10re PR c++/85662 ("error: non-constant condition for static assertion" from ↵Jakub Jelinek10-20/+54
__builtin_offsetof in C++) PR c++/85662 * c-common.h (fold_offsetof_1): Removed. (fold_offsetof): Add TYPE argument defaulted to size_type_node and CTX argument defaulted to ERROR_MARK. * c-common.c (fold_offsetof_1): Renamed to ... (fold_offsetof): ... this. Remove wrapper function. Add TYPE argument, convert the pointer constant to TYPE and use size_binop with PLUS_EXPR instead of fold_build_pointer_plus if type is not a pointer type. Adjust recursive calls. * c-fold.c (c_fully_fold_internal): Use fold_offsetof rather than fold_offsetof_1, pass TREE_TYPE (expr) as TYPE to it and drop the fold_convert_loc. * c-typeck.c (build_unary_op): Use fold_offsetof rather than fold_offsetof_1, pass argtype as TYPE to it and drop the fold_convert_loc. * cp-gimplify.c (cp_fold): Use fold_offsetof rather than fold_offsetof_1, pass TREE_TYPE (x) as TYPE to it and drop the fold_convert. * g++.dg/ext/offsetof2.C: New test. From-SVN: r260119
2018-05-10re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute ↵Uros Bizjak2-0/+20
Difference) instruction) PR target/85693 * config/i386/sse.md (usadv64qi): New expander. From-SVN: r260117
2018-05-10re PR fortran/54613 ([F08] Add FINDLOC plus support MAXLOC/MINLOC with ↵Thomas Koenig2-7/+20
KIND=/BACK=) 2018-05-10 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/54613 * intrinsic.texi: Document BACK for MINLOC and MAXLOC. From-SVN: r260116
2018-05-10re PR fortran/68846 (Pointer function as LValue doesn't work when the ↵Paul Thomas5-1/+178
assignment regards a dummy argument.) 2018-05-10 Paul Thomas <pault@gcc.gnu.org> PR fortran/68846 PR fortran/70864 * resolve.c (get_temp_from_expr): The temporary must not have dummy or intent attributes. 2018-05-10 Paul Thomas <pault@gcc.gnu.org> PR fortran/68846 * gfortran.dg/temporary_3.f90 : New test. PR fortran/70864 * gfortran.dg/temporary_2.f90 : New test. From-SVN: r260113
2018-05-10rs6000: Remove -maltivec={be,le}Segher Boessenkool37-2072/+210
This removes the -maltivec=be and -maltivec=le options. Those were deprecated in GCC 8. Altivec will keep working on both BE and LE; it is just the BE-vectors- on-LE that is removed (the other way around was never supported). The main change is replacing VECTOR_ELT_ORDER_BIG by BYTES_BIG_ENDIAN (and then simplifying). * config/rs6000/altivec.md (altivec_vmrghb, altivec_vmrghh, altivec_vmrghw, altivec_vmrglb, altivec_vmrglh, altivec_vmrglw): Remove -maltivec=be support. (vec_widen_umult_even_v16qi, vec_widen_smult_even_v16qi, vec_widen_umult_even_v8hi, vec_widen_smult_even_v8hi, vec_widen_umult_even_v4si, vec_widen_smult_even_v4si, vec_widen_umult_odd_v16qi, vec_widen_smult_odd_v16qi, vec_widen_umult_odd_v8hi, vec_widen_smult_odd_v8hi, vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, altivec_vpkpx, altivec_vpks<VI_char>ss, altivec_vpks<VI_char>us, altivec_vpku<VI_char>us, altivec_vpku<VI_char>um, altivec_vsum2sws, altivec_vsumsws): Adjust. (altivec_vspltb *altivec_vspltb_internal, altivec_vsplth, *altivec_vsplth_internal, altivec_vspltw, *altivec_vspltw_internal, altivec_vspltsf, *altivec_vspltsf_internal): Remove -maltivec=be support. (altivec_vperm_<mode>, altivec_vperm_<mode>_uns, altivec_vupkhs<VU_char>, altivec_vupkls<VU_char>, altivec_vupkhpx, altivec_vupklpx, altivec_lvsl, altivec_lvsr): Adjust. (altivec_lve<VI_char>x): Delete expand. (*altivec_lve<VI_char>x_internal): Rename to... (altivec_lve<VI_char>x): ... this. (altivec_lvxl_<mode>): Delete expand. (*altivec_lvxl_<mode>_internal): Rename to ... (altivec_lvxl_<mode>): ... this. (altivec_stvxl_<mode>): Delete expand. (*altivec_stvxl_<mode>_internal): Rename to ... (altivec_stvxl_<mode>): ... this. (altivec_stve<VI_char>x): Delete expand. (*altivec_stve<VI_char>x_internal): Rename to ... (altivec_stve<VI_char>x): ... this. (doublee<mode>2, unsdoubleev4si2, doubleo<mode>2, unsdoubleov4si2, doubleh<mode>2, unsdoublehv4si2, doublel<mode>2, unsdoublelv4si2, reduc_plus_scal_<mode>): Adjust. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Adjust comment. (rs6000_cpu_cpp_builtins): Adjust. (altivec_resolve_overloaded_builtin): Remove -maltivec=be support. * config/rs6000/rs6000-protos.h (altivec_expand_lvx_be, altivec_expand_stvx_be, altivec_expand_stvex_be): Delete. * config/rs6000/rs6000.c (rs6000_option_override_internal): Remove -maltivec=be support. (rs6000_split_vec_extract_var): Adjust. (rs6000_split_v4si_init): Adjust. (swap_selector_for_mode): Delete. (altivec_expand_lvx_be, altivec_expand_stvx_be, altivec_expand_stvex_be): Delete. (altivec_expand_lv_builtin, altivec_expand_stv_builtin): Remove -maltivec=be support. (rs6000_gimple_fold_builtin): Ditto. (rs6000_generate_float2_double_code, rs6000_generate_float2_code): Adjust. * config/rs6000/rs6000.h (VECTOR_ELT_ORDER_BIG): Delete. (TARGET_DIRECT_MOVE_64BIT): Adjust. * config/rs6000/rs6000.md (split for extendsidi2 for vectors): Adjust. * config/rs6000/rs6000.opt (maltivec=le, maltivec=be): Delete. * config/rs6000/vsx.md (floate<mode>, unsfloatev2di, floato<mode>, unsfloatov2di, vsignedo_v2df, vsignede_v2df, vunsignedo_v2df, vunsignede_v2df, vsx_extract_<mode>_p9, *vsx_extract_si, *vsx_extract_<mode>_p8, *vsx_extract_si_<uns>float_df, *vsx_extract_si_<uns>float_<mode>, vsx_set_<mode>_p9, vsx_set_v4sf_p9, *vsx_insert_extract_v4sf_p9, *vsx_insert_extract_v4sf_p9_2, and an anonymous split): Adjust. (vsx_mergel_<mode>, vsx_mergeh_<mode>): Remove -maltivec=be support. (vsx_xxspltd_<mode>, extract4b, insert4b): Adjust. gcc/testsuite/ * gcc.dg/vmx/extract-be-order.c: Delete testcase. * gcc.dg/vmx/extract-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/insert-be-order.c: Delete testcase. * gcc.dg/vmx/insert-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/ld-be-order.c: Delete testcase. * gcc.dg/vmx/ld-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/lde-be-order.c: Delete testcase. * gcc.dg/vmx/ldl-be-order.c: Delete testcase. * gcc.dg/vmx/ldl-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/merge-be-order.c: Delete testcase. * gcc.dg/vmx/merge-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/mult-even-odd-be-order.c: Delete testcase. * gcc.dg/vmx/pack-be-order.c: Delete testcase. * gcc.dg/vmx/perm-be-order.c: Delete testcase. * gcc.dg/vmx/splat-be-order.c: Delete testcase. * gcc.dg/vmx/splat-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/st-be-order.c: Delete testcase. * gcc.dg/vmx/st-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/ste-be-order.c: Delete testcase. * gcc.dg/vmx/stl-be-order.c: Delete testcase. * gcc.dg/vmx/stl-vsx-be-order.c: Delete testcase. * gcc.dg/vmx/sum2s-be-order.c: Delete testcase. * gcc.dg/vmx/unpack-be-order.c: Delete testcase. * gcc.dg/vmx/vsums-be-order.c: Delete testcase. * gcc.target/powerpc/vec-setup-be-double.c: Delete testcase. * gcc.target/powerpc/vec-setup-be-long.c: Delete testcase. * gcc.target/powerpc/vec-setup.h: Remove -maltivec=be support. From-SVN: r260109
2018-05-10configure.ac (gcc_gxx_include_dir_add_sysroot): Set it to 1 only when ↵Eric Botcazou3-14/+20
--with-gxx-include-dir is also specified. * configure.ac (gcc_gxx_include_dir_add_sysroot): Set it to 1 only when --with-gxx-include-dir is also specified. * configure: Regenerate. From-SVN: r260108
2018-05-10re PR tree-optimization/85699 (gcc.dg/nextafter-2.c fail)Jakub Jelinek3-2/+22
PR tree-optimization/85699 * gcc.dg/nextafter-1.c (NO_LONG_DOUBLE): Define if not defined. Use !NO_LONG_DOUBLE instead of __LDBL_MANT_DIG__ != 106. * gcc.dg/nextafter-2.c: Include stdlib.h. For glibc < 2.24 define NO_LONG_DOUBLE to 1 before including nextafter-1.c. From-SVN: r260107
2018-05-10re PR c++/85400 (invalid Local Dynamic TLS relaxation for symbol defined in ↵Eric Botcazou6-3/+58
method) PR c++/85400 cp/ * decl2.c (adjust_var_decl_tls_model): New static function. (comdat_linkage): Call it on a variable. (maybe_make_one_only): Likewise. c-family/ * c-attribs.c (handle_visibility_attribute): Do not set no_add_attrs. From-SVN: r260106
2018-05-10Daily bump.GCC Administrator1-1/+1
From-SVN: r260104
2018-05-09go/build, cmd/go: update to match recent changes to gcIan Lance Taylor1-1/+1
Several recent changes to the gc version of cmd/go improve the gofrontend support. These changes are partially copies of existing gofrontend differences, and partially new code. This CL makes the gofrontend match the upstream code. The changes included here come from: https://golang.org/cl/111575 https://golang.org/cl/111595 https://golang.org/cl/111635 https://golang.org/cl/111636 For the record, the following recent gc changes are based on code already present in the gofrontend repo: https://golang.org/cl/110915 https://golang.org/cl/111615 For the record, a gc change, partially based on earlier gofrontend work, also with new gc code, was already copied to gofrontend repo in CL 111099: https://golang.org/cl/111097 This moves the generated list of standard library packages from cmd/go/internal/load to go/build. Reviewed-on: https://go-review.googlesource.com/112475 gotools/: * Makefile.am (check-go-tool): Don't copy zstdpkglist.go. * Makefile.in: Rebuild. From-SVN: r260097
2018-05-09RISC-V: Add with-multilib-list support.Jim Wilson5-2/+126
gcc/ PR target/84797 * config.gcc (riscv*-*-*): Handle --with-multilib-list. * config/riscv/t-withmultilib: New. * config/riscv/withmultilib.h: New. * doc/install.texi: Document RISC-V --with-multilib-list support. From-SVN: r260096
2018-05-09re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)Paolo Carlini2-1/+11
2018-05-09 Paolo Carlini <paolo.carlini@oracle.com> PR c++/85713 * g++.dg/cpp1y/lambda-generic-85713.C: New. From-SVN: r260092
2018-05-09builtins-8-runnable.c: New builtin test file.Carl Love2-0/+101
gcc/testsuite/ChangeLog: 2018-05-09 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-8-runnable.c: New builtin test file. From-SVN: r260090
2018-05-09re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)Paolo Carlini1-0/+0
/cp 2018-05-09 Paolo Carlini <paolo.carlini@oracle.com> PR c++/85713 Revert: 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * parser.c (cp_parser_parameter_declaration_list): When the entire parameter-declaration-list is erroneous maybe call abort_fully_implicit_template. /testsuite 2018-05-09 Paolo Carlini <paolo.carlini@oracle.com> PR c++/85713 Revert: 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * g++.dg/cpp1y/pr84588.C: New. From-SVN: r260087
2018-05-09re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)Paolo Carlini4-12/+20
/cp 2018-05-09 Paolo Carlini <paolo.carlini@oracle.com> PR c++/85713 Revert: 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * parser.c (cp_parser_parameter_declaration_list): When the entire parameter-declaration-list is erroneous maybe call abort_fully_implicit_template. /testsuite 2018-05-09 Paolo Carlini <paolo.carlini@oracle.com> PR c++/85713 Revert: 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * g++.dg/cpp1y/pr84588.C: New. From-SVN: r260086
2018-05-09* gcc.target/aarch64/sve/vcond_6.c: Add missing brace.Andreas Schwab2-1/+5
From-SVN: r260082
2018-05-09tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost vector.Richard Biener2-15/+36
2018-05-09 Richard Biener <rguenther@suse.de> * tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost vector. (vect_bb_vectorization_profitable_p): Adjust. Compute actual scalar cost using the cost vector and the add_stmt_cost machinery. From-SVN: r260078
2018-05-09rs6000: Give an argument to every REG_CFA_REGISTER (PR85645)Segher Boessenkool2-3/+9
The one for the prologue mflr did not have any value set, which means use the SET that is in the insn pattern. This works fine, except when some late pass decides to replace the SET_SRC -- this changes the meaning of the REG_CFA_REGISTER! Such passes should not do these things, but let's be more explicit here, for extra robustness. It could be argued that this defaulting is a design misfeature (it does not save much space either, etc.) PR rtl-optimization/85645 * config/rs6000/rs6000.c (rs6000_emit_prologue_components): Put a SET in the REG_CFA_REGISTER note for LR, don't leave it empty. From-SVN: r260077
2018-05-09shrink-wrap: Improve spread_components (PR85645)Segher Boessenkool2-3/+30
In the testcase for PR85645 we do a pretty dumb placement of the prologue/epilogue for the LR component: we place an epilogue for LR before a control flow split where one of the branches clobbers LR eventually, and the other does not. The branch that does clobber it will need a prologue again some time later. Because saving and restoring LR is a two step process---it needs to be moved via a GPR--- the backend emits CFI directives so that we get correct unwind information. But both regcprop and regrename do not properly handle such CFI directives leading to ICEs. Now, neither of the two branches needs to have LR restored at all, because both of the branches end up in an infinite loop. This patch makes spread_component return a boolean saying if anything was changed, and if so, it is called again. This obviously is finite (there is a finite number of basic blocks, each with a finite number of components, and spread_components can only assign more components to a block, never less). I also instrumented the code, and on a bootstrap+regtest spread_components made changes a maximum of two times. Interestingly though it made changes on two iterations in a third of the cases it did anything at all! PR rtl-optimization/85645 * shrink-wrap.c (spread_components): Return a boolean saying if anything was changed. (try_shrink_wrapping_separate): Iterate spread_components until nothing changes anymore. From-SVN: r260076
2018-05-09regrename: Don't rename the dest of a REG_CFA_REGISTER (PR85645)Segher Boessenkool2-4/+21
We should never change the destination of a REG_CFA_REGISTER, just like for insns with a REG_CFA_RESTORE, because we need to have the same control flow information on all branches that join. It is very doubtful that renaming the scratch registers used for prologue/epilogue will help anything either. PR rtl-optimization/85645 * regrename.c (build_def_use): Also kill the chains that include the destination of a REG_CFA_REGISTER note. From-SVN: r260075
2018-05-09regcprop: Avoid REG_CFA_REGISTER notes (PR85645)Segher Boessenkool2-0/+12
Changing a SET that has a REG_CFA_REGISTER note is wrong if we are changing the SET_DEST, or if the REG_CFA_REGISTER has nil as its argument, and maybe some other cases. It's never really useful to propagate into such an instruction, so let's just bail whenever we see such a note. PR rtl-optimization/85645 * regcprop.c (copyprop_hardreg_forward_1): Don't propagate into an insn that has a REG_CFA_REGISTER note. From-SVN: r260074
2018-05-09Add clobbers around IFN_LOAD/STORE_LANESRichard Sandiford6-17/+105
We build up the input to IFN_STORE_LANES one vector at a time. In RTL, each of these vector assignments becomes a write to subregs of the form (subreg:VEC (reg:AGGR R)), where R is the eventual input to the store lanes instruction. The problem is that RTL isn't very good at tracking liveness when things are initialised piecemeal by subregs, so R tends to end up being live on all paths from the entry block to the store. This in turn leads to unnecessary spilling around calls, as well as to excess register pressure in vector loops. This patch adds gimple clobbers to indicate the liveness of the IFN_STORE_LANES variable and makes sure that gimple clobbers are expanded to rtl clobbers where useful. For consistency it also uses clobbers to mark the point at which an IFN_LOAD_LANES variable is no longer needed. 2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * cfgexpand.c (expand_clobber): New function. (expand_gimple_stmt_1): Use it. * tree-vect-stmts.c (vect_clobber_variable): New function, split out from... (vectorizable_simd_clone_call): ...here. (vectorizable_store): Emit a clobber either side of an IFN_STORE_LANES sequence. (vectorizable_load): Emit a clobber after an IFN_LOAD_LANES sequence. gcc/testsuite/ * gcc.target/aarch64/store_lane_spill_1.c: New test. * gcc.target/aarch64/sve/store_lane_spill_1.c: Likewise. From-SVN: r260073
2018-05-09[nvptx] Make trap insn noreturnTom de Vries2-3/+9
2018-05-09 Tom de Vries <tom@codesourcery.com> PR target/85626 * config/nvptx/nvptx.md (define_insn "trap", define_insn "trap_if_true") (define_insn "trap_if_false"): Add exit after trap. From-SVN: r260072
2018-05-09re PR rtl-optimization/85638 (build failure for Ada runtime with SJLJ ↵Eric Botcazou2-30/+108
exceptions on x86) PR rtl-optimization/85638 * bb-reorder.c: Include common/common-target.h. (create_forwarder_block): New function extracted from... (fix_up_crossing_landing_pad): ...here. Rename into... (dw2_fix_up_crossing_landing_pad): ...this. (sjlj_fix_up_crossing_landing_pad): New function. (find_rarely_executed_basic_blocks_and_crossing_edges): In SJLJ mode, call sjlj_fix_up_crossing_landing_pad if there are incoming EH edges from both partitions and exit the loop after one iteration. From-SVN: r260070
2018-05-08PR c++/85706 - class deduction under decltypeJason Merrill3-1/+19
* pt.c (for_each_template_parm_r): Handle DECLTYPE_TYPE. Clear *walk_subtrees whether or not we walked into the operand. (type_uses_auto): Only look at deduced contexts. From-SVN: r260066
2018-05-09revert: extend.texi (PowerPC Built-in Functions): Rename this subsection.Kelvin Nilsen2-476/+432
2018-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org> Revert: * doc/extend.texi (PowerPC Built-in Functions): Rename this subsection. (Basic PowerPC Built-in Functions): The new name of the subsection previously known as "PowerPC Built-in Functions". (Basic PowerPC Built-in Functions Available on all Configurations): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.05): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.06): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.07): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 3.0): New subsubsection. From-SVN: r260065
2018-05-09Daily bump.GCC Administrator1-1/+1
From-SVN: r260063
2018-05-09* de.po, sv.po: Update.Joseph Myers3-319/+161
From-SVN: r260057
2018-05-08[PATCH] RISC-V: Use new linker emulations for glibc ABI.Jim Wilson2-2/+16
gcc/ * config/riscv/linux.h (MUSL_ABI_SUFFIX): Delete unnecessary backslash. (LD_EMUL_SUFFIX): New. (LINK_SPEC): Use it. From-SVN: r260056
2018-05-08builtins-8-p9-runnable.c: Add new test file.Carl Love2-0/+1046
gcc/testsuite/ChangeLog: 2018-05-08 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/builtins-8-p9-runnable.c: Add new test file. From-SVN: r260055
2018-05-08re PR c++/84588 (internal compiler error: Segmentation fault ↵Paolo Carlini4-0/+24
(contains_struct_check())) /cp 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * parser.c (cp_parser_parameter_declaration_list): When the entire parameter-declaration-list is erroneous maybe call abort_fully_implicit_template. /testsuite 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/84588 * g++.dg/cpp1y/pr84588.C: New. From-SVN: r260050
2018-05-08re PR c++/85695 (if constexpr misevaluates typedefed type value)Marek Polacek4-1/+32
PR c++/85695 * semantics.c (finish_if_stmt_cond): See through typedefs. * g++.dg/cpp1z/constexpr-if22.C: New test. From-SVN: r260049
2018-05-08extend.texi (PowerPC Built-in Functions): Rename this subsection.Kelvin Nilsen2-414/+493
gcc/ChangeLog: 2018-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org> * doc/extend.texi (PowerPC Built-in Functions): Rename this subsection. (Basic PowerPC Built-in Functions): The new name of the subsection previously known as "PowerPC Built-in Functions". (Basic PowerPC Built-in Functions Available on all Configurations): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.05): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.06): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 2.07): New subsubsection. (Basic PowerPC Built-in Functions Available on ISA 3.0): New subsubsection. From-SVN: r260048
2018-05-08re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute ↵Uros Bizjak2-0/+26
Difference) instruction) PR target/85693 * gcc.target/i386/pr85693.c: New test. From-SVN: r260047
2018-05-08re PR target/85683 (GCC 8 stopped using RMW (Read Modify Write) instructions ↵Jakub Jelinek4-1/+76
on x86[_64]) PR target/85683 * config/i386/i386.md: Add peepholes for mem {+,-,&,|,^}= x; mem != 0 after cmpelim optimization. * gcc.target/i386/pr49095.c: Add -masm=att to dg-options. Add scan-assembler-times checking that except for [fh]*xor other functions don't use any load instructions. From-SVN: r260045
2018-05-08config.gcc: Support "goldmont".Olga Makhotina13-29/+818
2018-05-08 Olga Makhotina <olga.makhotina@intel.com> gcc/ * config.gcc: Support "goldmont". * config/i386/driver-i386.c (host_detect_local_cpu): Detect "goldmont". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_GOLDMONT. * config/i386/i386.c (m_GOLDMONT): Define. (processor_target_table): Add "goldmont". (PTA_GOLDMONT): Define. (ix86_lea_outperforms): Add TARGET_GOLDMONT. (get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT. (fold_builtin_cpu): Add M_INTEL_GOLDMONT. (fold_builtin_cpu): Add "goldmont". (ix86_add_stmt_cost): Add TARGET_GOLDMONT. (ix86_option_override_internal): Add "goldmont". * config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT. (processor_type): Add PROCESSOR_GOLDMONT. * config/i386/i386.md: Add CPU "glm". * config/i386/glm.md: New file. * config/i386/x86-tune.def: Add m_GOLDMONT. * doc/invoke.texi: Add goldmont as x86 -march=/-mtune= CPU type. libgcc/ * config/i386/cpuinfo.h (processor_types): Add INTEL_GOLDMONT. * config/i386/cpuinfo.c (get_intel_cpu): Detect Goldmont. gcc/testsuite/ * gcc.target/i386/builtin_target.c: Test goldmont. * gcc.target/i386/funcspec-56.inc: Tests for arch=goldmont and arch=silvermont. From-SVN: r260042
2018-05-08re PR target/85572 (faster code for absolute value of __v2di)Jakub Jelinek8-25/+165
PR target/85572 * config/i386/i386.c (ix86_expand_sse2_abs): Handle E_V2DImode and E_V4DImode. * config/i386/sse.md (abs<mode>2): Use VI_AVX2 iterator instead of VI1248_AVX512VL_AVX512BW. Handle V2DImode and V4DImode if not TARGET_AVX512VL using ix86_expand_sse2_abs. Formatting fixes. * g++.dg/other/sse2-pr85572-1.C: New test. * g++.dg/other/sse2-pr85572-2.C: New test. * g++.dg/other/sse4-pr85572-1.C: New test. * g++.dg/other/avx2-pr85572-1.C: New test. From-SVN: r260041
2018-05-08re PR target/85317 (missing constant propagation on _mm(256)_movemask_*)Jakub Jelinek5-0/+79
PR target/85317 * config/i386/i386.c (ix86_fold_builtin): Handle IX86_BUILTIN_{,P}MOVMSK{PS,PD,B}{,128,256}. * gcc.target/i386/pr85317.c: New test. * gcc.target/i386/avx2-vpmovmskb-2.c (avx2_test): Add asm volatile optimization barrier to avoid optimizing away the expected insn. From-SVN: r260040
2018-05-08re PR target/85480 (zero extension from xmm to zmm via _mm512_insert???x? ↵Jakub Jelinek5-0/+113
not optimized) PR target/85480 * config/i386/sse.md (ssequaterinsnmode): New mode attribute. (*<extract_type>_vinsert<shuffletype><extract_suf>_0): New pattern. * gcc.target/i386/avx512dq-pr85480-1.c: New test. * gcc.target/i386/avx512dq-pr85480-2.c: New test. From-SVN: r260039
2018-05-08Move C++ SVE tests to g++.target/aarch64/sveRichard Sandiford8-13/+31
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> gcc/testsuite/ * g++.dg/other/sve_const_pred_1.C: Rename to... * g++.target/aarch64/sve/const_pred_1.C: ...this. Remove aarch64 target selectors and explicit -march options. * g++.dg/other/sve_const_pred_2.C: Rename to... * g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_3.C: Rename to... * g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_4.C: Rename to... * g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise. * g++.dg/other/sve_tls_2.C: Rename to... * g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1.C: Rename to... * g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1_run.C: Rename to... * g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise. From-SVN: r260038
2018-05-08Tighten condition in vect/pr85586.c (PR 85654)Richard Sandiford2-1/+7
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> gcc/testsuite/ PR testsuite/85586 * gcc.dg/vect/pr85586.c: Restrict LOOP VECTORIZED test to !vect_no_align. From-SVN: r260036
2018-05-08re PR c++/57429 (Dependent function call with one visible declaration, deleted)Paolo Carlini2-0/+15
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/57429 * g++.dg/cpp0x/deleted14.C: New. From-SVN: r260035
2018-05-08[arm] PR target/85658 Fix operator precedence errors in parsecpu.awkRichard Earnshaw2-9/+20
There are a number of places in parsecpu.awk where I've managed to get the operator precedence between ! and 'in' incorrect (! binds more tightly). In most cases this just makes a consistency test ineffective, but in a few cases it means we fail to correctly diagnose errors by the user (for example, when passing an invalid cpu or architecture name to configure. This patch fixes all the cases I could find, based on searching for all uses of the two operators in the same expression. The tweak to the API of check_fpu is to bring it into line with the other check functions - it now returns the result rather than printing it directly. The caller now does the printing, in the same way that the chkarch and chkcpu commands do. PR target/85658 * config/arm/parsecpu.awk (check_cpu): Fix operator precedence. (check_arch): Likewise. (check_fpu): Return the result rather than printing it. (end arch): Fix operator precedence. (end cpu): Likewise. (END): Print the result from check_fpu. From-SVN: r260032
2018-05-08[AArch64] Predicated SVE comparison foldsRichard Sandiford6-2/+402
This patch adds SVE patterns that combine a PTRUE-predicated comparison with a separate AND. The main benefit is for optimising ANDs with the loop predicate, as in the testcase. However, one of the potential drawbacks is that it triggers even for cases in which two naturally-parallel comparisons are ANDed together. Whether that's a win or a less will depend on the schedule, but it has the potential to be a win more often than a loss. The combine patterns are undeniably ugly. One way of getting around them would be to allow 1->1 "splits" when combining 2 instructions, as well as 1->2 splits when combining more than 2 instructions (although that wouldn't really be a split). Another would be to have a way of defining target-specific rtx simplifications. branches/ARM/sve-branch has a prototype implementation of that, but it would need some clean-up before being ready to submit. It would also be good to make it closer to the match.pd style. Until then, I think what the combine patterns are doing is the "correct" implementation given the current infrastructure. 2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * config/aarch64/aarch64-sve.md (*pred_cmp<cmp_op><mode>_combine) (*pred_cmp<cmp_op><mode>, *fcm<cmp_op><mode>_and_combine) (*fcmuo<mode>_and_combine, *fcm<cmp_op><mode>_and) (*fcmuo<mode>_and): New patterns. gcc/testsuite/ * gcc.target/aarch64/sve/vcond_6.c: Do not expect any ANDs. XFAIL the BIC test. * gcc.target/aarch64/sve/vcond_7.c: New test. * gcc.target/aarch64/sve/vcond_7_run.c: Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r260031
2018-05-08re PR c++/70563 (SFINAE fails when trying invalid template instantiation)Paolo Carlini2-0/+46
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/70563 * g++.dg/cpp0x/sfinae62.C: New. From-SVN: r260030
2018-05-08[AArch64] Use UNSPEC_MERGE_PTRUE for comparisonsRichard Sandiford4-166/+265
This patch rewrites the SVE comparison handling so that it uses UNSPEC_MERGE_PTRUE for comparisons that are known to be predicated on a PTRUE, for consistency with other patterns. Specific unspecs are then only needed for truly predicated floating-point comparisons, such as those used in the expansion of UNEQ for flag_trapping_math. The patch also makes sure that the comparison expanders attach a REG_EQUAL note to instructions that use UNSPEC_MERGE_PTRUE, so passes can use that as an alternative to the unspec pattern. (This happens automatically for optabs. The problem was that this code emits instruction patterns directly.) No specific benefit on its own, but it lays the groundwork for the next patch. 2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * config/aarch64/iterators.md (UNSPEC_COND_LO, UNSPEC_COND_LS) (UNSPEC_COND_HI, UNSPEC_COND_HS, UNSPEC_COND_UO): Delete. (SVE_INT_CMP, SVE_FP_CMP): New code iterators. (cmp_op, sve_imm_con): New code attributes. (SVE_COND_INT_CMP, imm_con): Delete. (cmp_op): Remove above unspecs from int attribute. * config/aarch64/aarch64-sve.md (*vec_cmp<cmp_op>_<mode>): Rename to... (*cmp<cmp_op><mode>): ...this. Use UNSPEC_MERGE_PTRUE instead of comparison-specific unspecs. (*vec_cmp<cmp_op>_<mode>_ptest): Rename to... (*cmp<cmp_op><mode>_ptest): ...this and adjust likewise. (*vec_cmp<cmp_op>_<mode>_cc): Rename to... (*cmp<cmp_op><mode>_cc): ...this and adjust likewise. (*vec_fcm<cmp_op><mode>): Rename to... (*fcm<cmp_op><mode>): ...this and adjust likewise. (*vec_fcmuo<mode>): Rename to... (*fcmuo<mode>): ...this and adjust likewise. (*pred_fcm<cmp_op><mode>): New pattern. * config/aarch64/aarch64.c (aarch64_emit_unop, aarch64_emit_binop) (aarch64_emit_sve_ptrue_op, aarch64_emit_sve_ptrue_op_cc): New functions. (aarch64_unspec_cond_code): Remove handling of LTU, GTU, LEU, GEU and UNORDERED. (aarch64_gen_unspec_cond, aarch64_emit_unspec_cond): Delete. (aarch64_emit_sve_predicated_cond): New function. (aarch64_expand_sve_vec_cmp_int): Use aarch64_emit_sve_ptrue_op_cc. (aarch64_emit_unspec_cond_or): Replace with... (aarch64_emit_sve_or_conds): ...this new function. Use aarch64_emit_sve_ptrue_op for the individual comparisons and aarch64_emit_binop to OR them together. (aarch64_emit_inverted_unspec_cond): Replace with... (aarch64_emit_sve_inverted_cond): ...this new function. Use aarch64_emit_sve_ptrue_op for the comparison and aarch64_emit_unop to invert the result. (aarch64_expand_sve_vec_cmp_float): Update after the above changes. Use aarch64_emit_sve_ptrue_op for native comparisons. From-SVN: r260029
2018-05-08[AArch64] Tweak sve/vcond_6.c testRichard Sandiford2-6/+12
sve/vcond_6.c was effectively testing a three-input logical operation, since the result of BINOP needed to be ANDed with the loop predicate before loading src[i]. This patch makes it really test a binary operation instead. A later patch will add (and optimise) the three-operand case. 2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> gcc/testsuite/ * gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally load from src[i]. From-SVN: r260028
2018-05-08re PR c++/80691 (Narrowing conversion in {} allowed in a SFINAE context)Paolo Carlini2-0/+29
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/80691 * g++.dg/cpp0x/narrowing1.C: New. From-SVN: r260027
2018-05-08re PR tree-optimization/85588 (-fwrapv miscompilation)Richard Biener2-0/+6
2018-05-08 Richard Biener <rguenther@suse.de> PR middle-end/85588 * gcc.dg/torture/pr85574.c: Rename to... * gcc.dg/torture/pr85588.c: ... this. From-SVN: r260024
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