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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2018-05-08 09:35:36 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2018-05-08 09:35:36 +0000 |
| commit | 4fdd8b18ecb46da1b89c00f1ab500fb15106189d (patch) | |
| tree | 3ade4980cbefa2515678f71e49237b7485ba41b9 /gcc | |
| parent | 3e8f909a069d36528b4cfd404db8d857f9a9d95b (diff) | |
| download | gcc-4fdd8b18ecb46da1b89c00f1ab500fb15106189d.zip gcc-4fdd8b18ecb46da1b89c00f1ab500fb15106189d.tar.gz gcc-4fdd8b18ecb46da1b89c00f1ab500fb15106189d.tar.bz2 | |
[AArch64] Tweak sve/vcond_6.c test
sve/vcond_6.c was effectively testing a three-input logical operation,
since the result of BINOP needed to be ANDed with the loop predicate
before loading src[i]. This patch makes it really test a binary
operation instead. A later patch will add (and optimise) the
three-operand case.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/testsuite/
* gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally
load from src[i].
From-SVN: r260028
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c | 13 |
2 files changed, 12 insertions, 6 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 000dc68..cc61ffb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-05-08 Richard Sandiford <richard.sandiford@linaro.org> + + * gcc.target/aarch64/sve/vcond_6.c (LOOP): Unconditionally + load from src[i]. + 2018-05-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/80691 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c index 67157e3..718afae 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_6.c @@ -19,9 +19,12 @@ TYPE fallback, int count) \ { \ for (int i = 0; i < count; ++i) \ - dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]), \ - __builtin_isunordered (c[i], d[i])) \ - ? src[i] : fallback); \ + { \ + TYPE srcv = src[i]; \ + dest[i] = (BINOP (__builtin_isunordered (a[i], b[i]), \ + __builtin_isunordered (c[i], d[i])) \ + ? srcv : fallback); \ + } \ } #define TEST_BINOP(T, BINOP) \ @@ -40,9 +43,7 @@ TEST_ALL (LOOP) -/* Currently we don't manage to remove ANDs from the other loops. */ -/* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} } } */ +/* { dg-final { scan-assembler-times {\tand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\torr\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\teor\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ /* { dg-final { scan-assembler-times {\tnand\tp[0-9]+\.b, p[0-9]+/z, p[0-9]+\.b, p[0-9]+\.b} 3 } } */ |