| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-06-01 | 2018-05-15 Michael Collison <michael.collison@arm.com> | Michael Collison | 1 | -0/+17 |
| 2018-05-31 | re PR target/85984 (ICE in create_pseudo_cfg, at dwarf2cfi.c:2874) | Jakub Jelinek | 1 | -0/+18 |
| 2018-05-31 | Patch implementing vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics for AARCH64 ... | Sameera Deshpande | 3 | -0/+243 |
| 2018-05-30 | Reverting r260635 | Andre Vieira | 1 | -25/+3 |
| 2018-05-30 | [AArch64] Improve LDP/STP generation that requires a base register | Jackson Woodruff | 4 | -0/+111 |
| 2018-05-29 | re PR target/85950 (Unsafe-math-optimizations regresses optimization using SS... | Uros Bizjak | 1 | -0/+16 |
| 2018-05-29 | re PR target/85918 (Conversions to/from [unsigned] long long are not vectoriz... | Jakub Jelinek | 2 | -13/+609 |
| 2018-05-28 | re PR tree-optimization/85934 (ICE: verify_gimple failed (error: type mismatc... | Richard Biener | 1 | -0/+20 |
| 2018-05-27 | re PR target/85918 (Conversions to/from [unsigned] long long are not vectoriz... | Jakub Jelinek | 1 | -0/+42 |
| 2018-05-25 | RISC-V: Add interrupt attribute support. | Jim Wilson | 5 | -0/+68 |
| 2018-05-25 | re PR target/85832 ([AVX512] possible shorter code when comparing with vector... | Jakub Jelinek | 4 | -0/+100 |
| 2018-05-25 | re PR tree-optimization/85720 (bad codegen for looped assignment of primitive... | Bin Cheng | 1 | -1/+1 |
| 2018-05-25 | Add IFN_COND_{MUL,DIV,MOD,RDIV} | Richard Sandiford | 3 | -4/+54 |
| 2018-05-25 | [AArch64] Add SVE support for integer division | Richard Sandiford | 4 | -0/+110 |
| 2018-05-25 | Fold VEC_COND_EXPRs to IFN_COND_* where possible | Richard Sandiford | 6 | -0/+459 |
| 2018-05-24 | sse.md (cvtusi2<ssescalarmodesuffix>64<round_name>): Add {q} suffix to insn m... | Uros Bizjak | 2 | -4/+4 |
| 2018-05-24 | Require ifunc support in gcc.target/i386/pr85345.c | Rainer Orth | 1 | -0/+1 |
| 2018-05-24 | PR target/83009: Relax strict address checking for store pair lanes | Andre Vieira | 1 | -3/+25 |
| 2018-05-23 | re PR target/78849 (ICE on initialization of global struct containing __int20... | Jeff Law | 2 | -4/+59 |
| 2018-05-23 | i386.md (*floatuns<SWI48:mode><MODEF:mode>2_avx512): New insn pattern. | Uros Bizjak | 2 | -0/+30 |
| 2018-05-23 | [AArch64][PR target/84882] Add mno-strict-align | Sudakshina Das | 2 | -0/+55 |
| 2018-05-22 | Don't mark IFUNC resolver as only called directly | H.J. Lu | 1 | -0/+44 |
| 2018-05-22 | [AArch64] Recognize a missed usage of a sbfiz instruction | Luis Machado | 1 | -0/+24 |
| 2018-05-22 | [AArch64] Merge stores of D-register values with different modes | Jackson Woodruff | 3 | -0/+97 |
| 2018-05-21 | re PR target/85657 (Make __ibm128 a separate type, even if long double uses t... | Michael Meissner | 3 | -0/+230 |
| 2018-05-21 | [AArch64][committed] Fix gcc.target/aarch64/vec_init_1.c for tiny and large m... | Kyrylo Tkachov | 1 | -1/+5 |
| 2018-05-21 | svn rm files missed out from "[arm][2/2] Remove support for -march=armv3 and ... | Kyrylo Tkachov | 3 | -98/+0 |
| 2018-05-21 | [AArch64] Implement usadv16qi and ssadv16qi standard names | Kyrylo Tkachov | 2 | -0/+54 |
| 2018-05-21 | Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a | Tamar Christina | 4 | -16/+36 |
| 2018-05-18 | [AARCH64, SVE] Remove a couple of xfail from slp_5.c | Sudakshina Das | 1 | -2/+2 |
| 2018-05-18 | [arm][1/2] Remove support for deprecated -march=armv5 and armv5e | Kyrylo Tkachov | 2 | -11/+3 |
| 2018-05-18 | [AArch64] Unify vec_set patterns, support floating-point vector modes properly | Kyrylo Tkachov | 1 | -0/+69 |
| 2018-05-17 | RISC-V: Optimize switch with sign-extended index. | Jim Wilson | 2 | -0/+30 |
| 2018-05-17 | re PR tree-optimization/85698 (CPU2017 525.x264_r fails starting with r257581) | Pat Haugen | 1 | -0/+79 |
| 2018-05-17 | re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away) | Jakub Jelinek | 3 | -0/+519 |
| 2018-05-17 | re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away) | Jakub Jelinek | 3 | -0/+217 |
| 2018-05-17 | re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away) | Jakub Jelinek | 3 | -0/+302 |
| 2018-05-17 | avx512fintrin.h (_mm512_set_epi16, [...]): New intrinsics. | Jakub Jelinek | 11 | -0/+1257 |
| 2018-05-17 | [patch AArch64] Do not perform a vector splat for vector initialisation if it... | James Greenhalgh | 1 | -0/+20 |
| 2018-05-17 | config.gcc: Support "goldmont-plus". | Olga Makhotina | 2 | -0/+5 |
| 2018-05-16 | vsx-vector-6-be.c: Remove file. | Carl Love | 2 | -32/+9 |
| 2018-05-16 | Handle vector boolean types when calculating the SLP unroll factor | Richard Sandiford | 4 | -0/+124 |
| 2018-05-14 | [AArch64] Add combine pattern to fuse AESE/AESMC instructions | Kyrylo Tkachov | 2 | -0/+90 |
| 2018-05-14 | Remove remaining uses of * in patterns | Wilco Dijkstra | 2 | -8/+8 |
| 2018-05-14 | i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, [...]): New defines. | Sebastian Peryt | 1 | -0/+11 |
| 2018-05-11 | i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, [...]): New defines. | Sebastian Peryt | 2 | -0/+54 |
| 2018-05-11 | re PR tree-optimization/85692 (Two source permute not used for vector initial... | Allan Sandfeld Jensen | 1 | -0/+18 |
| 2018-05-10 | * gcc.target/i386/xgetsetbv.c: Fix whitespace. | Uros Bizjak | 1 | -3/+3 |
| 2018-05-10 | i386.c (ix86_expand_builtin): Generate SImode target register for null target. | Uros Bizjak | 1 | -4/+18 |
| 2018-05-10 | rs6000: Remove -maltivec={be,le} | Segher Boessenkool | 3 | -47/+2 |
