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2018-05-24sse.md (cvtusi2<ssescalarmodesuffix>64<round_name>): Add {q} suffix to insn m...Uros Bizjak2-4/+4
2018-05-24Require ifunc support in gcc.target/i386/pr85345.cRainer Orth1-0/+1
2018-05-24PR target/83009: Relax strict address checking for store pair lanesAndre Vieira1-3/+25
2018-05-23re PR target/78849 (ICE on initialization of global struct containing __int20...Jeff Law2-4/+59
2018-05-23i386.md (*floatuns<SWI48:mode><MODEF:mode>2_avx512): New insn pattern.Uros Bizjak2-0/+30
2018-05-23[AArch64][PR target/84882] Add mno-strict-alignSudakshina Das2-0/+55
2018-05-22Don't mark IFUNC resolver as only called directlyH.J. Lu1-0/+44
2018-05-22[AArch64] Recognize a missed usage of a sbfiz instructionLuis Machado1-0/+24
2018-05-22[AArch64] Merge stores of D-register values with different modesJackson Woodruff3-0/+97
2018-05-21re PR target/85657 (Make __ibm128 a separate type, even if long double uses t...Michael Meissner3-0/+230
2018-05-21[AArch64][committed] Fix gcc.target/aarch64/vec_init_1.c for tiny and large m...Kyrylo Tkachov1-1/+5
2018-05-21svn rm files missed out from "[arm][2/2] Remove support for -march=armv3 and ...Kyrylo Tkachov3-98/+0
2018-05-21[AArch64] Implement usadv16qi and ssadv16qi standard namesKyrylo Tkachov2-0/+54
2018-05-21Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-aTamar Christina4-16/+36
2018-05-18[AARCH64, SVE] Remove a couple of xfail from slp_5.cSudakshina Das1-2/+2
2018-05-18[arm][1/2] Remove support for deprecated -march=armv5 and armv5eKyrylo Tkachov2-11/+3
2018-05-18[AArch64] Unify vec_set patterns, support floating-point vector modes properlyKyrylo Tkachov1-0/+69
2018-05-17RISC-V: Optimize switch with sign-extended index.Jim Wilson2-0/+30
2018-05-17re PR tree-optimization/85698 (CPU2017 525.x264_r fails starting with r257581)Pat Haugen1-0/+79
2018-05-17re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)Jakub Jelinek3-0/+519
2018-05-17re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)Jakub Jelinek3-0/+217
2018-05-17re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)Jakub Jelinek3-0/+302
2018-05-17avx512fintrin.h (_mm512_set_epi16, [...]): New intrinsics.Jakub Jelinek11-0/+1257
2018-05-17[patch AArch64] Do not perform a vector splat for vector initialisation if it...James Greenhalgh1-0/+20
2018-05-17config.gcc: Support "goldmont-plus".Olga Makhotina2-0/+5
2018-05-16vsx-vector-6-be.c: Remove file.Carl Love2-32/+9
2018-05-16Handle vector boolean types when calculating the SLP unroll factorRichard Sandiford4-0/+124
2018-05-14[AArch64] Add combine pattern to fuse AESE/AESMC instructionsKyrylo Tkachov2-0/+90
2018-05-14Remove remaining uses of * in patternsWilco Dijkstra2-8/+8
2018-05-14i386-common.c (OPTION_MASK_ISA_CLDEMOTE_SET, [...]): New defines.Sebastian Peryt1-0/+11
2018-05-11i386-common.c (OPTION_MASK_ISA_WAITPKG_SET, [...]): New defines.Sebastian Peryt2-0/+54
2018-05-11re PR tree-optimization/85692 (Two source permute not used for vector initial...Allan Sandfeld Jensen1-0/+18
2018-05-10* gcc.target/i386/xgetsetbv.c: Fix whitespace.Uros Bizjak1-3/+3
2018-05-10i386.c (ix86_expand_builtin): Generate SImode target register for null target.Uros Bizjak1-4/+18
2018-05-10rs6000: Remove -maltivec={be,le}Segher Boessenkool3-47/+2
2018-05-09builtins-8-runnable.c: New builtin test file.Carl Love1-0/+98
2018-05-09* gcc.target/aarch64/sve/vcond_6.c: Add missing brace.Andreas Schwab1-1/+1
2018-05-09Add clobbers around IFN_LOAD/STORE_LANESRichard Sandiford2-0/+40
2018-05-08builtins-8-p9-runnable.c: Add new test file.Carl Love1-0/+1043
2018-05-08re PR tree-optimization/85693 (Generation of SAD (Sum of Absolute Difference)...Uros Bizjak1-0/+21
2018-05-08re PR target/85683 (GCC 8 stopped using RMW (Read Modify Write) instructions ...Jakub Jelinek1-1/+4
2018-05-08config.gcc: Support "goldmont".Olga Makhotina2-0/+7
2018-05-08re PR target/85317 (missing constant propagation on _mm(256)_movemask_*)Jakub Jelinek2-0/+39
2018-05-08re PR target/85480 (zero extension from xmm to zmm via _mm512_insert???x? not...Jakub Jelinek2-0/+64
2018-05-08[AArch64] Predicated SVE comparison foldsRichard Sandiford3-2/+264
2018-05-08[AArch64] Tweak sve/vcond_6.c testRichard Sandiford1-6/+7
2018-05-06picdtr.c: Correct option -fPIE -mpic-data-is-text-relative.Michael Eager1-1/+1
2018-05-06picdtr.c: Add test for -fPIE -mpic-data-is-text-relative.Andrew Sadek1-0/+160
2018-05-04vsx-vector-6.h (foo): Add test for vec_max, vec_trunc.Carl Love3-7/+19
2018-05-03re PR target/85530 ([X86] _mm512_mullox_epi64 and _mm512_mask_mullox_epi64 no...Jakub Jelinek4-0/+125
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