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2018-11-09or1k: testsuite: initial support for openriscStafford Horne17-0/+236
2018-11-09neon.md (div<mode>3): New pattern.Prathamesh Kulkarni2-0/+32
2018-11-09Add PTWRITE builtins for x86Andi Kleen2-0/+44
2018-11-08Add mips option dependency only config with loongson target.Chenghua Xu1-4/+13
2018-11-07re PR c/87691 (transparent_union attribute does not work with MODE_PARTIAL_INT)Jozef Lawrynowicz1-0/+41
2018-11-07Fix some typo and brain twister logical.Chenghua Xu2-2/+2
2018-11-07Add support for Loongson EXT2 instructions.Chenghua Xu3-0/+23
2018-11-07Add support for Loongson EXT instructions.Chenghua Xu1-0/+2
2018-11-07Add support for Loongson MMI instructions.Chenghua Xu3-5/+15
2018-11-06S/390: Accept cdb in load-and-test-fp-1 testcaseIlya Leoshkevich1-1/+1
2018-11-06msp430.h (REG_CLASS_CONTENTS): Add R0 to REG_CLASS_CONTENTS[GEN_REGS].Jozef Lawrynowicz1-0/+16
2018-11-06S/390: Fix PR87723Andreas Krebbel1-0/+29
2018-11-06re PR middle-end/18041 (OR of two single-bit bitfields is inefficient)Richard Biener2-0/+27
2018-11-06avx512fintrin.h: Update VFIXUPIMM* intrinsics.Wei Xiao17-116/+143
2018-11-05S/390: Make tests expect column numbers in RTL outputIlya Leoshkevich3-18/+18
2018-11-05S/390: Add loc patterns for QImode and HImodeRobin Dapp2-0/+50
2018-11-03re PR target/87079 (nios2 optimization for size - case of regression relative...Sandra Loosemore2-0/+68
2018-10-31Provide extension hint for aarch64 target (PR driver/83193).Martin Liska3-0/+38
2018-10-31re PR middle-end/70359 (Code size increase for x86/ARM/others compared to gcc...Richard Biener2-0/+35
2018-10-31[ARC] Add BI/BIH instruction support.Claudiu Zissulescu1-0/+34
2018-10-31[ARC] Cleanup TLS implementation and add a number of tests.Claudiu Zissulescu5-7/+80
2018-10-31[ARC] Remove non standard funcions calls.Claudiu Zissulescu1-3/+2
2018-10-31Fix PR87374: ICE with -mslow-flash-data and -mword-relocationsThomas Preud'homme9-0/+9
2018-10-29[rs6000] Remove inaccurate commentPaul A. Clarke1-1/+0
2018-10-26sse-addss-1.c: Call abort under DEBUG also; formatting cleanup.Bill Schmidt44-288/+243
2018-10-26[rs6000] Add tests for compatible implementations of x86 SSSE3 intrinsicsPaul A. Clarke18-0/+1692
2018-10-26[rs6000] Enable 32bit support for tests of x86-compatibile intrinsicsPaul A. Clarke250-251/+1
2018-10-25rs6000-c.c (P9V_BUILTIN_VEC_VSCEDPGT, [...]): Rename base overloaded name.Carl Love1-0/+277
2018-10-25S/390: Merge movdi_larl into movdi_64Ilya Leoshkevich7-0/+85
2018-10-24rs6000.c (TARGET_MANGLE_DECL_ASSEMBLER_NAME): Define as rs6000_mangle_decl_as...Michael Meissner2-0/+40
2018-10-24S/390: Fix ICE in s390_check_qrst_address ()Ilya Leoshkevich1-0/+32
2018-10-22S/390: Add the forgotten test for r265371Ilya Leoshkevich1-0/+12
2018-10-22i386: Enable AVX512 memory broadcast for INT andnotH.J. Lu8-0/+96
2018-10-22i386: Enable AVX512 memory broadcast for INT logicH.J. Lu27-0/+324
2018-10-22i386: Enable AVX512 memory broadcast for INT addH.J. Lu17-0/+204
2018-10-21i386: Update AVX512 FMSUB/FNMADD/FNMSUB testsH.J. Lu3-0/+30
2018-10-21i386: Enable AVX512 memory broadcast for FNMSUBH.J. Lu11-0/+132
2018-10-21i386: Enable AVX512 memory broadcast for FNMADDH.J. Lu11-0/+132
2018-10-21Enable AVX512 memory broadcast for FMSUBH.J. Lu11-0/+132
2018-10-21i386: Enable AVX512 memory broadcast for FP mulH.J. Lu9-0/+108
2018-10-21i386: Add missing AVX512VL or/xor intrinsicsH.J. Lu1-0/+76
2018-10-20i386: Enable AVX512 memory broadcast for FP divH.J. Lu8-0/+96
2018-10-19rs6000: Put CR0 first in REG_ALLOC_ORDERSegher Boessenkool2-8/+4
2018-10-19re PR tree-optimization/87657 (SLP ICE in libgfortran matmul_i2_vanilla)Richard Biener1-0/+22
2018-10-19i386: Enable AVX512 memory broadcast for FP addH.J. Lu23-0/+283
2018-10-19lra: fix spill_hard_reg_in_range clobber checkIlya Leoshkevich1-0/+16
2018-10-18i386: Enable AVX512 memory broadcast for FMAH.J. Lu19-0/+238
2018-10-18Simplify subreg of vec_merge of vec_duplicateH.J. Lu1-0/+12
2018-10-15[PR87563][AARCH64-SVE]: Don't keep ifcvt loop when COND_<OP> ifn could not be...Renlin Li1-0/+18
2018-10-14i386: Add register source to movddupH.J. Lu1-0/+12
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