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AgeCommit message (Expand)AuthorFilesLines
9 daysTurn test cases into UNSUPPORTED if running into 'sorry, unimplemented: dynam...Thomas Schwinge10-10/+0
11 daystestsuite: Fix sve/pcs/args_1.c failures [PR116604]Richard Sandiford1-15/+16
11 daystestsuite: Fix sve/var_stride_*.c failuresRichard Sandiford2-4/+2
12 daysaarch64: Fix testcase pr112105.cAndrew Pinski1-1/+1
14 dayslate-combine: Tighten register class check [PR108840]Richard Sandiford1-1/+1
2025-02-11[PR target/115478] Accept ADD, IOR or XOR when combining objects with no bits...Jeff Law1-2/+2
2025-02-11aarch64: Update fp8 dependenciesAndrew Carlotti6-10/+10
2025-02-06vect: Move induction IV increments [PR110449]Richard Sandiford1-11/+14
2025-02-05testsuite: Revert to the original version of pr100056.cRichard Sandiford1-3/+1
2025-02-03aarch64: Fix dupq_* testsuite failuresRichard Sandiford1-0/+13
2025-01-24aarch64: Add command line support for armv9.5-aAndrew Carlotti1-0/+14
2025-01-24aarch64: Make AARCH64_FL_CRYPTO always unsetAndrew Carlotti1-0/+14
2025-01-24aarch64: Improve mcpu/march conflict checkAndrew Carlotti2-0/+2
2025-01-24Fix command flags for SVE2 faminmaxSaurabh Jha3-2/+13
2025-01-23aarch64: Avoid redundant writes to FPMRRichard Sandiford8-7/+43
2025-01-23aarch64: Fix memory cost for FPM_REGNUMRichard Sandiford8-8/+24
2025-01-23aarch64: Allow FPMR source values to be zeroRichard Sandiford1-0/+47
2025-01-22aarch64: Fix aarch64_write_sysregdi predicateRichard Sandiford2-3/+16
2025-01-21AArch64: Add LUTI ACLE for SVE2Vladimir Miloserdov21-0/+1215
2025-01-21middle-end: use ncopies both when registering and reading masks [PR118273]Tamar Christina1-0/+15
2025-01-20vect: Preserve OMP info for conditional stores [PR118348]Richard Sandiford2-0/+35
2025-01-20Revert "vect: Preserve OMP info for conditional stores [PR118384]"Richard Sandiford2-35/+0
2025-01-20vect: Preserve OMP info for conditional stores [PR118384]Richard Sandiford2-0/+35
2025-01-20aarch64: Add missing simd requirements for INS [PR118531]Richard Sandiford3-0/+24
2025-01-18AArch64: Use standard names for saturating arithmeticAkram Ahmad12-16/+825
2025-01-18AArch64: Use standard names for SVE saturating arithmeticAkram Ahmad5-0/+312
2025-01-18Revert "AArch64: Use standard names for saturating arithmetic"Tamar Christina12-825/+16
2025-01-18Revert "AArch64: Use standard names for SVE saturating arithmetic"Tamar Christina5-312/+0
2025-01-17AArch64: Use standard names for SVE saturating arithmeticTamar Christina5-0/+312
2025-01-17AArch64: Use standard names for saturating arithmeticTamar Christina12-16/+825
2025-01-16AArch64: have -mcpu=native detect architecture extensions for unknown non-hom...Tamar Christina4-0/+61
2025-01-16AArch64: don't override march to assembler with mcpu if march is specified [P...Tamar Christina1-0/+11
2025-01-15AArch64: Deprecate -mabi=ilp32Wilco Dijkstra7-7/+7
2025-01-10Add new hardreg PRE passAndrew Carlotti4-0/+114
2025-01-10aarch64: Add new +rcpc2 flagAndrew Carlotti2-2/+2
2025-01-10aarch64: Add new +flagm2 flagAndrew Carlotti2-2/+2
2025-01-10aarch64: Add new +frintts flagAndrew Carlotti2-2/+2
2025-01-10aarch64: Add new +jscvt flagAndrew Carlotti2-2/+2
2025-01-10aarch64: Add new +fcma flagAndrew Carlotti5-5/+5
2025-01-10rtl: Remove invalid compare simplification [PR117186]Richard Sandiford1-0/+128
2025-01-09AArch64: Fix costing of emulated gathers/scatters [PR118188]Tamar Christina3-0/+60
2025-01-08aarch64: Fix overly restrictive sibcall check [PR107102]Richard Sandiford1-0/+80
2025-01-07AArch64: Switch off early schedulingWilco Dijkstra12-74/+13
2025-01-07AArch64: Block combine_and_move from creating FP literal loadsWilco Dijkstra2-52/+24
2025-01-07AArch64: Remove AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTSJennifer Schmitz2-2/+2
2025-01-06aarch64: remove extra XTN in vector concatenationAkram Ahmad1-0/+32
2025-01-06SVE intrinsics: Fold svmul by -1 to svneg for unsigned typesJennifer Schmitz4-13/+30
2025-01-06AArch64: Implement four and eight chunk VLA concats [PR118272]Tamar Christina1-0/+27
2025-01-02Update copyright years.Jakub Jelinek19-19/+19
2024-12-30aarch64: Add mf8 data movement intrinsicsRichard Sandiford40-38/+3123
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