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37 hoursSVE intrinsics: Add fold_active_lanes_to method to refactor svmul and svdiv.Jennifer Schmitz14-72/+342
42 hoursAArch64: support encoding integer immediates using floating point movesTamar Christina1-0/+87
42 hoursAArch64: update testsuite to account for new zero movesTamar Christina52-412/+410
5 daysSVE intrinsics: Fold svmul with constant power-of-2 operand to svlslJennifer Schmitz9-242/+2577
6 dayssimplify-rtx: Fix incorrect folding of shift and AND [PR117012]Tamar Christina1-0/+16
6 daysAArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]Tamar Christina16-694/+694
6 daysaarch64: Fix folding of degenerate svwhilele case [PR117045]Richard Sandiford3-1/+66
9 daysaarch64: Add codegen support for SVE2 faminmaxSaurabh Jha2-0/+104
9 daysaarch64: Add SVE2 faminmax intrinsicsSaurabh Jha6-0/+2586
9 daysaarch64: Alter pr116258.c test to correct for big endian.Richard Ball1-1/+2
11 daysaarch64: Fix SVE ACLE gimple folds for C++ LTO [PR116629]Richard Sandiford1-0/+381
11 daystree-optimization/116024 - simplify some cases of X +- C1 cmp C2Artemiy Volkov1-1/+1
12 daysaarch64: Expand CTZ to RBIT + CLZ for SVE [PR109498]Soumya AR1-0/+49
13 daysgcc: Remove executable permissions of testcases and *.md filesJakub Jelinek6-0/+0
13 daysaarch64: Fix general permutes of svbfloat16_tsRichard Sandiford1-0/+10
13 daysaarch64: Handle SVE modes in aarch64_evpc_reencode [PR116583]Richard Sandiford4-0/+587
2024-10-04aarch64: Fix bug with max/min (PR116934)Saurabh Jha1-0/+13
2024-10-01aarch64: Add fp8 scalar typesClaudio Bantaloukas2-0/+490
2024-09-30autovectorizer: Test autovectorization of different dot-prod modes.Victor Do Nascimento1-0/+66
2024-09-30aarch64: Fix aarch64 backend-use of (u|s|us)dot_prod patternsVictor Do Nascimento1-0/+26
2024-09-23aarch64: Add codegen support for AdvSIMD faminmaxSaurabh Jha3-0/+681
2024-09-23aarch64: Add AdvSIMD faminmax intrinsicsSaurabh Jha2-0/+125
2024-09-22aarch64: Take into account when VF is higher than known scalar itersTamar Christina9-29/+66
2024-09-19SVE intrinsics: Fold svmul with all-zero operands to zero vectorJennifer Schmitz2-2/+367
2024-09-17SVE intrinsics: Fold svdiv with all-zero operands to zero vectorJennifer Schmitz2-8/+373
2024-09-16aarch64: Improve vector constant generation using SVE INDEX instruction [PR11...Pengxuan Zheng5-8/+103
2024-09-16aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for SVE instructions.Soumya AR34-93/+136
2024-09-09middle-end: also optimized `popcount(a) <= 1` [PR90693]Andrew Pinski3-0/+91
2024-09-05[AARCH64] adjust gcc.target/aarch64/sve/mask_gather_load_7.cRichard Biener1-4/+4
2024-09-03aarch64: Fix testcase vec-init-22-speed.c [PR116589]Andrew Pinski1-1/+1
2024-09-03SVE intrinsics: Fold constant operands for svmul.Jennifer Schmitz1-0/+302
2024-09-03SVE intrinsics: Fold constant operands for svdiv.Jennifer Schmitz1-0/+358
2024-08-31phiopt: Ignore some nop statements in heursics [PR116098]Andrew Pinski1-0/+28
2024-08-29expand: Allow widdening optab when expanding popcount==1 [PR116508]Andrew Pinski1-0/+45
2024-08-28aarch64: Add a test for zeroing <64bits>x2_t structuresRichard Sandiford1-0/+21
2024-08-23ifcvt: disallow call instructions in noce_convert_multiple_sets [PR116358]Manolis Tsamis1-0/+15
2024-08-22PR target/116365: Add user-friendly arguments to --param aarch64-autovec-pref...Jennifer Schmitz14-9/+29
2024-08-22PR tree-optimization/101390: Vectorize modulo operatorJennifer Schmitz1-0/+28
2024-08-21aarch64: Fix caller saves of VNx2QI [PR116238]Richard Sandiford1-0/+13
2024-08-21aarch64: Implement popcountti2 pattern [PR113042]Andrew Pinski2-0/+50
2024-08-19aarch64: Fix ls64 intrinsic availabilityAndrew Carlotti4-0/+38
2024-08-19aarch64: Fix memtag intrinsic availabilityAndrew Carlotti4-0/+38
2024-08-19aarch64: Fix tme intrinsic availabilityAndrew Carlotti4-0/+38
2024-08-15aarch64: Improve popcount for bytes [PR113042]Andrew Pinski4-0/+74
2024-08-15aarch64: Rename svpext to svpext_lane [PR116371]Richard Sandiford16-416/+416
2024-08-12ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_setsManolis Tsamis1-0/+20
2024-08-12ifcvt: Allow more operations in multiple set if conversionManolis Tsamis1-0/+79
2024-08-12aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for Advanced SIMDKyrylo Tkachov1-0/+64
2024-08-08aarch64/testsuite: Fix if-compare_2.c for removing vcond{,u,eq} patterns [PR1...Andrew Pinski1-2/+7
2024-08-08AArch64: Fix signbit mask creation after late combine [PR116229]Tamar Christina1-0/+20