| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-12-14 | [PATCH v3] match.pd: Add pattern to simplify `(a - 1) & -a` to `0` | Jovan Vukic | 1 | -0/+41 |
| 2024-11-30 | [PATCH v3] zero_extend(not) -> xor optimization [PR112398] | Alexey Merzlyakov | 1 | -0/+23 |
| 2024-11-14 | Revert "Reapply "[PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR1... | Jeff Law | 1 | -22/+0 |
| 2024-11-12 | Reapply "[PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR112398]" | Jeff Law | 1 | -0/+22 |
| 2024-11-12 | Revert "[PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR112398]" | Jeff Law | 1 | -22/+0 |
| 2024-11-06 | [PATCH v2] RISC-V: zero_extend(not) -> xor optimization [PR112398] | Alexey Merzlyakov | 1 | -0/+22 |
| 2024-11-04 | PR 117048: simplify-rtx: Simplify (X << C1) [+,^] (X >> C2) into ROTATE | Kyrylo Tkachov | 1 | -48/+156 |
| 2024-11-04 | Revert "PR 117048: simplify-rtx: Simplify (X << C1) [+,^] (X >> C2) into ROTATE" | Kyrylo Tkachov | 1 | -156/+48 |
| 2024-11-04 | simplify-rtx: Simplify ROTATE:HI (X:HI, 8) into BSWAP:HI (X) | Kyrylo Tkachov | 1 | -0/+8 |
| 2024-11-04 | PR 117048: simplify-rtx: Simplify (X << C1) [+,^] (X >> C2) into ROTATE | Kyrylo Tkachov | 1 | -48/+156 |
| 2024-10-25 | simplify-rtx: Handle `a != 0 ? -a : 0` [PR58195] | Andrew Pinski | 1 | -0/+22 |
| 2024-10-25 | gcc: Remove trailing whitespace | Jakub Jelinek | 1 | -8/+8 |
| 2024-10-14 | simplify-rtx: Fix incorrect folding of shift and AND [PR117012] | Tamar Christina | 1 | -2/+2 |
| 2024-10-11 | PR 117048: simplify-rtx: Extend (x << C1) | (X >> C2) --> ROTATE transformati... | Kyrylo Tkachov | 1 | -6/+10 |
| 2024-09-29 | [PATCH v2] RISC-V: Improve code generation for select of consecutive constants | Jovan Vukic | 1 | -0/+12 |
| 2024-07-31 | [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug | Jeff Law | 1 | -2/+3 |
| 2024-07-19 | Treat boolean vector elements as 0/-1 [PR115406] | Richard Sandiford | 1 | -1/+2 |
| 2024-06-13 | aarch64: Fix invalid nested subregs [PR115464] | Richard Sandiford | 1 | -0/+5 |
| 2024-06-12 | Fix ICE in rtl check due to CONST_WIDE_INT in CONST_VECTOR_DUPLICATE_P | liuhongt | 1 | -2/+4 |
| 2024-06-06 | Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode. | liuhongt | 1 | -0/+25 |
| 2024-06-05 | Don't simplify NAN/INF or out-of-range constant for FIX/UNSIGNED_FIX. | liuhongt | 1 | -4/+19 |
| 2024-05-25 | [committed] [v2] More logical op simplifications in simplify-rtx.cc | Jeff Law | 1 | -0/+29 |
| 2024-05-09 | Constant fold {-1,-1} << 1 in simplify-rtx.cc | Roger Sayle | 1 | -0/+54 |
| 2024-03-04 | PR target/114187: Fix ?Fmode SUBREG simplification in simplify_subreg. | Roger Sayle | 1 | -1/+1 |
| 2024-01-31 | simplify-rtx: Fix up last argument to simplify_gen_unary [PR113656] | Jakub Jelinek | 1 | -1/+1 |
| 2024-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2023-11-17 | Only allow (copysign x, NEG_CONST) -> (fneg (fabs x)) simplification for cons... | Andrew Pinski | 1 | -1/+1 |
| 2023-11-13 | Fix (fcopysign x, NEGATIVE_CONST) -> (fneg (fabs x)) simplification [PR112483] | Xi Ruoyao | 1 | -1/+1 |
| 2023-10-11 | Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI x 1). | Roger Sayle | 1 | -0/+17 |
| 2023-10-02 | Fix profiledbootstrap poly_int fallout [PR111642] | Richard Sandiford | 1 | -0/+1 |
| 2023-09-20 | RISC-V: Support simplifying x/(-1) to neg for vector. | Yanzhang Wang | 1 | -2/+2 |
| 2023-08-16 | [PATCH] RISC-V: Support simplify (-1-x) for vector. | Yanzhang Wang | 1 | -1/+1 |
| 2023-07-05 | Change MODE_BITSIZE to MODE_PRECISION for MODE_VECTOR_BOOL. | Robin Dapp | 1 | -5/+5 |
| 2023-06-23 | Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg. | Roger Sayle | 1 | -0/+32 |
| 2023-06-19 | Do not allow "x + 0.0" to "x" optimization with -fsignaling-nans | Toru Kisuki | 1 | -1/+2 |
| 2023-06-19 | simplify-rtx: Simplify VEC_CONCAT of SUBREG and VEC_CONCAT from same vector | Kyrylo Tkachov | 1 | -0/+11 |
| 2023-06-12 | simplify-rtx: Implement constant folding of SS_TRUNCATE, US_TRUNCATE | Kyrylo Tkachov | 1 | -0/+14 |
| 2023-06-07 | Add RTX codes for BITREVERSE and COPYSIGN. | Roger Sayle | 1 | -2/+47 |
| 2023-05-31 | Refactor wi::bswap as a function (instead of a method). | Roger Sayle | 1 | -1/+1 |
| 2023-05-30 | Replace a HWI_COMPUTABLE_MODE_P with wide-int in simplify-rtx.cc. | Roger Sayle | 1 | -7/+8 |
| 2023-05-30 | PR target/107172: Avoid "unusual" MODE_CC comparisons in simplify-rtx.cc | Roger Sayle | 1 | -0/+6 |
| 2023-04-19 | RISC-V: Align IOR optimization MODE_CLASS condition to AND. | Pan Li | 1 | -2/+2 |
| 2023-04-17 | RISC-V: Optimze the reverse conditions of rotate shift | Feng Wang | 1 | -8/+41 |
| 2023-04-14 | combine: Fix AND handling for WORD_REGISTER_OPERATIONS targets [PR109040] | Jakub Jelinek | 1 | -1/+7 |
| 2023-03-02 | simplify-rtx: Use byte in simplify_subreg rather than assume 0 offset | Andre Vieira | 1 | -5/+5 |
| 2023-02-27 | Fix RTL simplifications of FFS, POPCOUNT and PARITY. | Roger Sayle | 1 | -7/+22 |
| 2023-02-17 | simplify-rtx: Fix VOIDmode operand handling in simplify_subreg [PR108805] | Uros Bizjak | 1 | -1/+1 |
| 2023-02-02 | arm: Remove unnecessary zero-extending of MVE predicates before use [PR 107674] | Andre Vieira | 1 | -0/+16 |
| 2023-01-02 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2022-08-22 | middle-end: Fix issue of poly_uint16 (1, 1) in self test | zhongjuzhe | 1 | -1/+1 |
