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AgeCommit message (Expand)AuthorFilesLines
2022-09-28Add instruction level discriminator support.Eugene Rozenfeld1-0/+1
2022-07-20Remove unused remove_node_from_expr_listAlexander Monakov1-1/+0
2022-04-12libgccjit: Add support for register variables [PR104072]Antoni Boucher1-0/+1
2022-01-19ifcvt/optabs: Allow using a CC comparison for emit_conditional_move.Robin Dapp1-1/+10
2022-01-17Change references of .c files to .cc filesMartin Liska1-73/+73
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-01simplify-rtx: Punt on simplify_associative_operation with large operands [PR1...Jakub Jelinek1-0/+8
2021-11-01middle-end: Teach CSE to be able to do vector extracts.Tamar Christina1-0/+7
2021-08-17aarch64: Replace some uses of GET_CODE with RTL predicate macrosAlistair Lee1-0/+3
2021-07-30Add QI vector mode support to by-pieces for memsetH.J. Lu1-0/+2
2021-07-20Adjust by-value function vec arguments to by-reference.Martin Sebor1-2/+2
2021-07-13gcc: Add vec_select -> subreg RTL simplificationJonathan Wright1-0/+1
2021-06-07CALL_INSN may not be a real function call.liuhongt1-0/+5
2021-05-12middle-end/100547 - check rtvec_alloc sizeRichard Biener1-1/+1
2021-05-04Remove CC0Segher Boessenkool1-5/+0
2021-04-14Check for matching CONST_VECTOR encodings [PR99929]Richard Sandiford1-0/+17
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-17rtlanal: Add simple_regno_setRichard Sandiford1-0/+1
2020-12-17simplify-rtx: Put simplify routines into a classRichard Sandiford1-18/+131
2020-12-17recog: Split out a register_asm_p functionRichard Sandiford1-0/+1
2020-10-22Extend special_memory_constraint.liuhongt1-0/+1
2020-05-31Fix execute/20071219-1.c regression on H8 due to loss of REG_INC notes in pee...Jeff Law1-0/+1
2020-05-08csa: Fix --enable-checking=yes,df bootstrap failure in csa [PR94961]Jakub Jelinek1-1/+1
2020-04-02cselib: Reuse VALUEs on sp adjustments [PR92264]Jakub Jelinek1-0/+1
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-25Convert m68k to not use cc0Bernd Schmidt1-1/+0
2019-10-01Remove clobber_highRichard Sandiford1-12/+1
2019-09-30Pass an ABI to choose_hard_reg_modeRichard Sandiford1-1/+4
2019-09-30Add a function for getting the ABI of a call insn targetRichard Sandiford1-6/+4
2019-09-30Introduce rtx_alloca, alloca_raw_REG and alloca_rtx_fmt_*Ilya Leoshkevich1-0/+12
2019-09-19Rework constant subreg folds and handle more variable-length casesRichard Sandiford1-1/+19
2019-09-10Make get_call_rtx_from take a const rtx_insn *Richard Sandiford1-1/+1
2019-09-09Make note_stores take an rtx_insnRichard Sandiford1-2/+11
2019-09-09Simplify the implementation of HARD_REG_SETRichard Sandiford1-2/+1
2019-08-13Adjust placement of protoype for tablejump_casesi_patternOlivier Hainque1-1/+1
2019-08-13Handle casesi dispatch tablejumps in create_trace_edges (as well)Olivier Hainque1-0/+1
2019-07-09PR c++/61339 - add mismatch between struct and class [-Wmismatched-tags] to n...Martin Sebor1-4/+4
2019-07-09PR c++/61339 - add mismatch between struct and class [-Wmismatched-tags] to n...Martin Sebor1-17/+21
2019-07-08emit-rtl.c (set_insn_locations): New function moved from...Eric Botcazou1-0/+1
2019-05-29rtl.h (LABEL_REF_P): New #define.Michael Meissner1-0/+4
2019-03-30re PR rtl-optimization/89862 (LTO bootstrap fails for ARM)Kugan Vivekanandarajah1-0/+1
2019-03-28rtl.h (NONDEBUG_INSN_P): Define as NONJUMP_INSN_P or JUMP_P or CALL_P instead...Jakub Jelinek1-3/+2
2019-01-24re PR rtl-optimization/88948 (ICE in elimination_costs_in_insn, at reload1.c:...Uros Bizjak1-0/+3
2019-01-09PR other/16615 [1/5]Sandra Loosemore1-1/+1
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-11-27Come up with memop_ret enum instead of int endp for memory operations.Martin Liska1-1/+16
2018-11-20S/390: Skip LT(G) peephole when literal pool is involvedIlya Leoshkevich1-0/+1
2018-11-20re PR rtl-optimization/85925 (compilation of masking with 257 goes wrong in c...Eric Botcazou1-0/+19
2018-08-16expmed.h (canonicalize_comparison): New declaration.Vlad Lazar1-0/+9
2018-08-06Add func to check if register is clobbered by clobber_highAlan Hayward1-0/+10
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