aboutsummaryrefslogtreecommitdiff
path: root/gcc/ira-lives.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-22[PR99581] Define relaxed memory and use it for aarch64Vladimir N. Makarov1-0/+1
2021-03-09IRA: Process digital constraints containing more one digitVladimir N. Makarov1-45/+53
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-01-28Fix for PR93272 - LRA: EH reg allocated to hold local variableVladimir N. Makarov1-0/+48
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-10-07[IRA] Handle fully-tied destinations in a similar way to earlyclobbersRichard Sandiford1-14/+72
2019-09-30Remove global call sets: IRARichard Sandiford1-13/+11
2019-09-30Add a function for getting the ABI of a call insn targetRichard Sandiford1-4/+6
2019-09-10Add call_used_or_fixed_reg_pRichard Sandiford1-1/+1
2019-09-10Replace call_used_reg_set with call_used_or_fixed_regsRichard Sandiford1-1/+1
2019-09-09Remove AND_COMPL_HARD_REG_SETRichard Sandiford1-2/+1
2019-09-09Remove IOR_HARD_REG_SETRichard Sandiford1-12/+10
2019-07-01Use ira_setup_alts for conflict detectionRichard Sandiford1-5/+4
2019-05-22re PR middle-end/90553 (Register allocation allocates post-incremented addres...Hans-Peter Nilsson1-5/+11
2019-04-18re PR rtl-optimization/87871 (testcases fail after r265398 on arm)Peter Bergner1-10/+12
2019-01-09PR other/16615 [1/5]Sandra Loosemore1-1/+1
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-11-19re PR rtl-optimization/88033 (ICE on valid code at -O2 and -O3 on x86-64-linu...Peter Bergner1-2/+8
2018-10-12re PR rtl-optimization/87600 (Fix for PRs 86939 and 87479 causes build issues...Peter Bergner1-0/+5
2018-10-05re PR rtl-optimization/86939 (IRA incorrectly creates an interference between...Peter Bergner1-28/+69
2018-10-04re PR rtl-optimization/87466 (IRA and LRA spill all pseudos that are live acr...Peter Bergner1-2/+3
2018-09-30re PR rtl-optimization/86939 (IRA incorrectly creates an interference between...Peter Bergner1-30/+28
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
2017-12-20poly_int: SUBREG_BYTERichard Sandiford1-1/+1
2017-08-30Drop df_ from df_read_modify_subreg_pRichard Sandiford1-3/+3
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
2016-10-13Move MEMMODEL_* from coretypes.h to memmodel.hThomas Preud'homme1-0/+1
2016-07-26use auto_sbitmap in various placesTrevor Saunders1-7/+4
2016-07-01strcpy arg optimised outAlan Modra1-1/+1
2016-01-29re PR target/69299 (-mavx performance degradation with r232088)Vladimir Makarov1-0/+1
2016-01-04Update copyright years.Jakub Jelinek1-1/+1
2015-10-30alias.c: Remove unused headers.Andrew MacLeod1-5/+0
2015-10-29alias.c: Reorder #include statements and remove duplicates.Andrew MacLeod1-8/+7
2015-08-13ira-int.h: Include recog.h.Andrew MacLeod1-1/+0
2015-08-07Add alternative_mask to ira_implicitly_set_insn_hard_regsH.J. Lu1-2/+2
2015-07-11re PR middle-end/66353 (Missing bb_has_abnormal_call_pred in basic-block.h)Marek Polacek1-17/+2
2015-07-10gimple-predict.h: New file.Andrew MacLeod1-0/+1
2015-07-08re PR target/66334 (cleanup block fails to initialize EBX)Vladimir Makarov1-1/+15
2015-07-08tree-core.h: Include symtab.h.Andrew MacLeod1-8/+6
2015-06-17coretypes.h: Include input.h and as-a.h.Andrew MacLeod1-1/+0
2015-06-08coretypes.h: Include hash-table.h and hash-set.h for host files.Andrew MacLeod1-3/+0
2015-06-04coretypes.h: Include machmode.h...Andrew MacLeod1-1/+0
2015-05-19rtl.h (REG_NREGS): New macroRichard Sandiford1-1/+1
2015-05-19cfgcleanup.c (mentions_nonequal_regs): Use END_REGNO.Richard Sandiford1-1/+1
2015-04-22add default definition of EH_RETURN_DATA_REGNOTrevor Saunders1-2/+0
2015-01-05Update copyright years.Jakub Jelinek1-1/+1
2014-11-25ira-lives.c (process_bb_node_lives): Make code with conditional REAL_PIC_OFFS...Vladimir Makarov1-4/+7
2014-11-25re PR target/63527 (-fPIC uses 2 registers for GOT)Vladimir Makarov1-4/+31
2014-10-29decl.c, [...]: Remove redundant enum from machine_mode.Richard Sandiford1-2/+2
2014-10-27ggcplug.c: Shuffle includes to include gcc-plugin.h earlier.Andrew MacLeod1-0/+7
generated by cgit v1.1 at 2024-08-18 01:40:50 +0000