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2024-04-23Remove repeated information in -ftree-loop-distribute-patterns docJan Hubicka1-2/+0
We have: -ftree-loop-distribute-patterns Perform loop distribution of patterns that can be code generated with calls to a library. This flag is enabled by default at -O2 and higher, and by -fprofile-use and -fauto-profile. This pass distributes the initialization loops and generates a call to memset zero. For example, the loop ... and the initialization loop is transformed into a call to memset zero. This flag is enabled by default at -O3. It is also enabled by -fprofile-use and -fauto-profile. Which mentions optimizatoin flags twice and the repeated mention is out of date, since we enable this option at -O2 as well. gcc/ChangeLog: * doc/invoke.texi (-ftree-loop-distribute-patterns): Remove duplicated sentence about optimization flags implying this.
2024-04-23LoongArch: Define ISA versionsYang Yujie1-20/+37
These ISA versions are defined as -march= parameters and are recommended for building binaries for distribution. Detailed description of these definitions can be found at https://github.com/loongson/la-toolchain-conventions, which the LoongArch GCC port aims to conform to. gcc/ChangeLog: * config.gcc: Make la64v1.0 the default ISA preset of the lp64d ABI. * config/loongarch/genopts/loongarch-strings: Define la64v1.0, la64v1.1. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-c.cc (LARCH_CPP_SET_PROCESSOR): Likewise. (loongarch_cpu_cpp_builtins): Likewise. * config/loongarch/loongarch-cpu.cc (get_native_prid): Likewise. (fill_native_cpu_config): Likewise. * config/loongarch/loongarch-def.cc (array_tune): Likewise. * config/loongarch/loongarch-def.h: Likewise. * config/loongarch/loongarch-driver.cc (driver_set_m_parm): Likewise. (driver_get_normalized_m_opts): Likewise. * config/loongarch/loongarch-opts.cc (default_tune_for_arch): Likewise. (TUNE_FOR_ARCH): Likewise. (arch_str): Likewise. (loongarch_target_option_override): Likewise. * config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Likewise. (TARGET_uARCH_LA664): Likewise. * config/loongarch/loongarch-str.h (STR_CPU_ABI_DEFAULT): Likewise. (STR_ARCH_ABI_DEFAULT): Likewise. (STR_TUNE_GENERIC): Likewise. (STR_ARCH_LA64V1_0): Likewise. (STR_ARCH_LA64V1_1): Likewise. * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Likewise. (loongarch_asm_code_end): Likewise. * config/loongarch/loongarch.opt: Likewise. * doc/invoke.texi: Likewise.
2024-04-18[testsuite] introduce strndup effective targetAlexandre Oliva1-0/+3
A number of tests that call strndup fail on vxworks, where there's no strndup. Some of them already had workarounds to skip the strndup parts of the tests on platforms that don't offer it. I've changed them to rely on a strndup effective target instead, and extended the logic to other tests that were otherwise skipped entirely. for gcc/ChangeLog * doc/sourcebuild.texi (strndup): Add effective target. for gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_strndup): New. * gcc.dg/builtin-dynamic-object-size-0.c: Skip strndup tests when the function is not available. * gcc.dg/builtin-dynamic-object-size-1.c: Likewise. * gcc.dg/builtin-dynamic-object-size-2.c: Likewise. * gcc.dg/builtin-dynamic-object-size-3.c: Likewise. * gcc.dg/builtin-dynamic-object-size-4.c: Likewise. * gcc.dg/builtin-object-size-1.c: Likewise. * gcc.dg/builtin-object-size-2.c: Likewise. * gcc.dg/builtin-object-size-3.c: Likewise. * gcc.dg/builtin-object-size-4.c: Likewise.
2024-04-16Document that vector_size works with typedefs [PR92880]Andrew Pinski1-6/+7
This just adds a clause to make it more obvious that the vector_size attribute extension works with typedefs. Note this whole section needs a rewrite to be a similar format as other extensions. But that is for another day. gcc/ChangeLog: PR c/92880 * doc/extend.texi (Using Vector Instructions): Add that the base_types could be a typedef of them. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-04-16LoongArch: Add indexes for some compilation options.Lulu Cheng1-1/+6
gcc/ChangeLog: * config/loongarch/loongarch.opt.urls: Regenerate. * config/mn10300/mn10300.opt.urls: Likewise. * config/msp430/msp430.opt.urls: Likewise. * config/nds32/nds32-elf.opt.urls: Likewise. * config/nds32/nds32-linux.opt.urls: Likewise. * config/nds32/nds32.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rx/rx.opt.urls: Likewise. * config/sh/sh.opt.urls: Likewise. * config/sparc/sparc.opt.urls: Likewise. * doc/invoke.texi: Add indexes for some compilation options.
2024-04-15AVR: Add 8 more avrxmega3 MCUs.Georg-Johann Lay1-1/+1
gcc/ * config/avr/avr-mcus.def: Add: avr16du14, avr16du20, avr16du28, avr16du32, avr32du14, avr32du20, avr32du28, avr32du32. * doc/avr-mmcu.texi: Rebuild.
2024-04-12c++: reference cast, conversion fn [PR113141]Jason Merrill1-0/+13
The second testcase in 113141 is a separate issue: we first decide that the conversion is ill-formed, but then when recalculating the special c_cast_p handling makes us think it's OK. We don't want that, it should continue to fall back to the reinterpret_cast interpretation. And while we're here, let's warn that we're not using the conversion function. Note that the standard seems to say that in this case we should treat (Matrix &) as const_cast<Matrix &>(static_cast<const Matrix &>(X)), which would use the conversion operator, but that doesn't match existing practice, so let's resolve that another day. I've raised this issue with CWG; at the moment I lean toward never binding a temporary in a C-style cast to reference type, which would also be a change from existing practice. PR c++/113141 gcc/c-family/ChangeLog: * c.opt: Add -Wcast-user-defined. gcc/ChangeLog: * doc/invoke.texi: Document -Wcast-user-defined. gcc/cp/ChangeLog: * call.cc (reference_binding): For an invalid cast, warn and don't recalculate. gcc/testsuite/ChangeLog: * g++.dg/conversion/ref12.C: New test. Co-authored-by: Patrick Palka <ppalka@redhat.com>
2024-04-11modula2: add modula-2 language section to languages supported by GCCGaius Mulley1-0/+11
This patch introduces a small modula-2 language section to the Language Standards Supported by GCC node. gcc/ChangeLog: * doc/standards.texi (Language Standards Supported by GCC): Add Modula-2 language section. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-10analyzer: fixes to internal docsDavid Malcolm1-2/+8
gcc/ChangeLog: * doc/analyzer.texi: Various tweaks. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-04-09modula2: remove description of fdebug-trace-quad, fdebug-trace-api and add ↵Gaius Mulley1-8/+5
fm2-debug-trace= This documentation fix removes the descriptions of -fdebug-trace-quad and -fdebug-trace-api. It adds a description of -fm2-debug-trace= together with the trace alternatives: line,token,quad,all. gcc/ChangeLog: * doc/gm2.texi (Compiler options): Remove -fdebug-trace-quad. Remove -fdebug-trace-api. Add -fm2-debug-trace=. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-09Fix up duplicated words mostly in comments, part 2Jakub Jelinek2-5/+5
Another patch from eyeballing git grep -v 'long long\|optab optab\|template template\|double double' | grep ' \([a-zA-Z]\+\) \1 ' output, this time in gcc/ subdirectory. 2024-04-09 Jakub Jelinek <jakub@redhat.com> gcc/ * expr.cc (convert_mode_scalar): Fix duplicated words in comment; into into -> it into. * function.h (function::cond_uids): Fix duplicated words in comment; same same -> same. * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): Fix duplicated words in comment; model model -> model. * config/riscv/riscv-vector-builtins-shapes.cc (build_base): Fix duplicated words in comment; for for -> for. * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Fix duplicated words in comment; more more -> more. * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Fix duplicated words in comment; be be -> be. * tree-profile.cc (masking_vectors): Fix duplicated words in comment; has has -> has, the the -> the. * value-range.cc (irange::set_range_from_bitmask): Fix duplicated words in comment; the the -> the. * gcov.cc (add_condition_counts): Fix duplicated words in comment; to to -> to. * vr-values.cc (get_scev_info): Fix duplicated words in comment; the the -> to the. * tree-vrp.cc (fully_replaceable): Fix duplicated words in comment; by by -> by. * mode-switching.cc (single_succ_confluence_n): Fix duplicated words in comment; the the -> the. * tree-ssa-phiopt.cc (value_replacement): Fix duplicated words in comment; can can -> we can. * gimple-range-phi.cc (phi_analyzer::process_phi): Fix duplicated words in comment; it it -> it is. * tree-ssa-sccvn.cc (visit_phi): Fix duplicated words in comment; to to -> to. * rtl-ssa/accesses.h (use_info::next_debug_insn_use): Fix duplicated words in comment; if if -> if. * doc/options.texi (InverseMask): Fix duplicated words; and and -> and. Change take to takes. * doc/invoke.texi (fanalyzer-undo-inlining): Fix duplicated words; be be -> be. (-minline-memops-threshold): Likewise. gcc/analyzer/ * analyzer.opt (Wanalyzer-undefined-behavior-strtok): Fix duplicated words; in in -> in. * program-state.cc (sm_state_map::replay_call_summary): Fix duplicated words in comment; to to -> to. (program_state::replay_call_summary): Likewise. * region-model.cc (region_model::replay_call_summary): Likewise. gcc/c/ * c-decl.cc (previous_tag): Fix duplicated words in comment; the the -> the. (diagnose_mismatched_decls): Fix duplicated words in comment; about about -> about. gcc/cp/ * constexpr.cc (build_new_constexpr_heap_type): Fix duplicated words in comment; is is -> is. * cp-tree.def (CO_RETURN_EXPR): Fix duplicated words in comment; for for -> for. * parser.cc (fixup_blocks_walker): Fix duplicated words in comment; is is -> is. * semantics.cc (fixup_template_type): Fix duplicated words in comment; for for -> for. (finish_omp_for): Fix duplicated words in comment; the the -> the. * pt.cc (more_specialized_fn): Fix duplicated words in comment; think think -> think. (type_targs_deducible_from): Fix duplicated words in comment; the the -> the. gcc/jit/ * docs/topics/expressions.rst (Constructor expressions): Fix duplicated words; have have -> have.
2024-04-08GCN: '--param=gcn-preferred-vectorization-factor=[default,32,64]'Thomas Schwinge1-0/+8
..., and specify '--param=gcn-preferred-vectorization-factor=64' for 'gcc.target/gcn/[...]' test cases with 'scan-assembler' directives that are specific to 64-lane vectors. This resolves regressions introduced in commit 6dedafe166cc02ae87b6a0699ad61ce3ffc46803 "amdgcn: Prefer V32 on RDNA devices". gcc/ * config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor): New. * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it. * doc/invoke.texi (Optimize Options): Document it. gcc/testsuite/ * gcc.target/gcn/cond_fmaxnm_1.c: Specify '--param=gcn-preferred-vectorization-factor=64'. * gcc.target/gcn/cond_fmaxnm_2.c: Likewise. * gcc.target/gcn/cond_fmaxnm_3.c: Likewise. * gcc.target/gcn/cond_fmaxnm_4.c: Likewise. * gcc.target/gcn/cond_fmaxnm_5.c: Likewise. * gcc.target/gcn/cond_fmaxnm_6.c: Likewise. * gcc.target/gcn/cond_fmaxnm_7.c: Likewise. * gcc.target/gcn/cond_fmaxnm_8.c: Likewise. * gcc.target/gcn/cond_fminnm_1.c: Likewise. * gcc.target/gcn/cond_fminnm_2.c: Likewise. * gcc.target/gcn/cond_fminnm_3.c: Likewise. * gcc.target/gcn/cond_fminnm_4.c: Likewise. * gcc.target/gcn/cond_fminnm_5.c: Likewise. * gcc.target/gcn/cond_fminnm_6.c: Likewise. * gcc.target/gcn/cond_fminnm_7.c: Likewise. * gcc.target/gcn/cond_fminnm_8.c: Likewise. * gcc.target/gcn/cond_shift_3.c: Likewise. * gcc.target/gcn/cond_shift_4.c: Likewise. * gcc.target/gcn/cond_shift_8.c: Likewise. * gcc.target/gcn/cond_shift_9.c: Likewise. * gcc.target/gcn/cond_smax_1.c: Likewise. * gcc.target/gcn/cond_smin_1.c: Likewise. * gcc.target/gcn/cond_umax_1.c: Likewise. * gcc.target/gcn/cond_umin_1.c: Likewise. * gcc.target/gcn/simd-math-1.c: Likewise. * gcc.target/gcn/simd-math-5-char.c: Likewise. * gcc.target/gcn/simd-math-5-long.c: Likewise. * gcc.target/gcn/simd-math-5-short.c: Likewise. * gcc.target/gcn/simd-math-5.c: Likewise. * gcc.target/gcn/smax_1.c: Likewise. * gcc.target/gcn/smin_1.c: Likewise. * gcc.target/gcn/umax_1.c: Likewise. * gcc.target/gcn/umin_1.c: Likewise.
2024-04-08New effective-target 'asm_goto_with_outputs'Thomas Schwinge1-0/+6
After commit e16f90be2dc8af6c371fe79044c3e668fa3dda62 "testsuite: Fix up lra effective target", we get for nvptx target: -PASS: gcc.c-torture/compile/asmgoto-2.c -O0 (test for excess errors) +ERROR: gcc.c-torture/compile/asmgoto-2.c -O0 : no files matched glob pattern "lra1020113.c.[0-9][0-9][0-9]r.reload" for " dg-do 2 compile { target lra } " Etc. However, nvptx appears to support 'asm goto' with outputs, including the new execution test case: PASS: gcc.dg/pr107385.c execution test Therefore, generally use new effective-target 'asm_goto_with_outputs' instead of 'lra'. One exceptions is 'gcc.dg/pr110079.c', which doesn't use 'asm goto' with outputs, and continues using effective-target 'lra', with special-casing nvptx target, to avoid ERROR for 'lra'. gcc/ * doc/sourcebuild.texi (Effective-Target Keywords): Document 'asm_goto_with_outputs'. Add comment to 'lra'. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_lra): Add comment. (check_effective_target_asm_goto_with_outputs): New. * gcc.c-torture/compile/asmgoto-2.c: Use it. * gcc.c-torture/compile/asmgoto-5.c: Likewise. * gcc.c-torture/compile/asmgoto-6.c: Likewise. * gcc.c-torture/compile/pr98096.c: Likewise. * gcc.dg/pr100590.c: Likewise. * gcc.dg/pr107385.c: Likewise. * gcc.dg/pr108095.c: Likewise. * gcc.dg/pr97954.c: Likewise. * gcc.dg/torture/pr100329.c: Likewise. * gcc.dg/torture/pr100398.c: Likewise. * gcc.dg/torture/pr100519.c: Likewise. * gcc.dg/torture/pr110422.c: Likewise. * gcc.dg/pr110079.c: Special-case nvptx target.
2024-04-08RISC-V: Implement TLS Descriptors.Tatsuyuki Ishi2-1/+15
This implements TLS Descriptors (TLSDESC) as specified in [1]. The 4-instruction sequence is implemented as a single RTX insn for simplicity, but this can be revisited later if instruction scheduling or more flexible RA is desired. The default remains to be the traditional TLS model, but can be configured with --with-tls={trad,desc}. The choice can be revisited once toolchain and libc support ships. [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373. gcc/ChangeLog: * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor. * config.gcc: Add --with-tls configuration option to change the default TLS flavor. * config/riscv/riscv.h: Add TARGET_TLSDESC determined from -mtls-dialect and with_tls defaults. * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the two TLS flavors. * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type. * config/riscv/riscv.md: Add instruction sequence for TLSDESC. * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction sequence length data for TLSDESC. (riscv_legitimize_tls_address): Add lowering of TLSDESC. * doc/install.texi: Document --with-tls for RISC-V. * doc/invoke.texi: Document -mtls-dialect for RISC-V. gcc/testsuite/ChangeLog: * gcc.target/riscv/tls_1.x: Add TLSDESC GD test case. * gcc.target/riscv/tlsdesc.c: Same as above.
2024-04-05analyzer: respect GCC_COLORS in out-of-bounds diagrams [PR114588]David Malcolm1-1/+9
gcc/analyzer/ChangeLog: PR analyzer/114588 * access-diagram.cc (access_diagram_impl::access_diagram_impl): Replace hardcoded colors for valid_style and invalid_style with calls to text_art::get_style_from_color_cap_name. gcc/ChangeLog: PR analyzer/114588 * diagnostic-color.cc (color_dict): Add "valid" and "invalid" as color capability names. * doc/invoke.texi: Document them in description of GCC_COLORS. * text-art/style.cc: Include "diagnostic-color.h". (text_art::get_style_from_color_cap_name): New. * text-art/types.h (get_style_from_color_cap_name): New decl. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-04-04Add condition coverage (MC/DC)Jørgen Kvalsvik2-0/+59
This patch adds support in gcc+gcov for modified condition/decision coverage (MC/DC) with the -fcondition-coverage flag. MC/DC is a type of test/code coverage and it is particularly important for safety-critical applicaitons in industries like aviation and automotive. Notably, MC/DC is required or recommended by: * DO-178C for the most critical software (Level A) in avionics. * IEC 61508 for SIL 4. * ISO 26262-6 for ASIL D. From the SQLite webpage: Two methods of measuring test coverage were described above: "statement" and "branch" coverage. There are many other test coverage metrics besides these two. Another popular metric is "Modified Condition/Decision Coverage" or MC/DC. Wikipedia defines MC/DC as follows: * Each decision tries every possible outcome. * Each condition in a decision takes on every possible outcome. * Each entry and exit point is invoked. * Each condition in a decision is shown to independently affect the outcome of the decision. In the C programming language where && and || are "short-circuit" operators, MC/DC and branch coverage are very nearly the same thing. The primary difference is in boolean vector tests. One can test for any of several bits in bit-vector and still obtain 100% branch test coverage even though the second element of MC/DC - the requirement that each condition in a decision take on every possible outcome - might not be satisfied. https://sqlite.org/testing.html#mcdc MC/DC comes in different flavors, the most important being unique cause MC/DC and masking MC/DC. This patch implements masking MC/DC, which is works well with short circuiting semantics, and according to John Chilenski's "An Investigation of Three Forms of the Modified Condition Decision Coverage (MCDC) Criterion" (2001) is as good as unique cause at catching bugs. Whalen, Heimdahl, and De Silva "Efficient Test Coverage Measurement for MC/DC" describes an algorithm for finding the masking table from an AST walk, but my algorithm figures this out by analyzing the control flow graph. The CFG is considered a reduced ordered binary decision diagram and an input vector a path through the BDD, which is recorded. Specific edges will mask ("null out") the contribution from earlier path segments, which can be determined by finding short circuit endpoints. Masking is most easily understood as circuiting of terms in the reverse-ordered Boolean function, and the masked conditions do not affect the decision like short-circuited conditions do not affect the decision. A tag/discriminator mapping from gcond->uid is created during gimplification and made available through the function struct. The values are unimportant as long as basic conditions constructed from a single Boolean expression are given the same identifier. This happens in the breaking down of ANDIF/ORIF trees, so the coverage generally works well for frontends that create such trees. Like Whalen et al this implementation records coverage in fixed-size bitsets which gcov knows how to interpret. Recording conditions only requires a few bitwise operations per condition and is very fast, but comes with a limit on the number of terms in a single boolean expression; the number of bits in a gcov_unsigned_type (which is usually typedef'd to uint64_t). For most practical purposes this is acceptable, and by default a warning will be issued if gcc cannot instrument the expression. This is a practical limitation in the implementation, and not a limitation of the algorithm, so support for more conditions can be supported by introducing arbitrary-sized bitsets. In action it looks pretty similar to the branch coverage. The -g short opt carries no significance, but was chosen because it was an available option with the upper-case free too. gcov --conditions: 3: 17:void fn (int a, int b, int c, int d) { 3: 18: if ((a && (b || c)) && d) conditions covered 3/8 condition 0 not covered (true false) condition 1 not covered (true) condition 2 not covered (true) condition 3 not covered (true) 1: 19: x = 1; -: 20: else 2: 21: x = 2; 3: 22:} gcov --conditions --json-format: "conditions": [ { "not_covered_false": [ 0 ], "count": 8, "covered": 3, "not_covered_true": [ 0, 1, 2, 3 ] } ], Expressions with constants may be heavily rewritten before it reaches the gimplification, so constructs like int x = a ? 0 : 1 becomes _x = (_a == 0). From source you would expect coverage, but it gets neither branch nor condition coverage. The same applies to expressions like int x = 1 || a which are simply replaced by a constant. The test suite contains a lot of small programs and functions. Some of these were designed by hand to test for specific behaviours and graph shapes, and some are previously-failed test cases in other programs adapted into the test suite. gcc/ChangeLog: * builtins.cc (expand_builtin_fork_or_exec): Check condition_coverage_flag. * collect2.cc (main): Add -fno-condition-coverage to OBSTACK. * common.opt: Add new options -fcondition-coverage and -Wcoverage-too-many-conditions. * doc/gcov.texi: Add --conditions documentation. * doc/invoke.texi: Add -fcondition-coverage documentation. * function.cc (free_after_compilation): Free cond_uids. * function.h (struct function): Add cond_uids. * gcc.cc: Link gcov on -fcondition-coverage. * gcov-counter.def (GCOV_COUNTER_CONDS): New. * gcov-dump.cc (tag_conditions): New. * gcov-io.h (GCOV_TAG_CONDS): New. (GCOV_TAG_CONDS_LENGTH): New. (GCOV_TAG_CONDS_NUM): New. * gcov.cc (class condition_info): New. (condition_info::condition_info): New. (condition_info::popcount): New. (struct coverage_info): New. (add_condition_counts): New. (output_conditions): New. (print_usage): Add -g, --conditions. (process_args): Likewise. (output_intermediate_json_line): Output conditions. (read_graph_file): Read condition counters. (read_count_file): Likewise. (file_summary): Print conditions. (accumulate_line_info): Accumulate conditions. (output_line_details): Print conditions. * gimplify.cc (next_cond_uid): New. (reset_cond_uid): New. (shortcut_cond_r): Set condition discriminator. (tag_shortcut_cond): New. (gimple_associate_condition_with_expr): New. (shortcut_cond_expr): Set condition discriminator. (gimplify_cond_expr): Likewise. (gimplify_function_tree): Call reset_cond_uid. * ipa-inline.cc (can_early_inline_edge_p): Check condition_coverage_flag. * ipa-split.cc (pass_split_functions::gate): Likewise. * passes.cc (finish_optimization_passes): Likewise. * profile.cc (struct condcov): New declaration. (cov_length): Likewise. (cov_blocks): Likewise. (cov_masks): Likewise. (cov_maps): Likewise. (cov_free): Likewise. (instrument_decisions): New. (read_thunk_profile): Control output to file. (branch_prob): Call find_conditions, instrument_decisions. (init_branch_prob): Add total_num_conds. (end_branch_prob): Likewise. * tree-core.h (struct tree_exp): Add condition_uid. * tree-profile.cc (struct conds_ctx): New. (CONDITIONS_MAX_TERMS): New. (EDGE_CONDITION): New. (topological_cmp): New. (index_of): New. (single_p): New. (single_edge): New. (contract_edge_up): New. (struct outcomes): New. (conditional_succs): New. (condition_index): New. (condition_uid): New. (masking_vectors): New. (emit_assign): New. (emit_bitwise_op): New. (make_top_index_visit): New. (make_top_index): New. (paths_between): New. (struct condcov): New. (cov_length): New. (cov_blocks): New. (cov_masks): New. (cov_maps): New. (cov_free): New. (find_conditions): New. (struct counters): New. (find_counters): New. (resolve_counter): New. (resolve_counters): New. (instrument_decisions): New. (tree_profiling): Check condition_coverage_flag. (pass_ipa_tree_profile::gate): Likewise. * tree.h (SET_EXPR_UID): New. (EXPR_COND_UID): New. libgcc/ChangeLog: * libgcov-merge.c (__gcov_merge_ior): New. gcc/testsuite/ChangeLog: * lib/gcov.exp: Add condition coverage test function. * g++.dg/gcov/gcov-18.C: New test. * gcc.misc-tests/gcov-19.c: New test. * gcc.misc-tests/gcov-20.c: New test. * gcc.misc-tests/gcov-21.c: New test. * gcc.misc-tests/gcov-22.c: New test. * gcc.misc-tests/gcov-23.c: New test.
2024-04-03GCN: install.texi update for Newlib change and LLVM 18 releaseTobias Burnus1-3/+5
gcc/ChangeLog: * doc/install.texi (amdgcn-*-amdhsa): Update Newlib recommendation and update wording for LLVM 18 release.
2024-04-02LoongArch: Add support for TLS descriptors.mengqinggang1-1/+15
Add support for TLS descriptors on normal code model and extreme code model. Normal code model instruction sequence: -mno-explicit-relocs: la.tls.desc $r4, s add.d $r12, $r4, $r2 -mexplicit-relocs: pcalau12i $r4,%desc_pc_hi20(s) addi.d $r4,$r4,%desc_pc_lo12(s) ld.d $r1,$r4,%desc_ld(s) jirl $r1,$r1,%desc_call(s) add.d $r12, $r4, $r2 Extreme code model instruction sequence: -mno-explicit-relocs: la.tls.desc $r4, $r12, s add.d $r12, $r4, $r2 -mexplicit-relocs: pcalau12i $r4,%desc_pc_hi20(s) addi.d $r12,$r0,%desc_pc_lo12(s) lu32i.d $r12,%desc64_pc_lo20(s) lu52i.d $r12,$r12,%desc64_pc_hi12(s) add.d $r4,$r4,$r12 ld.d $r1,$r4,%desc_ld(s) jirl $r1,$r1,%desc_call(s) add.d $r12, $r4, $r2 The default is still traditional TLS model, but can be configured with --with-tls={trad,desc}. The default can change to TLS descriptors once libc and LLVM support this. gcc/ChangeLog: * config.gcc: Add --with-tls option to change TLS flavor. * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to configure TLS flavor. * config/loongarch/loongarch-def.h (struct loongarch_target): Add tls_dialect. * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls flavor. * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add tls_dialect. (loongarch_config_target): Ditto. (loongarch_update_gcc_opt_status): Ditto. * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto. (TARGET_TLS_DESC): New define. * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS DESC instructions sequence length. (loongarch_legitimize_tls_address): New TLS DESC instruction sequence. (loongarch_option_override_internal): Add la_opt_tls_dialect. (loongarch_option_restore): Add la_target.tls_dialect. * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal code model for TLS DESC. (got_load_tls_desc_off64): Extreme cmode model for TLS DESC. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch.opt.urls: Ditto. * doc/invoke.texi: Add a description of the compilation option '-mtls-dialect={trad,desc}'. gcc/testsuite/ChangeLog: * gcc.target/loongarch/cmodel-extreme-1.c: Add -mtls-dialect=trad. * gcc.target/loongarch/cmodel-extreme-2.c: Ditto. * gcc.target/loongarch/explicit-relocs-auto-tls-ld-gd.c: Ditto. * gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c: Ditto. * gcc.target/loongarch/func-call-medium-1.c: Ditto. * gcc.target/loongarch/func-call-medium-2.c: Ditto. * gcc.target/loongarch/func-call-medium-3.c: Ditto. * gcc.target/loongarch/func-call-medium-4.c: Ditto. * gcc.target/loongarch/tls-extreme-macro.c: Ditto. * gcc.target/loongarch/tls-gd-noplt.c: Ditto. * gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-auto-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c: New test. * gcc.target/loongarch/explicit-relocs-tls-desc.c: New test. Co-authored-by: Lulu Cheng <chenglulu@loongson.cn> Co-authored-by: Xi Ruoyao <xry111@xry111.site>
2024-04-01LoongArch: Add descriptions of the compilation options.Lulu Cheng1-2/+43
Add descriptions for the compilation options '-mfrecipe' '-mdiv32' '-mlam-bh' '-mlamcas' and '-mld-seq-sa'. gcc/ChangeLog: * doc/invoke.texi: Add descriptions for the compilation options.
2024-03-28PR modula2/114517 gm2 does not allow comparison operator hash in column oneGaius Mulley1-1/+2
This patch allows -fno-cpp to be supplied to gm2. Without this patch it causes an ICE. The patch allows -fno-cpp to turn off cpp flags. These are tested in m2.flex to decide whether a change of state is allowed (enabling handling of #line directives). gcc/ChangeLog: PR modula2/114517 * doc/gm2.texi: Mention gm2 treats a # in the first column as a preprocessor directive unless -fno-cpp is supplied. gcc/m2/ChangeLog: PR modula2/114517 * gm2-compiler/M2Options.def (SetCpp): Add comment. (GetCpp): Move after SetCpp. (GetLineDirectives): New procedure function. * gm2-compiler/M2Options.mod (GetLineDirectives): New procedure function. * gm2-gcc/m2options.h (M2Options_GetLineDirectives): New prototype. * gm2-lang.cc (gm2_langhook_init_options): OPT_fcpp only assert if !value. * m2.flex: Test GetLineDirectives before changing to LINE0 state. gcc/testsuite/ChangeLog: PR modula2/114517 * gm2/cpp/fail/hashfirstcolumn2.mod: New test. * gm2/imports/fail/imports-fail.exp: New test. * gm2/imports/fail/localmodule2.mod: New test. * gm2/imports/run/pass/localmodule.mod: New test. Signed-off-by: Gaius Mulley <(no_default)>
2024-03-27docs: Use @var{S} etc. in Spec File invoke.texi documentationJakub Jelinek1-47/+47
We got internally a question about the Spec File syntax, misunderstanding what is the literal syntax and what are the placeholder variables in the syntax descriptions. The following patch attempts to use @var{S} etc. instead of just S to clarify it stands for any option (or start of option etc.) rather than literal S, say in %{S:X}. At least in HTML documentation it then uses italics. 2024-03-27 Jakub Jelinek <jakub@redhat.com> * doc/invoke.texi (Spec Files): Use @var{S} instead of S, @var{X} instead of X etc. for other placeholders.
2024-03-27aarch64: Add +lse128 architectural extension command-line flagVictor Do Nascimento1-0/+4
Given how, at present, the choice of using LSE128 atomic instructions by the toolchain is delegated to run-time selection in the form of Libatomic ifuncs, responsible for querying target support, the `+lse128' target architecture compile-time flag is absent from GCC. This, however, contrasts with the Binutils implementation, which gates LSE128 instructions behind the `+lse128' flag. This can lead to problems in GCC for certain use-cases. One such example is in the use of inline assembly, whereby the inability of enabling the feature in the command-line prevents the compiler from automatically issuing the necessary LSE128 `.arch' directive. This patch therefore brings GCC into alignment with LLVM and Binutils in adding support for the `+lse128' architectural extension flag. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def: Add LSE128 AARCH64_OPT_EXTENSION, adding it as a dependency for the D128 feature. * doc/invoke.texi (AArch64 Options): Document +lse128. gcc/testsuite/ChangeLog: * gcc.target/aarch64/lse128-flag.c: New. * gcc.target/aarch64/cpunative/info_23: Likewise. * gcc.target/aarch64/cpunative/native_cpu_23.c: Likewise.
2024-03-25amdgcn: Add gfx1036 targetRichard Biener2-1/+5
Add support for the gfx1036 RDNA2 APU integrated graphics devices. The ROCm documentation warns that these may not be supported, but it seems to work at least partially. gcc/ChangeLog: * config.gcc (amdgcn): Add gfx1036 entries. * config/gcn/gcn-hsa.h (NO_XNACK): Likewise. (gcn_local_sym_hash): Likewise. * config/gcn/gcn-opts.h (enum processor_type): Likewise. (TARGET_GFX1036): New macro. * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036. (gcn_omp_device_kind_arch_isa): Likewise. (output_file_start): Likewise. * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__. (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__. * config/gcn/gcn.opt: Add gfx1036. * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New. (main): Handle gfx1036. * config/gcn/t-omp-device: Add gfx1036 isa. * doc/install.texi (amdgcn): Add gfx1036. * doc/invoke.texi (-march): Likewise. libgomp/ChangeLog: * plugin/plugin-gcn.c (EF_AMDGPU_MACH): GFX1036. (gcn_gfx1103_s): New. (isa_hsa_name): Handle gfx1036. (isa_code): Likewise. (max_isa_vgprs): Likewise.
2024-03-22amdgcn: Add gfx1103 targetAndrew Stubbs2-6/+10
Add support for the gfx1103 RDNA3 APU integrated graphics devices. The ROCm documentation warns that these may not be supported, but it seems to work at least partially. gcc/ChangeLog: * config.gcc (amdgcn): Add gfx1103 entries. * config/gcn/gcn-hsa.h (NO_XNACK): Likewise. (gcn_local_sym_hash): Likewise. * config/gcn/gcn-opts.h (enum processor_type): Likewise. (TARGET_GFX1103): New macro. * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103. (gcn_omp_device_kind_arch_isa): Likewise. (output_file_start): Likewise. (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100. * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__. * config/gcn/gcn.opt: Add gfx1103. * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New. (main): Handle gfx1103. * config/gcn/t-omp-device: Add gfx1103 isa. * doc/install.texi (amdgcn): Add gfx1103. * doc/invoke.texi (-march): Likewise. libgomp/ChangeLog: * plugin/plugin-gcn.c (EF_AMDGPU_MACH): GFX1103. (gcn_gfx1103_s): New. (isa_hsa_name): Handle gfx1103. (isa_code): Likewise. (max_isa_vgprs): Likewise.
2024-03-21Document -fexcess-precision=16.liuhongt1-0/+3
gcc/ChangeLog: PR middle-end/114347 * doc/invoke.texi: Document -fexcess-precision=16.
2024-03-19libstdc++: Regenerate <bits/version.h> in maintainer modeJonathan Wakely1-0/+2
This is a generated header but regenerating it requires the manual step of running 'make -C include update-version' in the libstdc++ build dir. Make it regenerate automatically when --enable-maintainer-mode is used. libstdc++-v3/ChangeLog: * include/Makefile.am [MAINTAINER_MODE]: Add target to automatically update <bits/version.h>. * include/Makefile.in: Regenerate. gcc/ChangeLog: * doc/install.texi (Prerequisites): Document use of autogen for libstdc++.
2024-03-18[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+3
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Create XCVbi extension support. * config/riscv/riscv.opt: Likewise. * config/riscv/corev.md: Implement cv_branch<mode> pattern for cv.beqimm and cv.bneimm. * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V branch instruction pattern. * config/riscv/constraints.md: Implement constraints cv_bi_s5 - signed 5-bit immediate. * config/riscv/predicates.md: Implement predicate const_int5s_operand - signed 5 bit immediate. * doc/sourcebuild.texi: Add XCVbi documentation. gcc/testsuite/ChangeLog: * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test. * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test. * lib/target-supports.exp: Add proc for XCVbi.
2024-03-18Add AMD znver5 processor enablement with scheduler modelJan Hubicka2-0/+13
2024-02-14 Jan Hubicka <jh@suse.cz> Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com> gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5. * common/config/i386/i386-common.cc (processor_names): Add znver5. (processor_alias_table): Likewise. * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen family. (processor_subtypes): Add znver5. * config.gcc (x86_64-*-* |...): Likewise. * config/i386/driver-i386.cc (host_detect_local_cpu): Let march=native detect znver5 cpu's. * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5. * config/i386/i386-options.cc (m_ZNVER5): New definition (processor_cost_table): Add znver5. * config/i386/i386.cc (ix86_reassociation_width): Likewise. * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5 (PTA_ZNVER5): New definition. * config/i386/i386.md (define_attr "cpu"): Add znver5. (Scheduling descriptions) Add znver5.md. * config/i386/x86-tune-costs.h (znver5_cost): New definition. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5. (ix86_adjust_cost): Likewise. * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5. (avx512_store_by_pieces): Add m_ZNVER5. * doc/extend.texi: Add znver5. * doc/invoke.texi: Likewise. * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler. gcc/testsuite/ChangeLog: * g++.target/i386/mv29.C: Handle znver5 arch. * gcc.target/i386/funcspec-56.inc:Likewise.
2024-03-15MIPS: Add -m(no-)strict-align optionYunQiang Su1-6/+12
We support options -m(no-)unaligned-access 2 years ago, while currently most of other ports prefer -m(no-)strict-align. Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access as alias. gcc * config/mips/mips.opt: Support -mstrict-align, and use TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access as alias. * config/mips/mips.h: Use TARGET_STRICT_ALIGN. * config/mips/mips.opt.urls: Regenerate. * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
2024-03-09[committed] [target/102250] Document python requirement for risc-vjlaw1-0/+5
PR target/102250 gcc/ * doc/install.texi: Document need for python when building RISC-V compilers.
2024-03-08bpf: add size threshold for inlining mem builtinsDavid Faust1-1/+10
BPF cannot fall back on library calls to implement memmove, memcpy and memset, so we attempt to expand these inline always if possible. However, this inline expansion was being attempted even for excessively large operations, which could result in gcc consuming huge amounts of memory and hanging. Add a size threshold in the BPF backend below which to always expand these operations inline, and introduce an option -minline-memops-threshold= to control the threshold. Defaults to 1024 bytes. gcc/ * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do not attempt inline expansion if size is above threshold. * config/bpf/bpf.opt (-minline-memops-threshold): New option. * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>: Document. gcc/testsuite/ * gcc.target/bpf/inline-memops-threshold-1.c: New test. * gcc.target/bpf/inline-memops-threshold-2.c: New test.
2024-03-08i386: Guard noreturn no-callee-saved-registers optimization with ↵Jakub Jelinek1-0/+10
-mnoreturn-no-callee-saved-registers [PR38534] The following patch hides the noreturn no_callee_saved_registers (except bp) optimization with a not enabled by default option. The reason is that most noreturn functions should be called just once in a program (unless they are recursive or invoke longjmp or similar, for exceptions we already punt), so it isn't that essential to save a few instructions in their prologue, but more importantly because it interferes with debugging. And unlike most other optimizations, doesn't actually make it harder to debug the given function, which can be solved by recompiling the given function if it is too hard to debug, but makes it harder to debug the callers of that noreturn function. Those can be from a different translation unit, different binary or even different package, so if e.g. glibc abort needs to use all of the callee saved registers (%rbx, %rbp, %r12, %r13, %r14, %r15), debugging any programs which abort will be harder because any DWARF expressions which use those registers will be optimized out, not just in the immediate caller, but in other callers as well until some frame restores a particular register from some stack slot. 2024-03-08 Jakub Jelinek <jakub@redhat.com> PR target/38534 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New option. * config/i386/i386-options.cc (ix86_set_func_type): Don't use TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless ix86_noreturn_no_callee_saved_registers is enabled. * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document. * gcc.target/i386/pr38534-1.c: Add -mnoreturn-no-callee-saved-registers to dg-options. * gcc.target/i386/pr38534-2.c: Likewise. * gcc.target/i386/pr38534-3.c: Likewise. * gcc.target/i386/pr38534-4.c: Likewise. * gcc.target/i386/pr38534-5.c: Likewise. * gcc.target/i386/pr38534-6.c: Likewise. * gcc.target/i386/pr114097-1.c: Likewise. * gcc.target/i386/stack-check-17.c: Likewise.
2024-03-07doc: Fix docs for -dD regarding predefined macrosJonathan Wakely1-2/+1
The manual has always claimed that -dD differs from -dM by not outputting predefined macros, but that's untrue. It has been untrue since GCC 3.0 (probably with the change to use libcpp as the default preprocessor implementation). gcc/ChangeLog: * doc/cppopts.texi: Remove incorrect claim about -dD not outputting predefined macros.
2024-03-04c++/modules: relax diagnostic about GMF contentsPatrick Palka1-1/+7
Issuing a hard error when the GMF doesn't consist only of preprocessing directives happens to be inconvenient for automated testcase reduction via cvise. This patch relaxes this diagnostic into a pedwarn that can be disabled with -Wno-global-module. gcc/c-family/ChangeLog: * c.opt (Wglobal-module): New warning. gcc/cp/ChangeLog: * parser.cc (cp_parser_translation_unit): Relax GMF contents error into a pedwarn. gcc/ChangeLog: * doc/invoke.texi (-Wno-global-module): Document. gcc/testsuite/ChangeLog: * g++.dg/modules/friend-6_a.C: Pass -Wno-global-module instead of -Wno-pedantic. Remove now unnecessary preprocessing directives from GMF. Reviewed-by: Jason Merrill <jason@redhat.com>
2024-03-04doc: update [[gnu::no_dangling]]Marek Polacek1-1/+2
...to offer a more realistic example. gcc/ChangeLog: * doc/extend.texi: Update [[gnu::no_dangling]].
2024-03-01c++: implement [[gnu::no_dangling]] [PR110358]Marek Polacek2-0/+54
Since -Wdangling-reference has false positives that can't be prevented, we should offer an easy way to suppress the warning. Currently, that is only possible by using a #pragma, either around the enclosing class or around the call site. But #pragma GCC diagnostic tend to be onerous. A better solution would be to have an attribute. To that end, this patch adds a new attribute, [[gnu::no_dangling]]. This attribute takes an optional bool argument to support cases like: template <typename T> struct [[gnu::no_dangling(std::is_reference_v<T>)]] S { // ... }; PR c++/110358 PR c++/109642 gcc/cp/ChangeLog: * call.cc (no_dangling_p): New. (reference_like_class_p): Use it. (do_warn_dangling_reference): Use it. Don't warn when the function or its enclosing class has attribute gnu::no_dangling. * tree.cc (cxx_gnu_attributes): Add gnu::no_dangling. (handle_no_dangling_attribute): New. gcc/ChangeLog: * doc/extend.texi: Document gnu::no_dangling. * doc/invoke.texi: Mention that gnu::no_dangling disables -Wdangling-reference. gcc/testsuite/ChangeLog: * g++.dg/ext/attr-no-dangling1.C: New test. * g++.dg/ext/attr-no-dangling2.C: New test. * g++.dg/ext/attr-no-dangling3.C: New test. * g++.dg/ext/attr-no-dangling4.C: New test. * g++.dg/ext/attr-no-dangling5.C: New test. * g++.dg/ext/attr-no-dangling6.C: New test. * g++.dg/ext/attr-no-dangling7.C: New test. * g++.dg/ext/attr-no-dangling8.C: New test. * g++.dg/ext/attr-no-dangling9.C: New test.
2024-03-01AVR: Document valid ranges of -mfuse-add=Georg-Johann Lay1-0/+1
gcc/ * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document valid values for level.
2024-03-01RISC-V: Add riscv_vector_cc function attributexuli1-0/+10
Standard vector calling convention variant will only enabled when function has vector argument or returning value by default, however user may also want to invoke function without that during a vectorized loop at some situation, but it will cause a huge performance penalty due to vector register store/restore. So user can declare function with this riscv_vector_cc attribute like below, that could enforce function will use standard vector calling convention variant. void foo() __attribute__((riscv_vector_cc)); [[riscv::vector_cc]] void foo(); // For C++11 and C23 For more details please reference the below link. https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 gcc/ChangeLog: * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc attribute to riscv_attribute_table. (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function. (riscv_fntype_abi): Add riscv_vector_cc attribute check. * doc/extend.texi: Add riscv_vector_cc attribute description. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test.
2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay1-1/+9
The Reduced Tiny core does not support indirect addressing with offset, which basically means that every indirect memory access with a size of more than one byte is effectively POST_INC or PRE_DEC. The lack of that addressing mode is currently handled by pretending to support it, and then let the insn printers add and subtract again offsets as needed. For example, the following C code int vars[10]; void inc_var2 (void) { ++vars[2]; } is compiled to: ldi r30,lo8(vars) ; 14 [c=4 l=2] *movhi/4 ldi r31,hi8(vars) subi r30,lo8(-(4)) ; 15 [c=8 l=6] *movhi/2 sbci r31,hi8(-(4)) ld r20,Z+ ld r21,Z subi r30,lo8((4+1)) sbci r31,hi8((4+1)) subi r20,-1 ; 16 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 subi r30,lo8(-(4+1)) ; 17 [c=4 l=4] *movhi/3 sbci r31,hi8(-(4+1)) st Z,r21 st -Z,r20 where the code could be -- and with this patch actually is -- like ldi r30,lo8(vars+4) ; 28 [c=4 l=2] *movhi/4 ldi r31,hi8(vars+4) ld r20,Z+ ; 17 [c=8 l=2] *movhi/2 ld r21,Z+ subi r20,-1 ; 19 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 st -Z,r21 ; 30 [c=4 l=2] *movhi/3 st -Z,r20 This is achieved in two steps: - A post-reload split into "real" instructions during .split2. - A new avr-specific mini pass .avr-fuse-add that runs before RTL peephole and that tries to combine the generated pointer additions into memory accesses to form POST_INC or PRE_DEC. gcc/ PR target/114100 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. * config/avr/avr.opt (-mfuse-add=): New target option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. * config/avr/avr-protos.h (avr_split_tiny_move) (make_avr_pass_fuse_add): New protos. * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses avr_split_tiny_move to split indirect memory accesses. (gen_move_clobbercc): New define_expand helper. * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. (avr_pass_fuse_add): New class from rtl_opt_pass. (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets of PLUS addressing for AVR_TINY. (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
2024-02-23doc: RISC-V: Document that -mcpu doesn't override -march or -mtunePalmer Dabbelt1-0/+2
This came up recently as Edwin was looking through the test suite. A few of us were talking about this during the patchwork meeting and were surprised. Looks like this is the desired behavior, so let's at least document it. gcc/ChangeLog: * doc/invoke.texi: Document -mcpu. Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-02-22c: Handle scoped attributes in __has*attribute and scoped attribute parsing ↵Jakub Jelinek1-4/+1
changes in -std=c11 etc. modes [PR114007] We aren't able to parse __has_attribute (vendor::attr) (and __has_c_attribute and __has_cpp_attribute) in strict C < C23 modes. While in -std=gnu* modes or in -std=c23 there is CPP_SCOPE token, in -std=c* (except for -std=c23) there are is just a pair of CPP_COLON tokens. The c-lex.cc hunk adds support for that. That leads to a question if we should return 1 or 0 from __has_attribute (gnu::unused) or not, because while [[gnu::unused]] is parsed fine in -std=gnu*/-std=c23 modes (sure, with pedwarn for < C23), we do not parse it at all in -std=c* (except for -std=c23), we only parse [[__extension__ gnu::unused]] there. While the __extension__ in there helps to avoid the pedwarn, I think it is better to be consistent between GNU and strict C < C23 modes and parse [[gnu::unused]] too; on the other side, I think parsing [[__extension__ gnu : : unused]] is too weird and undesirable. So, the following patch adds a flag during preprocessing at the point where we normally create CPP_SCOPE tokens out of 2 consecutive colons on the first CPP_COLON to mark the consecutive case (as we are tight on the bits, I've reused the PURE_ZERO flag, which is used just by the C++ FE and only ever set (both C and C++) on CPP_NUMBER tokens, this new flag has the same value and is only ever used on CPP_COLON tokens) and instead of checking loose_scope_p argument (i.e. whether it is [[__extension__ ...]] or not), it just parses CPP_SCOPE or CPP_COLON with CLONE_SCOPE flag followed by another CPP_COLON the same. The latter will never appear in >= C23 or -std=gnu* modes, though guarding its use say with flag_iso && !flag_isoc23 && doesn't really work because the __extension__ case temporarily clears flag_iso flag. This makes the -std=c11 etc. behavior more similar to -std=gnu11 or -std=c23, the only difference I'm aware of are the #define JOIN2(A, B) A##B [[vendor JOIN2(:,:) attr]] [[__extension__ vendor JOIN2(:,:) attr]] cases, which are accepted in the latter modes, but results in error in -std=c11; but the error is during preprocessing that :: doesn't form a valid preprocessing token, which is true, so just don't do that if you try to have __STRICT_ANSI__ && __STDC_VERSION__ <= 201710L compatibility. 2024-02-22 Jakub Jelinek <jakub@redhat.com> PR c/114007 gcc/ * doc/extend.texi: (__extension__): Remove comments about scope tokens vs. two colons. gcc/c-family/ * c-lex.cc (c_common_has_attribute): Parse 2 CPP_COLONs with the first one with COLON_SCOPE flag the same as CPP_SCOPE. gcc/c/ * c-parser.cc (c_parser_std_attribute): Remove loose_scope_p argument. Instead of checking it, parse 2 CPP_COLONs with the first one with COLON_SCOPE flag the same as CPP_SCOPE. (c_parser_std_attribute_list): Remove loose_scope_p argument, don't pass it to c_parser_std_attribute. (c_parser_std_attribute_specifier): Adjust c_parser_std_attribute_list caller. gcc/testsuite/ * gcc.dg/c23-attr-syntax-6.c: Adjust testcase for :: being valid even in -std=c11 even without __extension__ and : : etc. not being valid anymore even with __extension__. * gcc.dg/c23-attr-syntax-7.c: Likewise. * gcc.dg/c23-attr-syntax-8.c: New test. libcpp/ * include/cpplib.h (COLON_SCOPE): Define to PURE_ZERO. * lex.cc (_cpp_lex_direct): When lexing CPP_COLON with another colon after it, if !CPP_OPTION (pfile, scope) set COLON_SCOPE flag on the first CPP_COLON token.
2024-02-22invoke.texi: Fix some skipping UrlSuffix problem for MIPSYunQiang Su1-9/+5
The problem is that, there are these lines in mips.opt.urls: ; skipping UrlSuffix for 'mabi=' due to finding no URLs ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs These lines is not fixed by this patch due to that we don't document these options: ; skipping UrlSuffix for 'mlra' due to finding no URLs ; skipping UrlSuffix for 'mdebug' due to finding no URLs ; skipping UrlSuffix for 'meb' due to finding no URLs ; skipping UrlSuffix for 'mel' due to finding no URLs gcc * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix problem of mabi=, mno-flush-func, mexplicit-relocs; add missing leading - of mbranch-cost option. * config/mips/mips.opt.urls: Regenerate.
2024-02-21rs6000: Neuter option -mpower{8,9}-vector [PR109987]Kewen Lin4-25/+12
As PR109987 and its duplicated bugs show, -mno-power8-vector (and -mno-power9-vector) cause some problems and as Segher pointed out in [1] they are workaround options, so this patch is to remove -m{no,}-power{8,9}-options. Like what we did for option -mdirect-move before, this patch still keep the corresponding internal flags and they are automatically set based on -mcpu. The test suite update takes some efforts, it consists of some aspects: - effective target powerpc_p{8,9}vector_ok are removed and replaced with powerpc_vsx_ok. - Some cases having -mpower{8,9}-vector are updated with -mvsx, some of them already have -mdejagnu-cpu. For those that don't have -mdejagnu-cpu, if -mdejagnu-cpu is needed for the test point, then it's appended; otherwise, add additional-options -mdejagnu-cpu=power{8,9} if has_arch_pwr{8,9} isn't satisfied. - Some test cases are updated with explicit -mvsx. - Some test cases with those two option mixed are adjusted to keep the test points, like -mpower8-vector -mno-power9-vector are updated with -mdejagnu-cpu=power8 -mvsx etc. - Some test cases with -mno-power{8,9}-vector are updated by replacing -mno-power{8,9}-vector with -mno-vsx, or just removing it. - For some cases, we don't always specify -mdejagnu-cpu to avoid to restrict the testing coverage, it would check has_arch_pwr{8,9} and appended that as need. - For vect test cases run, it doesn't specify -mcpu=power9 for power10 and up. Bootstrapped and regtested on: - powerpc64-linux-gnu P7/P8/P9 {-m32,-m64} - powerpc64le-linux-gnu P8/P9/P10 Although it's stage4 now, as the discussion in PR113115 we are still eager to neuter these two options, so is it ok for trunk? [1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html PR target/109987 gcc/ChangeLog: * config/rs6000/constraints.md (we): Update internal doc without referring to option -mpower9-vector. * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector special handlings. * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS, OTHER_P8_VECTOR_MASKS): Merge to ... (OTHER_VSX_VECTOR_MASKS): ... here. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove some error message handlings and explicit option mask adjustments on explicit option power{8,9}-vector conflicting with other options. (rs6000_print_isa_options): Update comments. (rs6000_disable_incompatible_switches): Remove power{8,9}-vector related array items and handlings. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector special handlings. * config/rs6000/rs6000.opt: Make option power{8,9}-vector as WarnRemoved. * doc/extend.texi: Remove documentation referring to option -mpower8-vector. * doc/invoke.texi: Remove documentation for option -mpower{8,9}-vector and adjust some documentation referring to them. * doc/md.texi: Update documentation for constraint we. * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok. libgcc/ChangeLog: * config/rs6000/t-float128-hw: Replace options -mpower{8,9}-vector with -mcpu=power9. * configure.ac: Update use of option -mpower9-vector with -mcpu=power9. * configure: Regenerate. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_powerpc_p8vector_ok): Remove. (check_effective_target_powerpc_p9vector_ok): Remove. (check_p8vector_hw_available): Replace -mpower8-vector with -mcpu=power8. (check_p9vector_hw_available): Replace -mpower9-vector with -mcpu=power9. (check_ppc_float128_hw_available): Likewise. (check_vect_support_and_set_flags): Replace -mpower8-vector with -mcpu=power8, replace -mpower9-vector with -mcpu=power9 or nothing if check_power10_hw_available and place -mcpu=970 first if needed to avoid possible overriding. * g++.target/powerpc/altivec-19.C: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-5.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise. * gcc.target/powerpc/builtins-3-p9.c: Likewise. * gcc.target/powerpc/byte-in-either-range-0.c: Likewise. * gcc.target/powerpc/byte-in-either-range-1.c: Likewise. * gcc.target/powerpc/byte-in-range-0.c: Likewise. * gcc.target/powerpc/byte-in-range-1.c: Likewise. * gcc.target/powerpc/byte-in-set-0.c: Likewise. * gcc.target/powerpc/byte-in-set-1.c: Likewise. * gcc.target/powerpc/byte-in-set-2.c: Likewise. * gcc.target/powerpc/clone1.c: Likewise. * gcc.target/powerpc/ctz-3.c: Likewise. * gcc.target/powerpc/ctz-4.c: Likewise. * gcc.target/powerpc/darn-0.c: Likewise. * gcc.target/powerpc/darn-1.c: Likewise. * gcc.target/powerpc/darn-2.c: Likewise. * gcc.target/powerpc/dform-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-0.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-1.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-10.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-11.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-12.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-13.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-14.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-15.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-17.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-18.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-19.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-2.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-20.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-21.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-22.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-23.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-24.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-25.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-26.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-27.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-28.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-29.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-30.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-31.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-32.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-33.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-34.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-35.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-36.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-37.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-38.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-39.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-4.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-40.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-41.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-42.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-43.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-44.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-45.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-46.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-47.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-48.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-49.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-5.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-50.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-52.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-53.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-54.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-55.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-57.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-58.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-59.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-6.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-60.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-61.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-62.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-63.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-64.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-65.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-66.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-67.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-68.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-69.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-7.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-70.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-72.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-73.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-74.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-75.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-77.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-78.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-79.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-8.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-9.c: Likewise. * gcc.target/powerpc/direct-move-vector.c: Likewise. * gcc.target/powerpc/float128-type-2.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p9.c: Likewise. * gcc.target/powerpc/p9-dimode1.c: Likewise. * gcc.target/powerpc/p9-dimode2.c: Likewise. * gcc.target/powerpc/p9-extract-1.c: Likewise. * gcc.target/powerpc/p9-extract-2.c: Likewise. * gcc.target/powerpc/p9-extract-3.c: Likewise. * gcc.target/powerpc/p9-extract-4.c: Likewise. * gcc.target/powerpc/p9-fpcvt-1.c: Likewise. * gcc.target/powerpc/p9-fpcvt-2.c: Likewise. * gcc.target/powerpc/p9-fpcvt-3.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-1.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-2.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. * gcc.target/powerpc/p9-minmax-1.c: Likewise. * gcc.target/powerpc/p9-minmax-2.c: Likewise. * gcc.target/powerpc/p9-minmax-3.c: Likewise. * gcc.target/powerpc/p9-novsx.c: Likewise. * gcc.target/powerpc/p9-permute.c: Likewise. * gcc.target/powerpc/p9-sign_extend-runnable.c: Likewise. * gcc.target/powerpc/p9-splat-1.c: Likewise. * gcc.target/powerpc/p9-splat-2.c: Likewise. * gcc.target/powerpc/p9-splat-3.c: Likewise. * gcc.target/powerpc/p9-splat-4.c: Likewise. * gcc.target/powerpc/p9-splat-5.c: Likewise. * gcc.target/powerpc/p9-vbpermd.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-8.c: Likewise. * gcc.target/powerpc/p9-vneg.c: Likewise. * gcc.target/powerpc/p9-vparity.c: Likewise. * gcc.target/powerpc/p9-vpermr.c: Likewise. * gcc.target/powerpc/p9-xxbr-1.c: Likewise. * gcc.target/powerpc/p9-xxbr-2.c: Likewise. * gcc.target/powerpc/p9-xxbr-3.c: Likewise. * gcc.target/powerpc/ppc-fortran/pr80108-1.f90: Likewise. * gcc.target/powerpc/ppc-round3.c: Likewise. * gcc.target/powerpc/pr103124.c: Likewise. * gcc.target/powerpc/pr104015-1.c: Likewise. * gcc.target/powerpc/pr106769-p9.c: Likewise. * gcc.target/powerpc/pr107412.c: Likewise. * gcc.target/powerpc/pr110429.c: Likewise. * gcc.target/powerpc/pr66144-1.c: Likewise. * gcc.target/powerpc/pr71186.c: Likewise. * gcc.target/powerpc/pr71309.c: Likewise. * gcc.target/powerpc/pr71670.c: Likewise. * gcc.target/powerpc/pr71698.c: Likewise. * gcc.target/powerpc/pr71720.c: Likewise. * gcc.target/powerpc/pr72853.c: Likewise. * gcc.target/powerpc/pr78056-1.c: Likewise. * gcc.target/powerpc/pr78658.c: Likewise. * gcc.target/powerpc/pr78953.c: Likewise. * gcc.target/powerpc/pr79004.c: Likewise. * gcc.target/powerpc/pr79038-1.c: Likewise. * gcc.target/powerpc/pr79179.c: Likewise. * gcc.target/powerpc/pr79251.p9.c: Likewise. * gcc.target/powerpc/pr79799-1.c: Likewise. * gcc.target/powerpc/pr79799-2.c: Likewise. * gcc.target/powerpc/pr79799-3.c: Likewise. * gcc.target/powerpc/pr79799-5.c: Likewise. * gcc.target/powerpc/pr80695-p9.c: Likewise. * gcc.target/powerpc/pr81348.c: Likewise. * gcc.target/powerpc/pr81622.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. * gcc.target/powerpc/pr90763.c: Likewise. * gcc.target/powerpc/pr96933-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-2.c: Likewise. * gcc.target/powerpc/signbit-2.c: Likewise. * gcc.target/powerpc/vadsdu-0.c: Likewise. * gcc.target/powerpc/vadsdu-1.c: Likewise. * gcc.target/powerpc/vadsdu-2.c: Likewise. * gcc.target/powerpc/vadsdu-3.c: Likewise. * gcc.target/powerpc/vadsdu-4.c: Likewise. * gcc.target/powerpc/vadsdu-5.c: Likewise. * gcc.target/powerpc/vadsdub-1.c: Likewise. * gcc.target/powerpc/vadsdub-2.c: Likewise. * gcc.target/powerpc/vadsduh-1.c: Likewise. * gcc.target/powerpc/vadsduh-2.c: Likewise. * gcc.target/powerpc/vadsduw-1.c: Likewise. * gcc.target/powerpc/vadsduw-2.c: Likewise. * gcc.target/powerpc/vec-extract-4.c: Likewise. * gcc.target/powerpc/vec-init-3.c: Likewise. * gcc.target/powerpc/vec-minmax-1.c: Likewise. * gcc.target/powerpc/vec-minmax-2.c: Likewise. * gcc.target/powerpc/vec-set-char.c: Likewise. * gcc.target/powerpc/vec-set-int.c: Likewise. * gcc.target/powerpc/vec-set-short.c: Likewise. * gcc.target/powerpc/vec_reve_2.c: Likewise. * gcc.target/powerpc/vector_float.c: Likewise. * gcc.target/powerpc/vslv-0.c: Likewise. * gcc.target/powerpc/vslv-1.c: Likewise. * gcc.target/powerpc/vsrv-0.c: Likewise. * gcc.target/powerpc/vsrv-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-10.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-11.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-12.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-13.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-7.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-0.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-11.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-12.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-13.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-9.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-9.c: Likewise. * gcc.target/powerpc/vsx-builtin-msum.c: Likewise. * gcc.target/powerpc/vsx-himode.c: Likewise. * gcc.target/powerpc/vsx-himode2.c: Likewise. * gcc.target/powerpc/vsx-himode3.c: Likewise. * gcc.target/powerpc/vsx-qimode.c: Likewise. * gcc.target/powerpc/vsx-qimode2.c: Likewise. * gcc.target/powerpc/vsx-qimode3.c: Likewise. * g++.target/powerpc/pr65240-1.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.target/powerpc/pr65240-2.C: Likewise. * g++.target/powerpc/pr65240-3.C: Likewise. * g++.target/powerpc/pr65242.C: Likewise. * g++.target/powerpc/pr67211.C: Likewise. * g++.target/powerpc/pr71294.C: Likewise. * g++.target/powerpc/pr84279.C: Likewise. * g++.target/powerpc/pr93974.C: Likewise. * gcc.target/powerpc/atomic-p8.c: Likewise. * gcc.target/powerpc/atomic_load_store-p8.c: Likewise. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/bool2-p8.c: Likewise. * gcc.target/powerpc/bool3-p8.c: Likewise. * gcc.target/powerpc/builtins-1.c: Likewise. * gcc.target/powerpc/builtins-3-p8.c: Likewise. * gcc.target/powerpc/builtins-5.c: Likewise. * gcc.target/powerpc/builtins-9.c: Likewise. * gcc.target/powerpc/crypto-builtin-1.c: Likewise. * gcc.target/powerpc/crypto-builtin-2.c: Likewise. * gcc.target/powerpc/direct-move-double1.c: Likewise. * gcc.target/powerpc/direct-move-float1.c: Likewise. * gcc.target/powerpc/direct-move-long1.c: Likewise. * gcc.target/powerpc/direct-move-vint1.c: Likewise. * gcc.target/powerpc/float128-type-1.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-double.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-char.c: Likewise. * gcc.target/powerpc/fold-vec-neg-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-short.c: Likewise. * gcc.target/powerpc/fold-vec-select-double.c: Likewise. * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c: Likewise. * gcc.target/powerpc/fusion.c: Likewise. * gcc.target/powerpc/fusion2.c: Likewise. * gcc.target/powerpc/mul-vectorize-1.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst-v2.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst.c: Likewise. * gcc.target/powerpc/p8vector-builtin-1.c: Likewise. * gcc.target/powerpc/p8vector-builtin-2.c: Likewise. * gcc.target/powerpc/p8vector-builtin-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-4.c: Likewise. * gcc.target/powerpc/p8vector-builtin-5.c: Likewise. * gcc.target/powerpc/p8vector-builtin-6.c: Likewise. * gcc.target/powerpc/p8vector-builtin-7.c: Likewise. * gcc.target/powerpc/p8vector-fp.c: Likewise. * gcc.target/powerpc/p8vector-int128-1.c: Likewise. * gcc.target/powerpc/p8vector-ldst.c: Likewise. * gcc.target/powerpc/p8vector-vbpermq.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-1.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. * gcc.target/powerpc/ppc-round2.c: Likewise. * gcc.target/powerpc/pr100866-1.c: Likewise. * gcc.target/powerpc/pr100866-2.c: Likewise. * gcc.target/powerpc/pr104239-1.c: Likewise. * gcc.target/powerpc/pr104239-2.c: Likewise. * gcc.target/powerpc/pr104239-3.c: Likewise. * gcc.target/powerpc/pr106769-p8.c: Likewise. * gcc.target/powerpc/pr108396.c: Likewise. * gcc.target/powerpc/pr111449-1.c: Likewise. * gcc.target/powerpc/pr57744.c: Likewise. * gcc.target/powerpc/pr58673-1.c: Likewise. * gcc.target/powerpc/pr58673-2.c: Likewise. * gcc.target/powerpc/pr60137.c: Likewise. * gcc.target/powerpc/pr60203.c: Likewise. * gcc.target/powerpc/pr66144-2.c: Likewise. * gcc.target/powerpc/pr66144-3.c: Likewise. * gcc.target/powerpc/pr68163.c: Likewise. * gcc.target/powerpc/pr69548.c: Likewise. * gcc.target/powerpc/pr70669.c: Likewise. * gcc.target/powerpc/pr71977-1.c: Likewise. * gcc.target/powerpc/pr71977-2.c: Likewise. * gcc.target/powerpc/pr72717.c: Likewise. * gcc.target/powerpc/pr78056-3.c: Likewise. * gcc.target/powerpc/pr78056-4.c: Likewise. * gcc.target/powerpc/pr78102.c: Likewise. * gcc.target/powerpc/pr78543.c: Likewise. * gcc.target/powerpc/pr78604.c: Likewise. * gcc.target/powerpc/pr79251.p8.c: Likewise. * gcc.target/powerpc/pr79354.c: Likewise. * gcc.target/powerpc/pr79544.c: Likewise. * gcc.target/powerpc/pr79907.c: Likewise. * gcc.target/powerpc/pr79951.c: Likewise. * gcc.target/powerpc/pr80315-1.c: Likewise. * gcc.target/powerpc/pr80315-2.c: Likewise. * gcc.target/powerpc/pr80315-3.c: Likewise. * gcc.target/powerpc/pr80315-4.c: Likewise. * gcc.target/powerpc/pr80510-2.c: Likewise. * gcc.target/powerpc/pr80695-p8.c: Likewise. * gcc.target/powerpc/pr80718.c: Likewise. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr88558-p8.c: Likewise. * gcc.target/powerpc/pr88845.c: Likewise. * gcc.target/powerpc/pr91903.c: Likewise. * gcc.target/powerpc/pr92923-2.c: Likewise. * gcc.target/powerpc/pr96933-2.c: Likewise. * gcc.target/powerpc/pr97019.c: Likewise. * gcc.target/powerpc/pragma_power8.c: Likewise. * gcc.target/powerpc/signbit-1.c: Likewise. * gcc.target/powerpc/swaps-p8-1.c: Likewise. * gcc.target/powerpc/swaps-p8-12.c: Likewise. * gcc.target/powerpc/swaps-p8-14.c: Likewise. * gcc.target/powerpc/swaps-p8-15.c: Likewise. * gcc.target/powerpc/swaps-p8-16.c: Likewise. * gcc.target/powerpc/swaps-p8-17.c: Likewise. * gcc.target/powerpc/swaps-p8-18.c: Likewise. * gcc.target/powerpc/swaps-p8-19.c: Likewise. * gcc.target/powerpc/swaps-p8-2.c: Likewise. * gcc.target/powerpc/swaps-p8-22.c: Likewise. * gcc.target/powerpc/swaps-p8-23.c: Likewise. * gcc.target/powerpc/swaps-p8-24.c: Likewise. * gcc.target/powerpc/swaps-p8-25.c: Likewise. * gcc.target/powerpc/swaps-p8-26.c: Likewise. * gcc.target/powerpc/swaps-p8-27.c: Likewise. * gcc.target/powerpc/swaps-p8-3.c: Likewise. * gcc.target/powerpc/swaps-p8-30.c: Likewise. * gcc.target/powerpc/swaps-p8-33.c: Likewise. * gcc.target/powerpc/swaps-p8-36.c: Likewise. * gcc.target/powerpc/swaps-p8-39.c: Likewise. * gcc.target/powerpc/swaps-p8-4.c: Likewise. * gcc.target/powerpc/swaps-p8-42.c: Likewise. * gcc.target/powerpc/swaps-p8-45.c: Likewise. * gcc.target/powerpc/swaps-p8-46.c: Likewise. * gcc.target/powerpc/swaps-p8-5.c: Likewise. * gcc.target/powerpc/unpack-vectorize-3.c: Likewise. * gcc.target/powerpc/upper-regs-sf.c: Likewise. * gcc.target/powerpc/vec-cmp.c: Likewise. * gcc.target/powerpc/vec-extract-1.c: Likewise. * gcc.target/powerpc/vec-extract-3.c: Likewise. * gcc.target/powerpc/vec-extract-5.c: Likewise. * gcc.target/powerpc/vec-extract-6.c: Likewise. * gcc.target/powerpc/vec-extract-7.c: Likewise. * gcc.target/powerpc/vec-extract-8.c: Likewise. * gcc.target/powerpc/vec-extract-9.c: Likewise. * gcc.target/powerpc/vec-init-10.c: Likewise. * gcc.target/powerpc/vec-init-6.c: Likewise. * gcc.target/powerpc/vec-init-7.c: Likewise. * gcc.target/powerpc/vsx-extract-3.c: Likewise. * gcc.target/powerpc/vsx-extract-4.c: Likewise. * gcc.target/powerpc/vsx-extract-5.c: Likewise. * gcc.target/powerpc/vsx-simode.c: Likewise. * gcc.target/powerpc/vsx-simode2.c: Likewise. * gcc.target/powerpc/vsx-simode3.c: Likewise. * gcc.target/powerpc/builtins-4-int128-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/builtins-mergew-mergow.c: Likewise. * gcc.target/powerpc/direct-move-float3.c: Likewise. * gcc.target/powerpc/divkc3-2.c: Likewise. * gcc.target/powerpc/divkc3-3.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-add-4.c: Likewise. * gcc.target/powerpc/fold-vec-add-7.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.h: Likewise. * gcc.target/powerpc/fold-vec-cmp-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.h: Likewise. * gcc.target/powerpc/fold-vec-cntlz-char.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-int.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-short.c: Likewise. * gcc.target/powerpc/fold-vec-ld-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-float.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-short.c: Likewise. * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-short.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int.c: Likewise. * gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.h: Likewise. * gcc.target/powerpc/fold-vec-pack-double.c: Likewise. * gcc.target/powerpc/fold-vec-pack-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-st-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-sub-int128.c: Likewise. * gcc.target/powerpc/fold-vec-sub-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-float.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-int.c: Likewise. * gcc.target/powerpc/mmx-packs.c: Likewise. * gcc.target/powerpc/mmx-packssdw-1.c: Likewise. * gcc.target/powerpc/mmx-packsswb-1.c: Likewise. * gcc.target/powerpc/mmx-packuswb-1.c: Likewise. * gcc.target/powerpc/mmx-paddb-1.c: Likewise. * gcc.target/powerpc/mmx-paddd-1.c: Likewise. * gcc.target/powerpc/mmx-paddsb-1.c: Likewise. * gcc.target/powerpc/mmx-paddsw-1.c: Likewise. * gcc.target/powerpc/mmx-paddusb-1.c: Likewise. * gcc.target/powerpc/mmx-paddusw-1.c: Likewise. * gcc.target/powerpc/mmx-paddw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/mmx-pmaddwd-1.c: Likewise. * gcc.target/powerpc/mmx-pmulhw-1.c: Likewise. * gcc.target/powerpc/mmx-pmullw-1.c: Likewise. * gcc.target/powerpc/mmx-pslld-1.c: Likewise. * gcc.target/powerpc/mmx-psllw-1.c: Likewise. * gcc.target/powerpc/mmx-psrad-1.c: Likewise. * gcc.target/powerpc/mmx-psraw-1.c: Likewise. * gcc.target/powerpc/mmx-psrld-1.c: Likewise. * gcc.target/powerpc/mmx-psrlw-1.c: Likewise. * gcc.target/powerpc/mmx-psubb-2.c: Likewise. * gcc.target/powerpc/mmx-psubd-2.c: Likewise. * gcc.target/powerpc/mmx-psubsb-1.c: Likewise. * gcc.target/powerpc/mmx-psubsw-1.c: Likewise. * gcc.target/powerpc/mmx-psubusb-1.c: Likewise. * gcc.target/powerpc/mmx-psubusw-1.c: Likewise. * gcc.target/powerpc/mmx-psubw-2.c: Likewise. * gcc.target/powerpc/mmx-punpckhbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhdq-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhwd-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckldq-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklwd-1.c: Likewise. * gcc.target/powerpc/mulkc3-2.c: Likewise. * gcc.target/powerpc/mulkc3-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-8.c: Likewise. * gcc.target/powerpc/pr37191.c: Likewise. * gcc.target/powerpc/pr83862.c: Likewise. * gcc.target/powerpc/pr84154-1.c: Likewise. * gcc.target/powerpc/pr84220-sld2.c: Likewise. * gcc.target/powerpc/pr85456.c: Likewise. * gcc.target/powerpc/pr86731-longlong.c: Likewise. * gcc.target/powerpc/sse-addps-1.c: Likewise. * gcc.target/powerpc/sse-addss-1.c: Likewise. * gcc.target/powerpc/sse-andnps-1.c: Likewise. * gcc.target/powerpc/sse-andps-1.c: Likewise. * gcc.target/powerpc/sse-cmpss-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32x2ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi16-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi8-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-2.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-2.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-2.c: Likewise. * gcc.target/powerpc/sse-divps-1.c: Likewise. * gcc.target/powerpc/sse-divss-1.c: Likewise. * gcc.target/powerpc/sse-maxps-1.c: Likewise. * gcc.target/powerpc/sse-maxps-2.c: Likewise. * gcc.target/powerpc/sse-maxss-1.c: Likewise. * gcc.target/powerpc/sse-minps-1.c: Likewise. * gcc.target/powerpc/sse-minps-2.c: Likewise. * gcc.target/powerpc/sse-minss-1.c: Likewise. * gcc.target/powerpc/sse-movaps-1.c: Likewise. * gcc.target/powerpc/sse-movaps-2.c: Likewise. * gcc.target/powerpc/sse-movhlps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-2.c: Likewise. * gcc.target/powerpc/sse-movlhps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-2.c: Likewise. * gcc.target/powerpc/sse-movmskb-1.c: Likewise. * gcc.target/powerpc/sse-movmskps-1.c: Likewise. * gcc.target/powerpc/sse-movss-1.c: Likewise. * gcc.target/powerpc/sse-movss-2.c: Likewise. * gcc.target/powerpc/sse-movss-3.c: Likewise. * gcc.target/powerpc/sse-mulps-1.c: Likewise. * gcc.target/powerpc/sse-mulss-1.c: Likewise. * gcc.target/powerpc/sse-orps-1.c: Likewise. * gcc.target/powerpc/sse-pavgw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse-pminsw-1.c: Likewise. * gcc.target/powerpc/sse-pminub-1.c: Likewise. * gcc.target/powerpc/sse-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse-psadbw-1.c: Likewise. * gcc.target/powerpc/sse-rcpps-1.c: Likewise. * gcc.target/powerpc/sse-rsqrtps-1.c: Likewise. * gcc.target/powerpc/sse-shufps-1.c: Likewise. * gcc.target/powerpc/sse-sqrtps-1.c: Likewise. * gcc.target/powerpc/sse-subps-1.c: Likewise. * gcc.target/powerpc/sse-subss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-2.c: Likewise. * gcc.target/powerpc/sse-ucomiss-3.c: Likewise. * gcc.target/powerpc/sse-ucomiss-4.c: Likewise. * gcc.target/powerpc/sse-ucomiss-5.c: Likewise. * gcc.target/powerpc/sse-ucomiss-6.c: Likewise. * gcc.target/powerpc/sse-unpckhps-1.c: Likewise. * gcc.target/powerpc/sse-unpcklps-1.c: Likewise. * gcc.target/powerpc/sse-xorps-1.c: Likewise. * gcc.target/powerpc/sse2-addpd-1.c: Likewise. * gcc.target/powerpc/sse2-addsd-1.c: Likewise. * gcc.target/powerpc/sse2-andnpd-1.c: Likewise. * gcc.target/powerpc/sse2-andpd-1.c: Likewise. * gcc.target/powerpc/sse2-cmppd-1.c: Likewise. * gcc.target/powerpc/sse2-cmpsd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-2.c: Likewise. * gcc.target/powerpc/sse2-comisd-3.c: Likewise. * gcc.target/powerpc/sse2-comisd-4.c: Likewise. * gcc.target/powerpc/sse2-comisd-5.c: Likewise. * gcc.target/powerpc/sse2-comisd-6.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2ss-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-2.c: Likewise. * gcc.target/powerpc/sse2-cvtss2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvttpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-divpd-1.c: Likewise. * gcc.target/powerpc/sse2-divsd-1.c: Likewise. * gcc.target/powerpc/sse2-maxpd-1.c: Likewise. * gcc.target/powerpc/sse2-maxsd-1.c: Likewise. * gcc.target/powerpc/sse2-minpd-1.c: Likewise. * gcc.target/powerpc/sse2-minsd-1.c: Likewise. * gcc.target/powerpc/sse2-mmx.c: Likewise. * gcc.target/powerpc/sse2-movhpd-1.c: Likewise. * gcc.target/powerpc/sse2-movhpd-2.c: Likewise. * gcc.target/powerpc/sse2-movlpd-1.c: Likewise. * gcc.target/powerpc/sse2-movlpd-2.c: Likewise. * gcc.target/powerpc/sse2-movmskpd-1.c: Likewise. * gcc.target/powerpc/sse2-movq-1.c: Likewise. * gcc.target/powerpc/sse2-movq-2.c: Likewise. * gcc.target/powerpc/sse2-movq-3.c: Likewise. * gcc.target/powerpc/sse2-movsd-1.c: Likewise. * gcc.target/powerpc/sse2-movsd-2.c: Likewise. * gcc.target/powerpc/sse2-movsd-3.c: Likewise. * gcc.target/powerpc/sse2-mulpd-1.c: Likewise. * gcc.target/powerpc/sse2-mulsd-1.c: Likewise. * gcc.target/powerpc/sse2-orpd-1.c: Likewise. * gcc.target/powerpc/sse2-packssdw-1.c: Likewise. * gcc.target/powerpc/sse2-packsswb-1.c: Likewise. * gcc.target/powerpc/sse2-packuswb-1.c: Likewise. * gcc.target/powerpc/sse2-paddb-1.c: Likewise. * gcc.target/powerpc/sse2-paddd-1.c: Likewise. * gcc.target/powerpc/sse2-paddq-1.c: Likewise. * gcc.target/powerpc/sse2-paddsb-1.c: Likewise. * gcc.target/powerpc/sse2-paddsw-1.c: Likewise. * gcc.target/powerpc/sse2-paddusb-1.c: Likewise. * gcc.target/powerpc/sse2-paddusw-1.c: Likewise. * gcc.target/powerpc/sse2-paddw-1.c: Likewise. * gcc.target/powerpc/sse2-pand-1.c: Likewise. * gcc.target/powerpc/sse2-pandn-1.c: Likewise. * gcc.target/powerpc/sse2-pavgb-1.c: Likewise. * gcc.target/powerpc/sse2-pavgw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/sse2-pextrw.c: Likewise. * gcc.target/powerpc/sse2-pinsrw.c: Likewise. * gcc.target/powerpc/sse2-pmaddwd-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse2-pminsw-1.c: Likewise. * gcc.target/powerpc/sse2-pminub-1.c: Likewise. * gcc.target/powerpc/sse2-pmovmskb-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhw-1.c: Likewise. * gcc.target/powerpc/sse2-pmullw-1.c: Likewise. * gcc.target/powerpc/sse2-pmuludq-1.c: Likewise. * gcc.target/powerpc/sse2-por-1.c: Likewise. * gcc.target/powerpc/sse2-psadbw-1.c: Likewise. * gcc.target/powerpc/sse2-pshufd-1.c: Likewise. * gcc.target/powerpc/sse2-pshufhw-1.c: Likewise. * gcc.target/powerpc/sse2-pshuflw-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-2.c: Likewise. * gcc.target/powerpc/sse2-pslldq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-2.c: Likewise. * gcc.target/powerpc/sse2-psllw-1.c: Likewise. * gcc.target/powerpc/sse2-psllw-2.c: Likewise. * gcc.target/powerpc/sse2-psrad-1.c: Likewise. * gcc.target/powerpc/sse2-psrad-2.c: Likewise. * gcc.target/powerpc/sse2-psraw-1.c: Likewise. * gcc.target/powerpc/sse2-psraw-2.c: Likewise. * gcc.target/powerpc/sse2-psrld-1.c: Likewise. * gcc.target/powerpc/sse2-psrld-2.c: Likewise. * gcc.target/powerpc/sse2-psrldq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-2.c: Likewise. * gcc.target/powerpc/sse2-psrlw-1.c: Likewise. * gcc.target/powerpc/sse2-psrlw-2.c: Likewise. * gcc.target/powerpc/sse2-psubb-1.c: Likewise. * gcc.target/powerpc/sse2-psubd-1.c: Likewise. * gcc.target/powerpc/sse2-psubq-1.c: Likewise. * gcc.target/powerpc/sse2-psubsb-1.c: Likewise. * gcc.target/powerpc/sse2-psubsw-1.c: Likewise. * gcc.target/powerpc/sse2-psubusb-1.c: Likewise. * gcc.target/powerpc/sse2-psubusw-1.c: Likewise. * gcc.target/powerpc/sse2-psubw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhwd-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckldq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklwd-1.c: Likewise. * gcc.target/powerpc/sse2-pxor-1.c: Likewise. * gcc.target/powerpc/sse2-shufpd-1.c: Likewise. * gcc.target/powerpc/sse2-sqrtpd-1.c: Likewise. * gcc.target/powerpc/sse2-subpd-1.c: Likewise. * gcc.target/powerpc/sse2-subsd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-2.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-3.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-4.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-5.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-6.c: Likewise. * gcc.target/powerpc/sse2-unpckhpd-1.c: Likewise. * gcc.target/powerpc/sse2-unpcklpd-1.c: Likewise. * gcc.target/powerpc/sse2-xorpd-1.c: Likewise. * gcc.target/powerpc/sse3-addsubpd.c: Likewise. * gcc.target/powerpc/sse3-addsubps.c: Likewise. * gcc.target/powerpc/sse3-haddpd.c: Likewise. * gcc.target/powerpc/sse3-haddps.c: Likewise. * gcc.target/powerpc/sse3-hsubpd.c: Likewise. * gcc.target/powerpc/sse3-hsubps.c: Likewise. * gcc.target/powerpc/sse3-lddqu.c: Likewise. * gcc.target/powerpc/sse3-movddup.c: Likewise. * gcc.target/powerpc/sse3-movshdup.c: Likewise. * gcc.target/powerpc/sse3-movsldup.c: Likewise. * gcc.target/powerpc/sse4_1-blendpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendps-2.c: Likewise. * gcc.target/powerpc/sse4_1-blendps.c: Likewise. * gcc.target/powerpc/sse4_1-blendvpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendvps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilpd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilsd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilss.c: Likewise. * gcc.target/powerpc/sse4_1-floorpd.c: Likewise. * gcc.target/powerpc/sse4_1-floorps.c: Likewise. * gcc.target/powerpc/sse4_1-floorsd.c: Likewise. * gcc.target/powerpc/sse4_1-floorss.c: Likewise. * gcc.target/powerpc/sse4_1-pblendvb.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw-2.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw.c: Likewise. * gcc.target/powerpc/sse4_1-pcmpeqq.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrb.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrd.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxbq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxdq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxwq.c: Likewise. * gcc.target/powerpc/sse4_1-pmuldq.c: Likewise. * gcc.target/powerpc/sse4_1-ptest-1.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-2.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-3.c: Likewise. * gcc.target/powerpc/sse4_2-pcmpgtq.c: Likewise. * gcc.target/powerpc/ssse3-pabsb.c: Likewise. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/powerpc/ssse3-pabsw.c: Likewise. * gcc.target/powerpc/ssse3-palignr.c: Likewise. * gcc.target/powerpc/ssse3-phaddd.c: Likewise. * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. * gcc.target/powerpc/ssse3-phaddw.c: Likewise. * gcc.target/powerpc/ssse3-phsubd.c: Likewise. * gcc.target/powerpc/ssse3-phsubsw.c: Likewise. * gcc.target/powerpc/ssse3-phsubw.c: Likewise. * gcc.target/powerpc/ssse3-pmaddubsw.c: Likewise. * gcc.target/powerpc/ssse3-pmulhrsw.c: Likewise. * gcc.target/powerpc/ssse3-pshufb.c: Likewise. * gcc.target/powerpc/ssse3-psignb.c: Likewise. * gcc.target/powerpc/ssse3-psignd.c: Likewise. * gcc.target/powerpc/ssse3-psignw.c: Likewise. * gcc.target/powerpc/vec-cmp-sel.c: Likewise. * gcc.target/powerpc/vec-sld-modulo.c: Likewise. * gcc.target/powerpc/vec-srad-modulo.c: Likewise. * gcc.target/powerpc/vec-srd-modulo.c: Likewise. * gcc.target/powerpc/amo1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mpower9-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power9 if !has_arch_pwr9. * gcc.target/powerpc/amo2.c: Likewise. * gcc.target/powerpc/dform-1.c: Likewise. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/float128-5.c: Likewise. * gcc.target/powerpc/float128-complex-2.c: Likewise. * gcc.target/powerpc/float128-fma1.c: Likewise. * gcc.target/powerpc/float128-hw.c: Likewise. * gcc.target/powerpc/float128-hw10.c: Likewise. * gcc.target/powerpc/float128-hw11.c: Likewise. * gcc.target/powerpc/float128-hw2.c: Likewise. * gcc.target/powerpc/float128-hw3.c: Likewise. * gcc.target/powerpc/float128-hw4.c: Likewise. * gcc.target/powerpc/float128-hw5.c: Likewise. * gcc.target/powerpc/float128-hw6.c: Likewise. * gcc.target/powerpc/float128-hw7.c: Likewise. * gcc.target/powerpc/float128-hw8.c: Likewise. * gcc.target/powerpc/float128-hw9.c: Likewise. * gcc.target/powerpc/float128-minmax.c: Likewise. * gcc.target/powerpc/float128-odd.c: Likewise. * gcc.target/powerpc/float128-sqrt1.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p9.c: Likewise. * gcc.target/powerpc/gnuattr2.c: Likewise. * gcc.target/powerpc/pr71656-1.c: Likewise. * gcc.target/powerpc/pr71656-2.c: Likewise. * gcc.target/powerpc/pr81959.c: Likewise. * gcc.target/powerpc/pr82748-1.c: Likewise. * gcc.target/powerpc/pr82748-2.c: Likewise. * gcc.target/powerpc/pr111449-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/pr98914.c: Likewise. * gcc.target/powerpc/versioned-copy-loop.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/clone2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/p9-options-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr84226.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.dg/pr69667.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mpower9-vector with -mvsx. * gcc.dg/vect/pr109011-1.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector with -mdejagnu-cpu=power8 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, and replace -mpower9-vector with -mdejagnu-cpu=power9 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-4.c: Likewise. * gcc.dg/vect/pr109011-3.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector -mno-power9-vector with -mdejagnu-cpu=power8 -mvsx. * gcc.dg/vect/pr109011-5.c: Likewise. * gcc.target/powerpc/altivec-35.c: Remove -mno-power8-vector. * gcc.target/powerpc/vsx-vector-7.c: Replace -mno-power8-vector with -mdejagnu-cpu=power7. * gcc.dg/vect/O3-pr70130.c: Replace -mcpu=power7 with options -mdejagnu-cpu=power7 -mvsx and remove option -mno-power9-vector -mno-power8-vector. * gfortran.dg/vect/pr45714-b.f: Likewise. * gcc.dg/vect/pr48765.c: Remove dg-skip-if and replace -mcpu=power7 with option -mdejagnu-cpu=power6. * gcc.target/powerpc/pr78056-2.c: Likewise. * gcc.target/powerpc/altivec-2-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, remove -mpower8-vector and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/altivec-37.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mpower8-vector with -mvsx. * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-int.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p8.c: Likewise. * gcc.target/powerpc/pr104124.c: Likewise. * gcc.target/powerpc/vec-cmpne-long.c: Likewise. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/pr80098-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr80098-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mno-power8-vector with -mno-vsx. * gcc.target/powerpc/pragma_misc9.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok.
2024-02-21doc: Fix typos in -Wmismatched-dealloc docsJonathan Wakely1-1/+1
gcc/ChangeLog: * doc/invoke.texi (Warning Options): Fix typos.
2024-02-21pru: Document how -mmcu option uses MCU specsDimitar Dimitrov1-2/+8
The plan to maintain PRU hardware-specific specs in newlib tree has been abandoned in favour of a new distinct GIT project. Update the documentation accordingly. gcc/ChangeLog: * doc/invoke.texi (-mmcu): Add information about MCU specs. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-02-21pru: Document that arguments are not passed to main with -minrtDimitar Dimitrov1-5/+12
The minimal runtime has been documented from the beginning to break some standard features in order to reduce code size, while keeping the features required by typical firmware programs. Document one more imposed restriction - the main() function must take no arguments. gcc/ChangeLog: * doc/invoke.texi (-minrt): Clarify that main must take no arguments. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2024-02-20AVR: Use types of exact size and signedness in built-ins.Georg-Johann Lay1-9/+7
The AVR built-ins used types like "int" or "char" that don't have exact signedness or type size which depend on -mint8 and -f[no-][un-]signed-char etc. As the built-ins are modelling machine instructions of given type sizes and signedness, also use according types in their prototypes. gcc/ * config/avr/builtins.def: Use function prototypes of given size and signedness. * config/avr/avr.cc (avr_init_builtins): Adjust types required by builtins.def. * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2024-02-20AVR: extend.texi - Use @defbuiltin to document built-ins.Georg-Johann Lay1-16/+20
gcc/ * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin instead of @table.
2024-02-18AVR: Improve documentation for -mmcu=.Georg-Johann Lay1-6/+16
gcc/ * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel". Note on complete device support.
2024-02-18AVR: Add examples for ISR macro to interrupt attribute doc.Georg-Johann Lay1-30/+41
gcc/ * doc/extend.texi (AVR Function Attributes): Fuse description of "signal" and "interrupt" attribute. Link pseudo instruction.
generated by cgit v1.1 at 2025-09-27 02:33:52 +0000