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2024-09-05docs: double mention of armv9-a.Tamar Christina1-1/+0
The list of available architecture for Arm is incorrectly listing armv9-a twice. This removes the duplicate armv9-a enumeration from the part of the list having M-profile targets. gcc/ChangeLog: * doc/invoke.texi: Remove duplicate armv9-a mention.
2024-09-03Explicitly document that the "counted_by" attribute is only supported in C.Qing Zhao1-0/+4
The "counted_by" attribute currently is only supported in C, mention this explicitly in documentation and also issue warnings when see "counted_by" attribute in C++ with -Wattributes. gcc/c-family/ChangeLog: * c-attribs.cc (handle_counted_by_attribute): Is ignored and issues warning with -Wattributes in C++ for now. gcc/ChangeLog: * doc/extend.texi: Explicitly mentions counted_by is available only in C for now. gcc/testsuite/ChangeLog: * g++.dg/ext/flex-array-counted-by.C: New test. * g++.dg/ext/flex-array-counted-by-2.C: New test.
2024-09-02[testsuite] add linkonly to dg-additional-sources [PR115295]Alexandre Oliva1-4/+5
The D testsuite shows it was a mistake to assume that dg-additional-sources are never to be used for compilation tests. Even if an output file is specified for compilation, extra module files can be named and used in the compilation without being flagged as errors. Introduce a 'linkonly' flag for dg-additional-sources, and use it in pr95401.cc and other vector tests that default to run, so that its additional sources get discarded when vector tests downgrade to compile-only. This reverts previous workarounds for this very circumstance, that relied on being able to run vector tests anyway, even after failing to detect runtime or hardware vector support. for gcc/ChangeLog PR d/115295 * doc/sourcebuild.texi (dg-additional-sources): Add linkonly. for gcc/testsuite/ChangeLog PR d/115295 * g++.dg/vect/pr95401.cc: Add linkonly to dg-additional-sources. * g++.dg/vect/pr68762-1.cc: Likewise. * g++.dg/vect/simd-clone-3.cc: Likewise. * g++.dg/vect/simd-clone-5.cc: Likewise. * gcc.dg/vect/vect-simd-clone-10.c: Likewise. Drop dg-do run. * gcc.dg/vect/vect-simd-clone-12.c: Likewise. Likewise. * lib/gcc-defs.exp (additional_sources_omit_on_compile): New. (dg-additional-sources): Add to it on linkonly. (dg-additional-files-options): Omit select sources on compile.
2024-09-02amdgcn: remove gfx803 "Fiji" supportAndrew Stubbs2-12/+1
The gfx803 "Fiji" device was deprecated in GCC 14, removed from LLVM 18, and hasn't worked properly with the drivers since about ROCm 4. This patch removes the device from GCC options and documentation, and removes the direct mentions from the internals. The TARGET_GCN3 support in the back-end is now unused and can be removed (in a follow-up patch). gcc/ChangeLog: * config.gcc (amdgcn-*-*): Remove "fiji" from with_arch checks. * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Remove fiji alternative. (NO_XNACK): Likewise. (NO_SRAM_ECC): Likewise. (ASM_SPEC): Remove "%{}" around ABI_VERSION_SPEC. * config/gcn/gcn-opts.h (enum processor_type): Remove PROCESSOR_FIJI. (TARGET_FIJI): Delete. * config/gcn/gcn.cc (gcn_option_override): Remove Fiji. (gcn_omp_device_kind_arch_isa): Likewise. (output_file_start): Likewise. * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Likewise. * config/gcn/gcn.opt (gpu_type): Likewise. (march, mtune): Change default to PROCESSOR_VEGA10. * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX803): Delete. (copy_early_debug_info): Remove elf_flags_actual. Use ELFABIVERSION_AMDGPU_HSA_V4 unconditionally. (get_arch): Remove Fiji. (main): Remove gfx803. * config/gcn/t-omp-device (omp-device-properties-gcn): Remove fiji and gfx803. * doc/install.texi (amdgcn*-*-*): Remove fiji and special instructions. * doc/invoke.texi: Remove fiji. libgomp/ChangeLog: * libgomp.texi: Remove fiji and gfx803. * testsuite/libgomp.c/declare-variant-4.h: Remove fiji and gfx803. * testsuite/libgomp.c/declare-variant-4-fiji.c: Removed. * testsuite/libgomp.c/declare-variant-4-gfx803.c: Removed.
2024-09-02Rename gimple_asm_input_p to gimple_asm_basic_pRichard Sandiford1-0/+9
Following on from the earlier tree rename, this patch renames gimple_asm_input_p to gimple_asm_basic_p, and similarly for related names. gcc/ * doc/gimple.texi (gimple_asm_basic_p): Document. (gimple_asm_set_basic): Likewise. * gimple.h (GF_ASM_INPUT): Rename to... (GF_ASM_BASIC): ...this. (gimple_asm_set_input): Rename to... (gimple_asm_set_basic): ...this. (gimple_asm_input_p): Rename to... (gimple_asm_basic_p): ...this. * cfgexpand.cc (expand_asm_stmt): Update after above renaming. * gimple.cc (gimple_asm_clobbers_memory_p): Likewise. * gimplify.cc (gimplify_asm_expr): Likewise. * ipa-icf-gimple.cc (func_checker::compare_gimple_asm): Likewise. * tree-cfg.cc (stmt_can_terminate_bb_p): Likewise.
2024-09-02Rename ASM_INPUT_P to ASM_BASIC_PRichard Sandiford1-5/+11
ASM_INPUT_P is so named because it causes the eventual rtl insn pattern to be a top-level ASM_INPUT rather than an ASM_OPERANDS. However, this name has caused confusion, partly due to earlier documentation. The name also sounds related to ASM_INPUTS but is for a different piece of state. This patch renames it to ASM_BASIC_P, with the inverse meaning an extended asm. ("Basic asm" is the term used in extend.texi.) gcc/ * doc/generic.texi (ASM_BASIC_P): Document. * tree.h (ASM_INPUT_P): Rename to... (ASM_BASIC_P): ...this. (ASM_VOLATILE_P, ASM_INLINE_P): Reindent. * gimplify.cc (gimplify_asm_expr): Update after above renaming. * tree-core.h (tree_base): Likewise. gcc/c/ * c-typeck.cc (build_asm_expr): Rename ASM_INPUT_P to ASM_BASIC_P. gcc/cp/ * pt.cc (tsubst_stmt): Rename ASM_INPUT_P to ASM_BASIC_P. * parser.cc (cp_parser_asm_definition): Likewise. gcc/d/ * toir.cc (IRVisitor): Rename ASM_INPUT_P to ASM_BASIC_P. gcc/jit/ * jit-playback.cc (playback::block::add_extended_asm): Rename ASM_INPUT_P to ASM_BASIC_P. gcc/m2/ * gm2-gcc/m2block.cc (flush_pending_note): Rename ASM_INPUT_P to ASM_BASIC_P. * gm2-gcc/m2statement.cc (m2statement_BuildAsm): Likewise.
2024-08-31c: Add support for unsequenced and reproducible attributesJakub Jelinek1-0/+63
C23 added in N2956 ( https://open-std.org/JTC1/SC22/WG14/www/docs/n2956.htm ) two new attributes, which are described as similar to GCC const and pure attributes, but they aren't really same and it seems that even the paper is missing some of the differences. The paper says unsequenced is the same as const on functions without pointer arguments and reproducible is the same as pure on such functions (except that they are function type attributes rather than function declaration ones), but it seems the paper doesn't consider the finiteness GCC relies on (aka non-DECL_LOOPING_CONST_OR_PURE_P) - the paper only talks about using the attributes for CSE etc., not for DCE. The following patch introduces (for now limited) support for those attributes, both as standard C23 attributes and as GNU extensions (the difference is that the patch is then less strict on where it allows them, like other function type attributes they can be specified on function declarations as well and apply to the type, while C23 standard ones must go on the function declarators (i.e. after closing paren after function parameters) or in type specifiers of function type. If function doesn't have any pointer/reference arguments, the patch adds additional internal attribute with " noptr" suffix which then is used by flags_from_decl_or_type to handle those easy cases as ECF_CONST|ECF_LOOPING_CONST_OR_PURE or ECF_PURE|ECF_LOOPING_CONST_OR_PURE The harder cases aren't handled right now, I'd hope they can be handled incrementally. I wonder whether we shouldn't emit a warning for the gcc.dg/c23-attr-{reproducible,unsequenced}-5.c cases, while the standard clearly specifies that composite types should union the attributes and it is what GCC implements for decades, for ?: that feels dangerous for the new attributes, it would be much better to be conservative on say (cond ? unsequenced_function : normal_function) (args) There is no diagnostics on incorrect [[unsequenced]] or [[reproducible]] function definitions, while I think diagnosing non-const static/TLS declarations in the former could be easy, the rest feels hard. E.g. the const/pure discovery can just punt on everything it doesn't understand, but complete diagnostics would need to understand it. 2024-08-31 Jakub Jelinek <jakub@redhat.com> PR c/116130 gcc/ * doc/extend.texi (unsequenced, reproducible): Document new function type attributes. * calls.cc (flags_from_decl_or_type): Handle "unsequenced noptr" and "reproducible noptr" attributes. gcc/c-family/ * c-attribs.cc (c_common_gnu_attributes): Add entries for "unsequenced", "reproducible", "unsequenced noptr" and "reproducible noptr" attributes. (handle_unsequenced_attribute): New function. (handle_reproducible_attribute): Likewise. * c-common.h (handle_unsequenced_attribute): Declare. (handle_reproducible_attribute): Likewise. * c-lex.cc (c_common_has_attribute): Return 202311 for standard unsequenced and reproducible attributes. gcc/c/ * c-decl.cc (handle_std_unsequenced_attribute): New function. (handle_std_reproducible_attribute): Likewise. (std_attributes): Add entries for "unsequenced" and "reproducible" attributes. (c_warn_type_attributes): Add TYPE argument. Allow unsequenced or reproducible attributes if it is FUNCTION_TYPE. (groktypename): Adjust c_warn_type_attributes caller. (grokdeclarator): Likewise. (finish_declspecs): Likewise. * c-parser.cc (c_parser_declaration_or_fndef): Likewise. * c-tree.h (c_warn_type_attributes): Add TYPE argument. gcc/testsuite/ * c-c++-common/attr-reproducible-1.c: New test. * c-c++-common/attr-reproducible-2.c: New test. * c-c++-common/attr-unsequenced-1.c: New test. * c-c++-common/attr-unsequenced-2.c: New test. * gcc.dg/c23-attr-reproducible-1.c: New test. * gcc.dg/c23-attr-reproducible-2.c: New test. * gcc.dg/c23-attr-reproducible-3.c: New test. * gcc.dg/c23-attr-reproducible-4.c: New test. * gcc.dg/c23-attr-reproducible-5.c: New test. * gcc.dg/c23-attr-reproducible-5-aux.c: New file. * gcc.dg/c23-attr-unsequenced-1.c: New test. * gcc.dg/c23-attr-unsequenced-2.c: New test. * gcc.dg/c23-attr-unsequenced-3.c: New test. * gcc.dg/c23-attr-unsequenced-4.c: New test. * gcc.dg/c23-attr-unsequenced-5.c: New test. * gcc.dg/c23-attr-unsequenced-5-aux.c: New file. * gcc.dg/c23-has-c-attribute-2.c: Add tests for unsequenced and reproducible attributes.
2024-08-28doc: Add Dhruv Matani to ContributorsJonathan Wakely1-0/+3
gcc/ChangeLog: * doc/contrib.texi (Contributors): Add Dhruv Matani.
2024-08-28testsuite: Add scan-ltrans-rtl* for use in dg-final [PR116140]Alex Coplan1-2/+2
This extends the scan-ltrans-tree* helpers to create RTL variants. This is needed to check the behaviour of an RTL pass under LTO. gcc/ChangeLog: PR libstdc++/116140 * doc/sourcebuild.texi: Document ltrans-rtl value of kind for scan-<kind>-dump*. gcc/testsuite/ChangeLog: PR libstdc++/116140 * lib/scanltranstree.exp (scan-ltrans-rtl-dump): New. (scan-ltrans-rtl-dump-not): New. (scan-ltrans-rtl-dump-dem): New. (scan-ltrans-rtl-dump-dem-not): New. (scan-ltrans-rtl-dump-times): New.
2024-08-27Extend check-function-bodies to allow label and directivesH.J. Lu1-3/+6
As PR target/116174 shown, we may need to verify labels and the directive order. Extend check-function-bodies to support matched output lines to allow label and directives. gcc/ * doc/sourcebuild.texi (check-function-bodies): Add an optional argument for matched output lines. gcc/testsuite/ * gcc.target/i386/pr116174.c: Use check-function-bodies. * lib/scanasm.exp (parse_function_bodies): Append the line if $up_config(matched) matches the line. (check-function-bodies): Add an argument for matched. Set up_config(matched) to $matched. Append the expected line without $config(line_prefix) to function_regexp if it starts with ".L". Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-23doc: Specifically link to GPL v3.0 for GM2Gerald Pfeifer1-1/+1
The generic GPL link redirects to GPL v3.0 right now, but may redirect to a different version at one point. Specifically link to the version we are using gcc: * doc/gm2.texi (License): Specifically link to GPL v3.0
2024-08-22PR target/116365: Add user-friendly arguments to --param ↵Jennifer Schmitz1-8/+6
aarch64-autovec-preference=N The param aarch64-autovec-preference=N is a useful tool for testing auto-vectorisation in GCC as it allows the user to force a particular strategy. So far, N could be a numerical value between 0 and 4. This patch replaces the numerical values by more user-friendly names to distinguish the options. The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. Ok for mainline? Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com> gcc/ PR target/116365 * config/aarch64/aarch64-opts.h (enum aarch64_autovec_preference_enum): New enum. * config/aarch64/aarch64.cc (aarch64_cmp_autovec_modes): Change numerical to enum values. (aarch64_autovectorize_vector_modes): Change numerical to enum values. (aarch64_vector_costs::record_potential_advsimd_unrolling): Change numerical to enum values. * config/aarch64/aarch64.opt: Change param type to enum. * doc/invoke.texi: Update documentation. gcc/testsuite/ PR target/116365 * gcc.target/aarch64/autovec_param_asimd-only.c: New test. * gcc.target/aarch64/autovec_param_default.c: Likewise. * gcc.target/aarch64/autovec_param_prefer-asimd.c: Likewise. * gcc.target/aarch64/autovec_param_prefer-sve.c: Likewise. * gcc.target/aarch64/autovec_param_sve-only.c: Likewise. * gcc.target/aarch64/neoverse_v1_2.c: Update parameter value. * gcc.target/aarch64/neoverse_v1_3.c: Likewise. * gcc.target/aarch64/sve/cond_asrd_1.c: Likewise. * gcc.target/aarch64/sve/cond_cnot_4.c: Likewise. * gcc.target/aarch64/sve/cond_unary_5.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_5.c: Likewise. * gcc.target/aarch64/sve/cond_xorsign_2.c: Likewise. * gcc.target/aarch64/sve/pr98268-1.c: Likewise. * gcc.target/aarch64/sve/pr98268-2.c: Likewise.
2024-08-20doc: Normalize reference to binutils version for C6XGerald Pfeifer1-1/+1
We generally do not use a hyphen between project name and version. gcc: * doc/install.texi (Specific) <c6x-*-*>: Normalize reference to binutils.
2024-08-19rtl: Enable the use of rtx values with int and mode attributesAndre Vieira1-0/+5
The 'code' part of a 'define_code_attr' refers to the type of the key, in other words, it uses a code_iterator to pick the 'value' from their (key "value") pair list. However, rtx_alloc_for_name requires a code_attribute to be used when the 'value' needs to be a type. In other words, no other type of attributes could be used, before this patch, to produce a rtx typed 'value'. This patch removes that restriction and allows the backend to use any kind of attribute as long as that attribute always produces a valid code typed 'value'. gcc/ChangeLog: * read-rtl.cc (rtx_reader::rtx_alloc_for_name): Allow all attribute types to produce code 'values'. (check_code_attribute): Rename ... (check_attribute_codes): ... to this. And change comments to refer to * doc/md.texi: Add paragraph to document that you can use int and mode attributes to produce codes.
2024-08-18doc: Tweak gm2 mailing list addressGerald Pfeifer1-1/+1
gcc: * doc/gm2.texi (Contributing): Tweak gm2 mailing list address.
2024-08-17doc: Tweak PIM4 linkGerald Pfeifer1-1/+1
gcc: * doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link.
2024-08-17doc: Tweak link to gm2 list archiveGerald Pfeifer1-1/+1
Without the trailing slash we incur a "301 Moved Permanently". gcc: * doc/gm2.texi (Community): Tweak link to gm2 list archive.
2024-08-12Initial support for AVX10.2Haochen Jiang3-3/+38
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Handle avx10.2. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_2_256_SET): New. (OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Add OPTION_MASK_ISA2_AVX10_2_256_UNSET. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Add OPTION_MASK_ISA2_AVX10_2_512_UNSET. (OPTION_MASK_ISA2_AVX10_2_256_UNSET): New. (OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto. (ix86_handle_option): Handle avx10.2-256 and avx10.2-512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_2_256 and FEATURE_AVX10_2_512. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avx10.2-256 and avx10.2-512. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVX10_2_256__ and __AVX10_2_512__. * config/i386/i386-isa.def (AVX10_2): Add DEF_PTA(AVX10_2_256) and DEF_PTA(AVX10_2_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.2-256 and -mavx10.2-512. (ix86_valid_target_attribute_inner_p): Handle avx10.2-256 and avx10.2-512. * config/i386/i386.opt: Add option -mavx10.2, -mavx10.2-256 and -mavx10.2-512. * config/i386/i386.opt.urls: Regenerated. * doc/extend.texi: Document avx10.2, avx10.2-256 and avx10.2-512. * doc/invoke.texi: Document -mavx10.2, -mavx10.2-256 and -mavx10.2-512. * doc/sourcebuild.texi: Document target avx10.2, avx10.2-256, avx10.2-512. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto.
2024-08-10Fix reference to the dom walker function in the documentationAndi Kleen1-2/+2
It is using a class now with a different name. gcc/ChangeLog: * doc/cfg.texi: Fix references to dom_walker.
2024-08-08AVR: Fix a typo in __builtin_avr_mask1 documentation.Georg-Johann Lay1-1/+1
gcc/ * doc/extend.texi (AVR Built-in Functions) <mask1>: Fix a typo.
2024-08-07rs6000, Add new overloaded vector shift builtin int128 variantsCarl Love1-0/+43
Add the signed __int128 and unsigned __int128 argument types for the overloaded built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro. For each of the new argument types add a testcase and update the documentation for the built-in. gcc/ChangeLog: * config/rs6000/altivec.md (vs<SLDB_lr>db_<mode>): Change define_insn iterator to VEC_IC. * config/rs6000/rs6000-builtins.def (__builtin_altivec_vsldoi_v1ti, __builtin_vsx_xxsldwi_v1ti, __builtin_altivec_vsldb_v1ti, __builtin_altivec_vsrdb_v1ti): New builtin definitions. * config/rs6000/rs6000-overload.def (vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro): New overloaded definitions. * doc/extend.texi (vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro): Add documentation for new overloaded built-ins. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vec-shift-double-runnable-int128.c: New test file.
2024-08-06c++: permit errors inside uninstantiated templates [PR116064]Patrick Palka1-1/+11
In recent versions of GCC we've been diagnosing more and more kinds of errors inside a template ahead of time. This is a largely good thing because it catches bugs, typos, dead code etc sooner. But if the template never gets instantiated then such errors are harmless and can be inconvenient to work around if say the code in question is third party and in maintenance mode. So it'd be handy to be able to prevent these template errors from rendering the entire TU uncompilable. (Note that such code is "ill-formed no diagnostic required" according the standard.) To that end this patch turns any errors issued within a template into permerrors associated with a new -Wtemplate-body flag so that they can be downgraded via e.g. -fpermissive or -Wno-error=template-body. If the template containing a downgraded error later needs to be instantiated, we'll issue an error then. But if the template never gets instantiated then the downgraded error won't affect validity of the rest of the TU. This is implemented via a diagnostic hook that gets called for each diagnostic, and which adjusts an error diagnostic appropriately if we detect it's occurring from a template context, and additionally flags the template as erroneous. For example the new testcase permissive-error1a.C gives: gcc/testsuite/g++.dg/template/permissive-error1a.C: In function 'void f()': gcc/testsuite/g++.dg/template/permissive-error1a.C:7:5: warning: increment of read-only variable 'n' [-Wtemplate-body] 7 | ++n; | ^ ... gcc/testsuite/g++.dg/template/permissive-error1a.C: In instantiation of 'void f() [with T = int]': gcc/testsuite/g++.dg/template/permissive-error1a.C:26:9: required from here 26 | f<int>(); | ~~~~~~^~ gcc/testsuite/g++.dg/template/permissive-error1a.C:5:6: error: instantiating erroneous template 5 | void f() { | ^ gcc/testsuite/g++.dg/template/permissive-error1a.C:7:5: note: first error appeared here 7 | ++n; // { | ^ ... PR c++/116064 gcc/c-family/ChangeLog: * c.opt (Wtemplate-body): New warning. gcc/cp/ChangeLog: * cp-tree.h (erroneous_templates_t): Declare. (erroneous_templates): Declare. (cp_seen_error): Declare. (seen_error): #define to cp_seen_error. * error.cc (get_current_template): Define. (relaxed_template_errors): Define. (cp_adjust_diagnostic_info): Define. (cp_seen_error): Define. (cxx_initialize_diagnostics): Set diagnostic_context::m_adjust_diagnostic_info. * module.cc (finish_module_processing): Don't write the module if it contains an erroneous template. * pt.cc (maybe_diagnose_erroneous_template): Define. (instantiate_class_template): Call it. (instantiate_decl): Likewise. gcc/ChangeLog: * diagnostic.cc (diagnostic_context::initialize): Set m_adjust_diagnostic_info. (diagnostic_context::report_diagnostic): Call m_adjust_diagnostic_info. * diagnostic.h (diagnostic_context::m_adjust_diagnostic_info): New data member. * doc/invoke.texi (-Wno-template-body): Document. (-fpermissive): Mention -Wtemplate-body. gcc/testsuite/ChangeLog: * g++.dg/ext/typedef-init.C: Downgrade error inside template to warning due to -fpermissive. * g++.dg/pr84492.C: Likewise. * g++.old-deja/g++.pt/crash51.C: Remove unneeded dg-options. * g++.dg/template/permissive-error1.C: New test. * g++.dg/template/permissive-error1a.C: New test. * g++.dg/template/permissive-error1b.C: New test. * g++.dg/template/permissive-error1c.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2024-08-06doc: Rephrase GM2 Limitations sectionGerald Pfeifer1-4/+3
gcc: * doc/gm2.texi (Limitations): Rephrase. Remove invalid link.
2024-08-02c++: Move -Wdangling-reference to -WextraMarek Polacek1-1/+2
Despite a number of mitigations (don't warn for std::span-like classes, lambdas, adding [[gnu::no_dangling]], etc.), the warning still seems to cause some grief. Let's move the warning to -Wextra, then. gcc/c-family/ChangeLog: * c.opt (Wdangling-reference): Move from -Wall to -Wextra. gcc/ChangeLog: * doc/invoke.texi: Document that -Wdangling-reference is enabled by -Wextra.
2024-08-01AArch64: Add Cortex-X925 core definition and cost modelTamar Christina1-1/+1
This adds a cost model and core definition for Cortex-X925. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (cortex-x925): New. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/tuning_models/cortexx925.h: New file. * config/aarch64/aarch64.cc: Use it. * doc/invoke.texi: Document it.
2024-08-01AArch64: Add Neoverse N3 and Cortex-A725 core definition and cost modelTamar Christina1-1/+2
This adds a cost model and core definition for Neoverse N3 and Cortex-A725. It also makes Cortex-A725 use the Neoverse N3 cost model. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (neoverse-n3, cortex-a725): New. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/tuning_models/neoversen3.h: New file. * config/aarch64/aarch64.cc: Use it. * doc/invoke.texi: Document it.
2024-08-01AArch64: Add Neoverse V3AE core definition and cost modelTamar Christina1-1/+1
This adds a cost model and core definition for Neoverse V3AE. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (neoverse-v3ae): New. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/tuning_models/neoversev3ae.h: New file. * config/aarch64/aarch64.cc: Use it. * doc/invoke.texi: Document it.
2024-08-01AArch64: Add Neoverse V3 core definition and cost modelTamar Christina1-0/+1
This adds a cost model and core definition for Neoverse V3. It also makes Cortex-X4 use the Neoverse V3 cost model. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (cortex-x4): Update. (neoverse-v3): New. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/tuning_models/neoversev3.h: New file. * config/aarch64/aarch64.cc: Use it. * doc/invoke.texi: Document it.
2024-08-01Add TARGET_MODE_CAN_TRANSFER_BITSRichard Biener2-0/+13
The following adds a target hook to specify whether regs of MODE can be used to transfer bits. The hook is supposed to be used for value-numbering to decide whether a value loaded in such mode can be punned to another mode instead of re-loading the value in the other mode and for SRA to decide whether MODE is suitable as container holding a value to be used in different modes. * target.def (mode_can_transfer_bits): New target hook. * target.h (mode_can_transfer_bits): New function wrapping the hook and providing default behavior. * doc/tm.texi.in: Update. * doc/tm.texi: Re-generate.
2024-07-31aarch64: Add march flags for +fp8 arch extensionsClaudio Bantaloukas1-0/+2
This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (fp8): New. * config/aarch64/aarch64.h (TARGET_FP8): Likewise. * doc/invoke.texi (AArch64 Options): Document new -march flags and extensions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/fp8.c: New test.
2024-07-30RISC-V: Add basic support for the Zacas extensionGianluca Guida1-0/+10
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q (64/128 bit cas for rv32/64) will be added in a future patch. Extension: https://github.com/riscv/riscv-zacas Ratification: https://jira.riscv.org/browse/RVS-680 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zacas extension. * config/riscv/arch-canonicalize: Make zacas imply zaamo. * config/riscv/riscv.opt: Add zacas. * config/riscv/sync.md (zacas_atomic_cas_value<mode>): New pattern. (atomic_compare_and_swap<mode>): Use new pattern for compare-and-swap ops. (zalrsc_atomic_cas_value_strong<mode>): Rename atomic_cas_value_strong. * doc/sourcebuild.texi: Add Zacas documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zacas testsuite infra support. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Remove zacas to continue to test the lr/sc pairs. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test. * gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test. Co-authored-by: Patrick O'Neill <patrick@rivosinc.com> Tested-by: Andrea Parri <andrea@rivosinc.com> Signed-Off-By: Gianluca Guida <gianluca@rivosinc.com>
2024-07-30AVR: Propose to use attribute signal(n) via AVR-LibC's ISR_N.Georg-Johann Lay1-7/+23
gcc/ * doc/extend.texi (AVR Function Attributes): Propose to use attribute signal(n) via AVR-LibC's ISR_N from avr/interrupt.h
2024-07-29doc: Improve punctuation and grammar in -fdiagnostics-format docsJonathan Wakely1-2/+3
The hyphen can be misunderstood to mean "emitted to -" i.e. stdout. Refer to both forms by name, rather than using "the former" for one and referring to the other by name. gcc/ChangeLog: * doc/invoke.texi (Diagnostic Message Formatting Options): Replace hyphen with a new sentence. Replace "the former" with the actual value.
2024-07-28AVR target 116056 - Support attribute signal(n), interrupt(n) and noblock.Georg-Johann Lay2-0/+45
This patch adds support for arguments to the signal and interrupt function attributes. It allows to specify the ISR by means of the associated IRQ number, in extension to the current attributes that require to specify the ISR name like "__vector_1" as (assembly) name for the function. The new feature is more convenient, e.g. when the ISR is implemented by a class method or in a namespace. There is no requirement that the ISR is externally visible. The syntax is like: __attribute__((signal(1, 2, ...), signal(3, 4, ...))) [static] void isr_function (void) { // Code } Moreover, this patch adds support for the "noblock" function attribute to let an ISR start with a SEI instruction. Attribute "signal" together with "noblock" behaves like "interrupt" but without imposing a specific function name or visibility like "interrupt" does. PR target/116056 gcc/ * config/avr/avr.h (machine_function) <is_noblock>: New field. * config/avr/avr-c.cc (avr_cpu_cpp_builtins) <__HAVE_SIGNAL_N__>: New built-in macro. * config/avr/avr.cc (avr_declare_function_name): New function. (avr_attribute_table) <noblock>: New function attribute>. <signal, interrupt>: Allow any number of args. (avr_insert_attributes): Check validity of "signal" and "interrupt" arguments. (avr_foreach_function_attribute, avr_interrupt_signal_function) (avr_isr_number, avr_asm_isr_alias, avr_handle_isr_attribute) (avr_noblock_function_p): New static functions. (avr_interrupt_function): New from avr_interrupt_function_p. Adjust callers. (avr_signal_function): New from avr_signal_function_p. Adjust callers. (avr_set_current_function): Only diagnose non-__vector ISR names when "signal" or "interrupt" attribute has no args. Set cfun->machine->is_noblock. Warn about "noblock" in non-ISR functions. (struct avr_fun_cookie): New. (avr_expand_prologue, avr_asm_function_end_prologue): Handle "noblock". * config/avr/elf.h (ASM_DECLARE_FUNCTION_NAME): New define. * config/avr/avr-protos.h (avr_declare_function_name): New proto. * doc/extend.texi (AVR Function Attributes): Document signal(num) and interrupt(num). * doc/invoke.texi (AVR Built-in Macros) <__HAVE_SIGNAL_N__>: Document. gcc/testsuite/ * gcc.target/avr/torture/signal_n-1.c: New test. * gcc.target/avr/torture/signal_n-2.c: New test. * gcc.target/avr/torture/signal_n-3.c: New test. * gcc.target/avr/torture/signal_n-4.cpp: New test.
2024-07-25rtl-ssa: Define INCLUDE_ARRAYRichard Sandiford1-0/+1
g:72fbd3b2b2a497dbbe6599239bd61c5624203ed0 added a use of std::array without explicitly forcing <array> to be included. That didn't cause problems in my local builds but understandably did for some people. gcc/ * doc/rtl.texi: Document the need to define INCLUDE_ARRAY before including rtl-ssa.h. * rtl-ssa.h: Likewise (in comment). * config/aarch64/aarch64-cc-fusion.cc: Add INCLUDE_ARRAY. * config/aarch64/aarch64-early-ra.cc: Likewise. * config/riscv/riscv-avlprop.cc: Likewise. * config/riscv/riscv-vsetvl.cc: Likewise. * fwprop.cc: Likewise. * late-combine.cc: Likewise. * pair-fusion.cc: Likewise. * rtl-ssa/accesses.cc: Likewise. * rtl-ssa/blocks.cc: Likewise. * rtl-ssa/changes.cc: Likewise. * rtl-ssa/functions.cc: Likewise. * rtl-ssa/insns.cc: Likewise. * rtl-ssa/movement.cc: Likewise.
2024-07-25doc: Document -O1 as the preferred level for large machine-generated codeSam James1-0/+5
At -O1, the intention is that we compile things in a "reasonable" amount of time (ditto memory use). In particular, we try to especially avoid optimizations which scale poorly on pathological cases, as is the case for large machine-generated code. Recommend -O1 for large machine-generated code, as has been informally done on bugs for a while now. This applies (broadly speaking) for both large machine-generated functions but also to a lesser extent repetitive small-but-still-not-tiny functions from a generator program. gcc/ChangeLog: PR middle-end/114855 * doc/invoke.texi (Optimize options): Mention machine-generated code for -O1.
2024-07-24optabs/rs6000: Rename iorc and andc to iorn and andnAndrew Pinski1-4/+4
When I was trying to add an scalar version of iorc and andc, the optab that got matched was for and/ior with the mode of csi and cdi instead of iorc and andc optabs for si and di modes. Since csi/cdi are the complex integer modes, we need to rename the optabs to be without c there. This changes c to n which is a neutral and known not to be first letter of a mode. Bootstrapped and tested on x86_64 and powerpc64le. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def: s/iorc/iorn/. s/andc/andn/ for the code. * config/rs6000/rs6000-string.cc (expand_cmp_vec_sequence): Update to iorn. * config/rs6000/rs6000.md (andc<mode>3): Rename to ... (andn<mode>3): This. (iorc<mode>3): Rename to ... (iorn<mode>3): This. * doc/md.texi: Update documentation for the rename. * internal-fn.def (BIT_ANDC): Rename to ... (BIT_ANDN): This. (BIT_IORC): Rename to ... (BIT_IORN): This. * optabs.def (andc_optab): Rename to ... (andn_optab): This. (iorc_optab): Rename to ... (iorn_optab): This. * gimple-isel.cc (gimple_expand_vec_cond_expr): Update for the renamed internal functions, ANDC/IORC to ANDN/IORN. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-07-24modula2: Add GNU flex as a build and install prerequisite.Gaius Mulley1-0/+4
gcc/ChangeLog: * doc/install.texi (GM2-prerequisite): Add GNU flex. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-07-23doc: add missing @option for musttailMarek Polacek1-2/+2
gcc/ChangeLog: * doc/extend.texi: Add missing @option.
2024-07-23Add documentation for musttail attributeAndi Kleen1-2/+23
gcc/ChangeLog: PR c/83324 * doc/extend.texi: Document [[musttail]]
2024-07-23install.texi (gcn): Suggest newer commit for NewlibTobias Burnus1-3/+3
Newlib 4.4.0 lacks two commits: 7dd4eb1db (2024-03-25) to fix device console output for GFX10/GFX11 and ed50a50b9 (2024-04-04) to make the added lock.h compilable with C++. This commit mentiones now also the second commit. gcc/ChangeLog: * doc/install.texi (amdgcn-x-amdhsa): Suggest newer git version for newlib.
2024-07-22Add -mcpu=power11 support.Michael Meissner1-1/+1
This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. This patch allows GCC to be configured with the --with-cpu=power11 and --with-tune=power11 options. This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. 2024-07-22 Michael Meissner <meissner@linux.ibm.com> gcc/ * config.gcc (powerpc*-*-*): Add support for power11. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11. (power11 cpu): Add power11 definition. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. * config/rs6000/power10.md (all reservations): Add power11 support. gcc/testsuite/ * gcc.target/powerpc/power11-1.c: New test. * gcc.target/powerpc/power11-2.c: Likewise. * gcc.target/powerpc/power11-3.c: Likewise.
2024-07-22middle-end: Implement conditonal store vectorizer pattern [PR115531]Tamar Christina2-0/+9
This adds a conditional store optimization for the vectorizer as a pattern. The vectorizer already supports modifying memory accesses because of the pattern based gather/scatter recognition. Doing it in the vectorizer allows us to still keep the ability to vectorize such loops for architectures that don't have MASK_STORE support, whereas doing this in ifcvt makes us commit to MASK_STORE. Concretely for this loop: void foo1 (char *restrict a, int *restrict b, int *restrict c, int n, int stride) { if (stride <= 1) return; for (int i = 0; i < n; i++) { int res = c[i]; int t = b[i+stride]; if (a[i] != 0) res = t; c[i] = res; } } today we generate: .L3: ld1b z29.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x2, x5, lsl 2] ld1w z30.s, p7/z, [x1, x5, lsl 2] cmpne p15.b, p6/z, z29.b, #0 sel z30.s, p15, z30.s, z31.s st1w z30.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 which in gimple is: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect_t_20.12_74 = .MASK_LOAD (vectp.10_72, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; vect_res_11.17_80 = VEC_COND_EXPR <mask__34.16_79, vect_t_20.12_74, vect_res_18.9_68>; .MASK_STORE (vectp_c.18_81, 32B, loop_mask_67, vect_res_11.17_80); A MASK_STORE is already conditional, so there's no need to perform the load of the old values and the VEC_COND_EXPR. This patch makes it so we generate: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; .MASK_STORE (vectp_c.18_81, 32B, mask__34.16_79, vect_res_18.9_68); which generates: .L3: ld1b z30.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x1, x5, lsl 2] cmpne p7.b, p7/z, z30.b, #0 st1w z31.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 gcc/ChangeLog: PR tree-optimization/115531 * tree-vect-patterns.cc (vect_cond_store_pattern_same_ref): New. (vect_recog_cond_store_pattern): New. (vect_vect_recog_func_ptrs): Use it. * target.def (conditional_operation_is_expensive): New. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Document it. * targhooks.cc (default_conditional_operation_is_expensive): New. * targhooks.h (default_conditional_operation_is_expensive): New.
2024-07-20Revert "Add documentation for musttail attribute"Andi Kleen1-23/+2
This reverts commit 56f824cc206ff00d466aaeb11211d8005c4668bc.
2024-07-20doc: Remove documentation of two obsolete spec stringsAndré Maroneze1-3/+0
gcc: * doc/invoke.texi (Spec Files): Remove documentation of obsolete spec strings "predefines" and "signed_char".
2024-07-19Add documentation for musttail attributeAndi Kleen1-2/+23
gcc/ChangeLog: PR c/83324 * doc/extend.texi: Document [[musttail]]
2024-07-19AVR: Support new built-in function __builtin_avr_mask1.Georg-Johann Lay1-0/+17
gcc/ * config/avr/builtins.def (MASK1): New DEF_BUILTIN. * config/avr/avr.cc (avr_rtx_costs_1): Handle rtx costs for expressions like __builtin_avr_mask1. (avr_init_builtins) <uintQI_ftype_uintQI_uintQI>: New tree type. (avr_expand_builtin) [AVR_BUILTIN_MASK1]: Diagnose unexpected forms. (avr_fold_builtin) [AVR_BUILTIN_MASK1]: Handle case. * config/avr/avr.md (gen_mask1): New expand helper. (mask1_0x01_split, mask1_0x80_split, mask1_0xfe_split): New insn-and-split. (*mask1_0x01, *mask1_0x80, *mask1_0xfe): New insns. * doc/extend.texi (AVR Built-in Functions) <__builtin_avr_mask1>: Document new built-in function. gcc/testsuite/ * gcc.target/avr/torture/builtin-mask1.c: New test.
2024-07-18Doc: Add Standard-Names ustrunc and sstrunc for integer modesPan Li1-0/+12
This patch would like to add the doc for the Standard-Names ustrunc and sstrunc, include both the scalar and vector integer modes. gcc/ChangeLog: * doc/md.texi: Add Standard-Names ustrunc and sstrunc. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-18[aarch64] Document rewriting of -march=native to -mcpu=nativeKyrylo Tkachov1-1/+4
Commit dd9e5f4db2debf1429feab7f785962ccef6e0dbd changed -march=native to treat it as -mcpu=native if no other mcpu or mtune option was given. It would make sense to document this, especially if we try to persuade compilers like LLVM to take the same approach. This patch documents that behaviour. Bootstrapped and tested on aarch64-none-linux-gnu. Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com> gcc/ChangeLog: * doc/invoke.texi (AArch64 Options): Document rewriting of -march=native to -mcpu=native.
2024-07-14c, objc: Add -Wunterminated-string-initializationAlejandro Colomar1-1/+19
Warn about the following: char s[3] = "foo"; Initializing a char array with a string literal of the same length as the size of the array is usually a mistake. Rarely is the case where one wants to create a non-terminated character sequence from a string literal. In some cases, for writing faster code, one may want to use arrays instead of pointers, since that removes the need for storing an array of pointers apart from the strings themselves. char *log_levels[] = { "info", "warning", "err" }; vs. char log_levels[][7] = { "info", "warning", "err" }; This forces the programmer to specify a size, which might change if a new entry is later added. Having no way to enforce null termination is very dangerous, however, so it is useful to have a warning for this, so that the compiler can make sure that the programmer didn't make any mistakes. This warning catches the bug above, so that the programmer will be able to fix it and write: char log_levels[][8] = { "info", "warning", "err" }; This warning already existed as part of -Wc++-compat, but this patch allows enabling it separately. It is also included in -Wextra, since it may not always be desired (when unterminated character sequences are wanted), but it's likely to be desired in most cases. Since Wc++-compat now includes this warning, the test has to be modified to expect the text of the new warning too, in <gcc.dg/Wcxx-compat-14.c>. Link: https://lists.gnu.org/archive/html/groff/2022-11/msg00059.html Link: https://lists.gnu.org/archive/html/groff/2022-11/msg00063.html Link: https://inbox.sourceware.org/gcc/36da94eb-1cac-5ae8-7fea-ec66160cf413@gmail.com/T/ PR c/115185 gcc/c-family/ChangeLog: * c.opt: Add -Wunterminated-string-initialization. gcc/c/ChangeLog: * c-typeck.cc (digest_init): Separate warnings about character arrays being initialized as unterminated character sequences with string literals, from -Wc++-compat, into a new warning, -Wunterminated-string-initialization. gcc/ChangeLog: * doc/invoke.texi: Document the new -Wunterminated-string-initialization. gcc/testsuite/ChangeLog: * gcc.dg/Wcxx-compat-14.c: Adapt the test to match the new text of the warning, which doesn't say anything about C++ anymore. * gcc.dg/Wunterminated-string-initialization.c: New test. Acked-by: Doug McIlroy <douglas.mcilroy@dartmouth.edu> Acked-by: Mike Stump <mikestump@comcast.net> Reviewed-by: Sandra Loosemore <sloosemore@baylibre.com> Reviewed-by: Martin Uecker <uecker@tugraz.at> Signed-off-by: Alejandro Colomar <alx@kernel.org> Reviewed-by: Marek Polacek <polacek@redhat.com>
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