Initial support for AVX10.2

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features): Handle
	avx10.2.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX10_2_256_SET): New.
	(OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto.
	(OPTION_MASK_ISA2_AVX10_1_256_UNSET):
	Add OPTION_MASK_ISA2_AVX10_2_256_UNSET.
	(OPTION_MASK_ISA2_AVX10_1_512_UNSET):
	Add OPTION_MASK_ISA2_AVX10_2_512_UNSET.
	(OPTION_MASK_ISA2_AVX10_2_256_UNSET): New.
	(OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto.
	(ix86_handle_option): Handle avx10.2-256 and avx10.2-512.
	* common/config/i386/i386-cpuinfo.h (enum processor_features):
	Add FEATURE_AVX10_2_256 and FEATURE_AVX10_2_512.
	* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for
	avx10.2-256 and avx10.2-512.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
	__AVX10_2_256__ and __AVX10_2_512__.
	* config/i386/i386-isa.def (AVX10_2): Add DEF_PTA(AVX10_2_256)
	and DEF_PTA(AVX10_2_512).
	* config/i386/i386-options.cc (isa2_opts): Add -mavx10.2-256 and
	-mavx10.2-512.
	(ix86_valid_target_attribute_inner_p): Handle avx10.2-256 and
	avx10.2-512.
	* config/i386/i386.opt: Add option -mavx10.2, -mavx10.2-256 and
	-mavx10.2-512.
	* config/i386/i386.opt.urls: Regenerated.
	* doc/extend.texi: Document avx10.2, avx10.2-256 and avx10.2-512.
	* doc/invoke.texi: Document -mavx10.2, -mavx10.2-256 and
	-mavx10.2-512.
	* doc/sourcebuild.texi: Document target avx10.2, avx10.2-256,
	avx10.2-512.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Ditto.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/sse-12.c: Ditto.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.

3 files changed, 38 insertions, 3 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index ae1ada3..0ea7a87 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7466,6 +7466,21 @@ Enable/disable the generation of the AVX10.1 instructions.
 @itemx no-avx10.1-512
 Enable/disable the generation of the AVX10.1 512 bit instructions.
 
+@cindex @code{target("avx10.2")} function attribute, x86
+@item avx10.2
+@itemx no-avx10.2
+Enable/disable the generation of the AVX10.2 instructions.
+
+@cindex @code{target("avx10.2-256")} function attribute, x86
+@item avx10.2-256
+@itemx no-avx10.2-256
+Enable/disbale the generation of the AVX10.2 instructions.
+
+@cindex @code{target("avx10.2-512")} function attribute, x86
+@item avx10.2-512
+@itemx no-avx10.2-512
+Enable/disable the generation of the AVX10.2 512 bit instructions.
+
 @cindex @code{target("cld")} function attribute, x86
 @item cld
 @itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 27539a0..32b772d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1480,7 +1480,8 @@ See RS/6000 and PowerPC Options.
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 -mavx10.2-256
+-mavx10.2-512
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -35704,6 +35705,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @opindex mavx10.1-512
 @itemx -mavx10.1-512
+@need 200
+@opindex mavx10.2
+@itemx -mavx10.2
+@need 200
+@opindex mavx10.2-256
+@itemx -mavx10.2-256
+@need 200
+@opindex mavx10.2-512
+@itemx -mavx10.2-512
 These switches enable the use of instructions in the MMX, SSE,
 AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES,
 PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -35714,8 +35724,9 @@ WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD,
 AVX512VPOPCNTDQ, AVX512VNNI, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8,
 AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT,
 CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512,
-SM4, APX_F, USER_MSR, AVX10.1 or CLDEMOTE extended instruction sets.  Each has
-a corresponding @option{-mno-} option to disable use of these instructions.
+SM4, APX_F, USER_MSR, AVX10.1, AVX10.2 or CLDEMOTE extended instruction sets.
+Each has a corresponding @option{-mno-} option to disable use of these
+instructions.
 
 These extensions are also available as built-in functions: see
 @ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index d5c48e6..1a31f00 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2584,6 +2584,15 @@ Target supports the execution of @code{avx10.1} instructions.
 @item avx10.1-512
 Target supports the execution of @code{avx10.1-512} instructions.
 
+@item avx10.2
+Target supports the execution of @code{avx10.2} instructions.
+
+@item avx10.2-256
+Target supports the execution of @code{avx10.2} instructions.
+
+@item avx10.2-512
+Target supports the execution of @code{avx10.2-512} instructions.
+
 @item avx2
 Target supports compiling @code{avx2} instructions.