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2015-11-19Fix typo in doc/gty.texiDavid Malcolm1-2/+2
gcc/ChangeLog: * doc/gty.texi (Support for inheritance): Fix missing parentheses in example. From-SVN: r230609
2015-11-18avr-mcus.def: Add new avr4 devices atmega48pb and atmega88pb.Pitchumani Sivanupandi1-2/+2
* config/avr/avr-mcus.def: Add new avr4 devices atmega48pb and atmega88pb. Add new avr5 devices ata5791, ata8210, ata8510, atmega168pb and atmega328pb. * doc/avr-mmcu.texi: Regenerate. From-SVN: r230562
2015-11-18regrename.h (struct du_head): Add target_data_1 and target_data_2 fields.Bernd Schmidt1-1/+9
* regrename.h (struct du_head): Add target_data_1 and target_data_2 fields. * regrename.c (create_new_chain): Clear entire struct after allocating. * config/i386/i386.opt (mmitigate-rop): New option. * doc/invoke.texi (mmitigate-rop): Document. * config/i386/i386.c: Include "regrename.h". (ix86_rop_should_change_byte_p, reg_encoded_number, ix86_get_modrm_for_rop, set_rop_modrm_reg_bits, ix86_mitigate_rop): New static functions. (ix86_reorg): Call ix86_mitigate_rop if -fmitigate-rop. * config/i386/i386.md (attr "modrm_class"): New. (cmp<mode>_ccno_1, mov<mode>_xor, movstrict<mode>_xor, x86_mov<mode>cc_0_m1. x86_mov<mode>cc_0_m1_se) (x86_mov<mode>cc_0_m1_neg): Override modrm_class attribute. From-SVN: r230543
2015-11-17re PR c/48568 (Missing documentation for __attribute__((visibility ↵Sandra Loosemore1-0/+9
("protected"))) on variables.) 2015-11-17 Sandra Loosemore <sandra@codesourcery.com> PR 48568 * doc/extend.texi (Common Function Attributes) [visibility]: Add cross-references to matching variable and type attributes. (Common Variable Attributes) [visibility]: Add missing entry. From-SVN: r230498
2015-11-17Make builtin_vectorized_function take a combined_fnRichard Sandiford2-3/+11
This patch replaces the fndecl argument to builtin_vectorized_function with a combined_fn and gets the vectoriser to call it for internal functions too. The patch also moves vectorisation of machine-specific built-ins to a new hook, builtin_md_vectorized_function. Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnu and powerpc64-linux-gnu. gcc/ * target.def (builtin_vectorized_function): Take a combined_fn (in the form of an unsigned int) rather than a function decl. (builtin_md_vectorized_function): New. * targhooks.h (default_builtin_vectorized_function): Replace the fndecl argument with an unsigned int. (default_builtin_md_vectorized_function): Declare. * targhooks.c (default_builtin_vectorized_function): Replace the fndecl argument with an unsigned int. (default_builtin_md_vectorized_function): New function. * doc/tm.texi.in (TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION): New hook. * doc/tm.texi: Regenerate. * tree-vect-stmts.c (vectorizable_function): Update call to builtin_vectorized_function, also passing internal functions. Call builtin_md_vectorized_function for target-specific builtins. * config/aarch64/aarch64-protos.h (aarch64_builtin_vectorized_function): Replace fndecl argument with an unsigned int. * config/aarch64/aarch64-builtins.c: Include case-cfn-macros.h. (aarch64_builtin_vectorized_function): Update after above changes. Use CASE_CFN_*. * config/arm/arm-protos.h (arm_builtin_vectorized_function): Replace fndecl argument with an unsigned int. * config/arm/arm-builtins.c: Include case-cfn-macros.h (arm_builtin_vectorized_function): Update after above changes. Use CASE_CFN_*. * config/i386/i386.c: Include case-cfn-macros.h (ix86_veclib_handler): Take a combined_fn rather than a built_in_function. (ix86_veclibabi_svml, ix86_veclibabi_acml): Likewise. Use mathfn_built_in rather than calling builtin_decl_implicit directly. (ix86_builtin_vectorized_function) Update after above changes. Use CASE_CFN_*. * config/rs6000/rs6000.c: Include case-cfn-macros.h (rs6000_builtin_vectorized_libmass): Replace fndecl argument with a combined_fn. Use CASE_CFN_*. Use mathfn_built_in rather than calling builtin_decl_implicit directly. (rs6000_builtin_vectorized_function): Update after above changes. Use CASE_CFN_*. Move BUILT_IN_MD to... (rs6000_builtin_md_vectorized_function): ...this new function. (TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION): Define. From-SVN: r230491
2015-11-17Add null identifiers to genmatchRichard Sandiford1-0/+5
This patch adds a null identifier that can never match anything and can never be generated. It is only valid in operator lists and fors. Later patches will add uses of it. The idea is to allow operator lists for maths functions that have four entries: - float built-in - double built-in - long double built-in - internal function Not all maths functions have an associated internal function, and for those the final operator will be "null". Any simplification that tries to use a null substitution will be skipped. Tested on x86_64-linux-gnu, aarch64-linux-gnu and arm-linux-gnueabi. gcc/ * doc/match-and-simplify.texi: Document the "null" identifier. * genmatch.c (id_base::NULL_ID): New kind. (null_id): New variable. (get_operator): Add a parameter that says whether null identifiers are allowed. (contains_id): New function. (lower_for): Skip substitutions that would have a null_id in either the match or the result. (parser::parse_for): Allow the null identifier to be used. (parser::parse_operator_list): Likewise. (main): Initialize null_id. From-SVN: r230485
2015-11-17re PR other/56036 (Wrong indentation in multiple -O options explaination)Sandra Loosemore2-119/+150
2015-11-17 Sandra Loosemore <sandra@codesourcery.com> PR target/56036 * doc/invoke.texi (Option Summary): Add -mms-bitfields to x86 option list. (x86 Options): Add -mms-bitfields and -mno-ms-bitfields. Move discussion of the Microsoft structure layout details here from its former home in extend.texi. * doc/extend.texi (x86 Variable Attributes): Replace detailed discussion with pointer to its new location. Add cross-reference to corresponding type attributes. (x86 Type Attributes): Add cross-references to command-line options and variable attributes. From-SVN: r230467
2015-11-17[Patch AArch64] Add support for Cortex-A35James Greenhalgh1-2/+3
gcc/ * config/aarch64/aarch64-cores.def (cortex-a35): New. * config/aarch64/aarch64.c (cortexa35_tunings): New. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mcpu): Add Cortex-A35 From-SVN: r230458
2015-11-16re PR other/56036 (Wrong indentation in multiple -O options explaination)Thomas Preud'homme1-1/+1
2015-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com> PR 56036 * doc/invoke.texi (Optimize Options): Move @end table to the right place. From-SVN: r230452
2015-11-16re PR other/65129 (gcc manual index entry of __builtin_assume_aligned)Sandra Loosemore1-1/+1
2015-11-16 Sandra Loosemore <sandra@codesourcery.com> PR 65129 * doc/extend.texi (__builtin_assume_aligned): Fix formatting of return value. From-SVN: r230451
2015-11-16inline asm and multi-alternative constraintsDavid Wohlferd1-2/+3
* doc/md.texi ('#' and '*' constraint modifiers): Do not include these in the user documentation. (define_peephole2, define_split): Similarly. From-SVN: r230439
2015-11-16[Patch ARM] Add support for Cortex-A35James Greenhalgh1-1/+1
gcc/ * config/arm/arm-cores.def (cortex-a35): New. * config/arm/arm.c (arm_cortex_a35_tune): New. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Add cortex-a35. * config/arm/t-aprofile: Likewise. * doc/invoke.texi (-mcpu): Likewise. From-SVN: r230431
2015-11-16Add __attribute__((__simd__)) to GCC.Kirill Yukhin1-0/+16
gcc/ * omp-low.c (pass_omp_simd_clone::gate): If target allows - call without additional conditions. * doc/extend.texi (@item simd): New. gcc/c-family/ * c-common.c (handle_simd_attribute): New. (struct attribute_spec): Add entry for "simd". (handle_simd_attribute): New. gcc/c/ * c-parser.c (c_finish_omp_declare_simd): Look for "simd" attribute as well. Update error message. gcc/cp/ * parser.c (cp_parser_late_parsing_cilk_simd_fn_info): Look for "simd" attribute as well. Update error message. gcc/testsuite/ * c-c++-common/attr-simd.c: New test. * c-c++-common/attr-simd-2.c: New test. * c-c++-common/attr-simd-3.c: New test. From-SVN: r230422
2015-11-16re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not ↵Christian Bruel2-1/+10
available) 2015-11-16 Christian Bruel <christian.bruel@st.com> PR target/65837 * config/arm/arm-c.c (arm_cpu_builtins): Set or reset __ARM_FEATURE_CRYPTO, __VFP_FP__, __ARM_NEON__ (arm_pragma_target_parse): Change check for arm_cpu_builtins. undefine __ARM_FP. * config/arm/arm.c (arm_can_inline_p): Check FPUs. (arm_valid_target_attribute_rec): Handle -mfpu attribute target. * doc/invoke.texi (-mfpu=): Mention attribute and pragma. * doc/extend.texi (-mfpu=): Describe attribute. 2015-11-16 Christian Bruel <christian.bruel@st.com> PR target/65837 gcc.target/arm/lto/pr65837_0.c gcc.target/arm/attr-neon2.c gcc.target/arm/attr-neon.c gcc.target/arm/attr-neon-builtin-fail.c gcc.target/arm/attr-crypto.c From-SVN: r230408
2015-11-15remove conditional compilation of sdb debug infoTrevor Saunders2-2/+2
gcc/ChangeLog: 2015-11-14 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * defaults.h: New definition of SDB_DEBUGGING_INFO. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Adjust. * final.c (rest_of_clean_state): Remove check if SDB_DEBUGGING_INFO is defined. * function.c (number_blocks): Likewise. * output.h: Likewise. * sdbout.c: Likewise. * toplev.c (process_options): Likewise. From-SVN: r230390
2015-11-13[Patch,tree-optimization]: Add new path Splitting pass on tree ssaAjit Agarwal1-1/+15
representation * Makefile.in (OBJS): Add gimple-ssa-split-paths.o * common.opt (-fsplit-paths): New flag controlling path splitting. * doc/invoke.texi (fsplit-paths): Document. * opts.c (default_options_table): Add -fsplit-paths to -O2. * passes.def: Add split_paths pass. * timevar.def (TV_SPLIT_PATHS): New timevar. * tracer.c: Include "tracer.h" (ignore_bb_p): No longer static. (transform_duplicate): New function, broken out of tail_duplicate. (tail_duplicate): Use transform_duplicate. * tracer.h (ignore_bb_p): Declare (transform_duplicate): Likewise. * tree-pass.h (make_pass_split_paths): Declare. * gimple-ssa-split-paths.c: New file. * gcc.dg/tree-ssa/split-path-1.c: New test. Co-Authored-By: Jeff Law <law@redhat.com> From-SVN: r230364
2015-11-13constraints.md (we constraint): New constraint for 64-bit power9 vector support.Michael Meissner1-0/+29
[gcc] 2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (we constraint): New constraint for 64-bit power9 vector support. (wL constraint): New constraint for the element in a vector that can be addressed by the MFVSRLD instruction. * config/rs6000/rs6000-protos.h (convert_float128_to_int): Add declaration. (convert_int_to_float128): Likewise. (rs6000_generate_compare): Add support for ISA 3.0 (power9) hardware support for IEEE 128-bit floating point. (rs6000_expand_float128_convert): Likewise. (convert_float128_to_int): Likewise. (convert_int_to_float128): Likewise. * config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for ISA 3.0 hardware IEEE 128-bit floating point. (UNSPEC_IEEE128_MOVE): Likewise. (UNSPEC_IEEE128_CONVERT): Likewise. (FMA_F): Add support for IEEE 128-bit floating point hardware support. (Ff): Add support for DImode. (Fv): Likewise. (any_fix code iterator): New and updated iterators for IEEE 128-bit floating point hardware support. (any_float code iterator): Likewise. (s code attribute): Likewise. (su code attribute): Likewise. (az code attribute): Likewise. (uns code attribute): Likewise. (neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit floating point hardware support. (abs<mode>2, FLOAT128 iterator): Likewise. (add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit floating point hardware. (sub<mode>3, IEEE128 iterator): Likewise. (mul<mode>3, IEEE128 iterator): Likewise. (div<mode>3, IEEE128 iterator): Likewise. (copysign<mode>3, IEEE128 iterator): Likewise. (sqrt<mode>2, IEEE128 iterator): Likewise. (neg<mode>2, IEEE128 iterator): Likewise. (abs<mode>2, IEEE128 iterator): Likewise. (nabs<mode>2, IEEE128 iterator): Likewise. (fma<mode>4_hw, IEEE128 iterator): Likewise. (fms<mode>4_hw, IEEE128 iterator): Likewise. (nfma<mode>4_hw, IEEE128 iterator): Likewise. (nfms<mode>4_hw, IEEE128 iterator): Likewise. (extend<SFDF:mode><IEEE128:mode>2_hw): Likewise. (trunc<mode>df2_hw, IEEE128 iterator): Likewise. (trunc<mode>sf2_hw, IEEE128 iterator): Likewise. (fix_fixuns code attribute): Likewise. (float_floatuns code attribute): Likewise. (fix<uns>_<mode>si2_hw): Likewise. (fix<uns>_<mode>di2_hw): Likewise. (float<uns>_<mode>si2_hw): Likewise. (float<uns>_<mode>di2_hw): Likewise. (xscvqp<su>wz_<mode>): Likewise. (xscvqp<su>dz_<mode>): Likewise. (xscv<su>dqp_<mode): Likewise. (ieee128_mfvsrd): Likewise. (ieee128_mfvsrwz): Likewise. (ieee128_mtvsrw): Likewise. (ieee128_mtvsrd): Likewise. (trunc<mode>df2_odd): Likewise. (cmp<mode>_h): Likewise. (128-bit GPR splitters): Don't split a 128-bit move that is a direct move between GPR and vector registers using ISA 3.0 direct move instructions. (<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer multiply-add instruction. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0 debugging. (rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we constraint. Disable the VSX<->GPR direct move helpers if we have the MFVSRLD and MTVSRDD instructions. (rs6000_secondary_reload_simple_move): Add support for doing vector direct moves directly without additional scratch registers if we have ISA 3.0 instructions. (rs6000_secondary_reload_direct_move): Update comments. (rs6000_output_move_128bit): Add support for ISA 3.0 vector instructions. * config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0 direct move instructions. (vsx_movti_64bit): Likewise. (vsx_extract_<mode>): Likewise. * config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New macros for ISA 3.0 direct move instructions. (TARGET_DIRECT_MOVE_128): Likewise. (TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add instruction. * doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL constraints. Update wa documentation to say not to use %x<n> on instructions that only take Altivec registers. [gcc/testsuite] 2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit hardware floating point support. * gcc.target/powerpc/direct-move-vector.c: New test for 128-bit vector direct move instructions. * gcc.target/powerpc/maddld.c: New test. From-SVN: r230342
2015-11-13md.texi (vec_cmp@var{m}@var{n}): New item.Ilya Enkovich1-1/+35
gcc/ * doc/md.texi (vec_cmp@var{m}@var{n}): New item. (vec_cmpu@var{m}@var{n}): New item. (vcond@var{m}@var{n}): Specify comparison is signed. (vcondu@var{m}@var{n}): New item. (vcond_mask_@var{m}@var{n}): New item. (maskload@var{m}@var{n}): New item. (maskstore@var{m}@var{n}): New item. From-SVN: r230290
2015-11-12[PATCH] gcc.c: new macro POST_LINK_SPECS to be able to add additionalAndris Pavenis2-0/+10
steps after linking * gcc.c (POST_LINK_SPEC): Define if not already defined. (LINK_COMMAND_SPEC): Use post_link. (post_link_spec): New, initialize to POST_LINK_SPEC. (post_link): Initialize new static spec. * doc/tm.texi.in (POST_LINK_SPEC): Document. * doc/tm.texi: Regenerated. From-SVN: r230287
2015-11-12Add initial qualcomm support.Jim Wilson1-1/+2
gcc/ * config/aarch64/aarch64-cores.def (qdf24xx): New. * config/aarch64/aarch64-tune.md: Regenerated. * config/arm/arm-cores.def (qdf24xx): New. * config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated. * config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support. * doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx". (ARM Options/-mtune); Likewise. From-SVN: r230268
2015-11-11arc-common.c (arc_handle_option): Handle ARCv2 options.Claudiu Zissulescu1-2/+71
2015-11-11 Claudiu Zissulescu <claziss@synopsys.com> * common/config/arc/arc-common.c (arc_handle_option): Handle ARCv2 options. * config/arc/arc-opts.h: Add ARCv2 CPUs. * config/arc/arc-protos.h (arc_secondary_reload_conv): Prototype. * config/arc/arc.c (arc_secondary_reload): Handle subreg (reg) situation, and store instructions with large offsets. (arc_secondary_reload_conv): New function. (arc_init): Add ARCv2 options. (arc_conditional_register_usage): Select the proper register usage for ARCv2 processors. (arc_handle_interrupt_attribute): ILINK2 is only valid for ARCv1 architecture. (arc_compute_function_type): Likewise. (arc_print_operand): Handle new ARCv2 punctuation characters. (arc_return_in_memory): ARCv2 ABI returns in registers up to 16 bytes. (workaround_arc_anomaly, arc_asm_insn_p, arc_loop_hazard): New function. (arc_reorg, arc_hazard): Use it. * config/arc/arc.h (TARGET_CPU_CPP_BUILTINS): Define __HS__ and __EM__. (ASM_SPEC): Add ARCv2 options. (TARGET_NORM): ARC HS has norm instructions by default. (TARGET_OPTFPE): Use optimized floating point emulation for ARC HS. (TARGET_AT_DBR_CONDEXEC): Only for ARC600 family. (TARGET_EM, TARGET_HS, TARGET_V2, TARGET_MPYW, TARGET_MULTI): Define. (SIGNED_INT16, TARGET_MPY, TARGET_ARC700_MPY, TARGET_ANY_MPY): Likewise. (TARGET_ARC600_FAMILY, TARGET_ARCOMPACT_FAMILY): Likewise. (TARGET_LP_WR_INTERLOCK): Likewise. * config/arc/arc.md (commutative_binary_mult_comparison_result_used, movsicc_insn) (mulsi3, mulsi3_600_lib, mulsidi3, mulsidi3_700, mulsi3_highpart) (umulsi3_highpart_i, umulsi3_highpart_int, umulsi3_highpart) (umulsidi3, umulsidi3_700, cstoresi4, simple_return, p_return_i): Use it for ARCv2. (mulhisi3, mulhisi3_imm, mulhisi3_reg, umulhisi3, umulhisi3_imm) (umulhisi3_reg, umulhisi3_reg, mulsi3_v2, nopv, bswapsi2) (prefetch, divsi3, udivsi3 modsi3, umodsi3, arcset, arcsetltu) (arcsetgeu, arcsethi, arcsetls, reload_*_load, reload_*_store) (extzvsi): New pattern. * config/arc/arc.opt: New ARCv2 options. * config/arc/arcEM.md: New file. * config/arc/arcHS.md: Likewise. * config/arc/constraints.md (C3p): New constraint, accepts 1 and 2 values. (Cm2): A signed 9-bit integer constant constraint. (C62): An unsigned 6-bit integer constant constraint. (C16): A signed 16-bit integer constant constraint. * config/arc/predicates.md (mult_operator): Add ARCv2 processort. (short_const_int_operand): New predicate. * config/arc/t-arc-newlib: Add ARCv2 multilib options. * doc/invoke.texi: Add documentation for -mcpu=<archs/arcem> -mcode-density and -mdiv-rem. From-SVN: r230156
2015-11-10nvptx.opt (moptimize): New flag.Nathan Sidwell1-1/+6
* config/nvptx/nvptx.opt (moptimize): New flag. * config/nvptx/nvptx.c (nvptx_option_override): Set nvptx_optimize default. (nvptx_optimize_inner): New. (nvptx_process_pars): Call it when optimizing. * doc/invoke.texi (Nvidia PTX Options): Document -moptimize. From-SVN: r230137
2015-11-10[optabs][ifcvt][1/3] Define negcc, notcc optabsKyrylo Tkachov1-0/+15
* ifcvt.c (noce_try_inverse_constants): New function. (noce_process_if_block): Call it. * optabs.h (emit_conditional_neg_or_complement): Declare prototype. * optabs.def (negcc_optab, notcc_optab): Declare. * optabs.c (emit_conditional_neg_or_complement): New function. * doc/tm.texi (Standard Names): Document negcc, notcc names. From-SVN: r230089
2015-11-09Change behavior of -fsched-verbose optionNikolai Bozhenov1-6/+1
* haifa-sched.c (setup_sched_dump): Don't redirect output to stderr. * common.opt (-fsched-verbose): Set default value to 1. * invoke.texi (-fsched-verbose): Update the option's description. From-SVN: r230061
2015-11-09rs6000.opt (-mpower9-fusion): Add new switches for ISA 3.0 (power9).Michael Meissner1-6/+42
2015-11-09 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.opt (-mpower9-fusion): Add new switches for ISA 3.0 (power9). (-mpower9-vector): Likewise. (-mpower9-dform): Likewise. (-mpower9-minmax): Likewise. (-mtoc-fusion): Likewise. (-mmodulo): Likewise. (-mfloat128-hardware): Likewise. * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add option mask for ISA 3.0 (power9). (POWERPC_MASKS): Add new ISA 3.0 switches. (power9 cpu): Add power9 cpu. * config/rs6000/rs6000.h (ASM_CPU_POWER9_SPEC): Add support for power9. (ASM_CPU_SPEC): Likewise. (EXTRA_SPECS): Likewise. * config/rs6000/rs6000-opts.h (enum processor_type): Add PROCESSOR_POWER9. * config/rs6000/rs6000.c (power9_cost): Initial cost setup for power9. (rs6000_debug_reg_global): Add support for power9 fusion. (rs6000_setup_reg_addr_masks): Cache mode size. (rs6000_option_override_internal): Until real power9 tuning is added, use -mtune=power8 for -mcpu=power9. (rs6000_setup_reg_addr_masks): Do not allow pre-increment, pre-decrement, or pre-modify on SFmode/DFmode if we allow the use of Altivec registers. (rs6000_option_override_internal): Add support for ISA 3.0 switches. (rs6000_loop_align): Add support for power9 cpu. (rs6000_file_start): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (insn_must_be_first_in_group): Likewise. (insn_must_be_last_in_group): Likewise. (force_new_group): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power9. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define _ARCH_PWR9 if power9 support is available. * config/rs6000/aix61.h (ASM_CPU_SPEC): Add power9. * config/rs6000/aix53.h (ASM_CPU_SPEC): Likewise. * configure.ac: Determine if the assembler supports the ISA 3.0 instructions. * config.in (HAVE_AS_POWER9): Likewise. * configure: Regenerate. * doc/invoke.texi (RS/6000 and PowerPC Options): Document ISA 3.0 switches. From-SVN: r230031
2015-11-09i386: Add address spaces for fs/gs segments and tlsRichard Henderson1-2/+45
* config/i386/i386-c.c (ix86_target_macros): Define __SEG_FS, __SEG_GS, __SEG_TLS. (ix86_register_pragmas): Register address spaces __seg_fs, __seg_gs, __seg_tls. * config/i386/i386-protos.h (enum ix86_address_seg): Remove. (ADDR_SPACE_SEG_FS, ADDR_SPACE_SEG_GS, ADDR_SPACE_SEG_TLS): New. (struct ix86_address): Use addr_space_t instead of ix86_address_seg. * config/i386/i386.c (ix86_decompose_address): Likewise. (ix86_legitimate_address_p): Likewise. (memory_address_length): Likewise. Check mem address space too. (ix86_print_operand): Use ix86_print_operand_address_as. (ix86_print_operand_address_as): Rename from ix86_print_operand_address, add new addr_space_t parameter. Validate that either the parameter or the ix86_address segment is default address space. Handle ADDR_SPACE_SEG_TLS. (ix86_print_operand_address): New. (ix86_addr_space_subset_p, TARGET_ADDR_SPACE_SUBSET_P): New. (ix86_addr_space_convert, TARGET_ADDR_SPACE_CONVERT): New. (ix86_addr_space_debug, TARGET_ADDR_SPACE_DEBUG): New. (ix86_addr_space_zero_address_valid): New. (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): New. * config/i386/i386.h (DEFAULT_TLS_SEG_REG): Use addr_space_t constants. * config/i386/rdos.h (DEFAULT_TLS_SEG_REG): Likewise. * config/i386/predicates.md (address_no_seg_operand): Likewise. (vsib_address_operand): Likewise. (address_mpx_no_base_operand): Likewise. (address_mpx_no_index_operand): Likewise. * doc/extend.texi (x86 Named Address Spaces): New section. * gcc.target/i386/addr-space-1.c: New test. * gcc.target/i386/addr-space-2.c: New test. * gcc.target/i386/addr-space-3.c: New test. From-SVN: r230003
2015-11-09Add hook for modifying debug info for address spacesRichard Henderson2-0/+7
* dwarf2out.c (modified_type_die): Pass the address space number through TARGET_ADDR_SPACE_DEBUG to produce the dwarf address class. * target.def (TARGET_ADDR_SPACE_DEBUG): New. * targhooks.c (default_addr_space_debug): New. * targhooks.h (default_addr_space_debug): Declare. * doc/tm.texi.in (TARGET_ADDR_SPACE_DEBUG): Mark it. * doc/tm.texi: Rebuild. From-SVN: r230000
2015-11-09Add TARGET_ADDR_SPACE_ZERO_ADDRESS_VALIDRichard Henderson2-0/+7
* gimple.c (check_loadstore): Return false when 0 is a valid address. * fold-const.c (const_unop) [ADDR_SPACE_CONVERT_EXPR]: Do not fold null when 0 is valid in the source address space. * target.def (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): New. * targhooks.c (default_addr_space_zero_address_valid): New. * targhooks.h (default_addr_space_zero_address_valid): Declare. * doc/tm.texi.in (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Mark it. * doc/tm.texi: Rebuild. From-SVN: r229999
2015-11-08Merge of the scalar-storage-order branch.Eric Botcazou2-12/+79
From-SVN: r229965
2015-11-06inline asm and multi-alternative constraintsDavid Wohlferd1-3/+17
* doc/md.texi (multi-alternative constraints): Don't document alternatives inherently tied to reload for the user documentation. From-SVN: r229897
2015-11-06[Patch ARM] Unified assembler in ARM state.Ramana Radhakrishnan1-4/+3
gcc/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates. * config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe. (arm_output_multireg_pop): Likewise. (output_move_double): Likewise. (output_move_quad): Likewise. (output_return_instruction): Likewise. (arm_print_operand): Remove support for %( and %. print modifiers. (arm_output_shift): Make unified asm. (arm_declare_function_name): Likewise. * config/arm/arm.h (TARGET_UNIFIED_ASM): Delete. (ASM_APP_OFF): Adjust. (ASM_OUTPUT_REG_PUSH): Undo special casing for TARGET_ARM. (ASM_OUTPUT_REG_POP): Likewise. * config/arm/arm.md: Adjust uses of %., %(, %) * config/arm/sync.md: Likewise. * config/arm/thumb2.md: Likewise. * config/arm/ldmstm.md: Regenerate. * config/arm/arm.opt (masm-unified-syntax): Do not special case Thumb. * doc/invoke.texi (masm-unified-syntax): Update documentation. gcc/testsuite/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gcc.target/arm/combine-movs.c: * gcc.target/arm/interrupt-1.c: * gcc.target/arm/interrupt-2.c: * gcc.target/arm/unaligned-memcpy-4.c: From-SVN: r229875
2015-11-06aarch64-builtins.c: Builtins for rsqrt and rsqrtf.Benedikt Huber1-0/+12
2015-11-06 Benedikt Huber <benedikt.huber@theobroma-systems.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> * config/aarch64/aarch64-builtins.c: Builtins for rsqrt and rsqrtf. * config/aarch64/aarch64-protos.h: Declare. * config/aarch64/aarch64-simd.md: Matching expressions for frsqrte and frsqrts. * config/aarch64/aarch64-tuning-flags.def: Added recip_sqrt. * config/aarch64/aarch64.c: New functions. Emit rsqrt estimation code when applicable. * config/aarch64/aarch64.md: Added enum entries. * config/aarch64/aarch64.opt: Added option -mlow-precision-recip-sqrt. * testsuite/gcc.target/aarch64/rsqrt_asm_check_common.h: Common macros for assembly checks. * testsuite/gcc.target/aarch64/rsqrt_asm_check_negative_1.c: Make sure frsqrts and frsqrte are not emitted. * testsuite/gcc.target/aarch64/rsqrt_asm_check_1.c: Make sure frsqrts and frsqrte are emitted. * testsuite/gcc.target/aarch64/rsqrt_1.c: Functional tests for rsqrt. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Co-Authored-By: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> From-SVN: r229866
2015-11-05PR c++/67942 - diagnose placement new buffer overflowMartin Sebor1-1/+8
gcc/ * invoke.texi (-Wplacement-new): Document new option. * gcc/testsuite/g++.dg/warn/Wplacement-new-size.C: New test. gcc/c-family/ * c.opt (-Wplacement-new): New option. gcc/cp/ * cp/init.c (warn_placement_new_too_small): New function. (build_new_1): Call it. gcc/testsuite/ * g++.dg/warn/Wplacement-new-size.C: New test. From-SVN: r229827
2015-11-05target.def (goacc.dim_limit): New hook.Nathan Sidwell2-0/+7
* target.def (goacc.dim_limit): New hook. * targhooks.h (default_goacc_dim_limit): Declare. * doc/tm.texi.in (TARGET_GOACC_DIM_LIMIT): Add. * doc/tm.texi: Rebuilt. * omp-low.h (get_oacc_fn_dim_size, get_oacc_ifn_dim_arg): Declare. * omp-low.c (get_oacc_fn_dim_size, get_oacc_ifn_dim_arg): New. (default_goacc_dim_limit): New. * config/nvptx/nvptx.c (PTX_VECTOR_LENGTH, PTX_WORKER_LENGTH): New. (nvptx_goacc_dim_limit) New. (TARGET_GOACC_DIM_LIMIT): Override. * tree-vrp.c: Include omp-low.h, target.h. (extract_range_basic): Add handling for IFN_GOACC_DIM_SIZE & IFN_GOACC_DIM_POS. From-SVN: r229809
2015-11-04internal-fn.def (GOACC_REDUCTION): New.Nathan Sidwell2-0/+11
* internal-fn.def (GOACC_REDUCTION): New. * internal-fn.h (enum ifn_goacc_reduction_kind): New. * internal-fn.c (expand_GOACC_REDUCTION): New. * target.def (goacc.reduction): New OpenACC hook. * targhooks.h (default_goacc_reduction): Declare. * doc/tm.texi.in: Add TARGET_GOACC_REDUCTION. * doc/tm.texi: Rebuilt. * omp-low.c (oacc_get_reduction_array_id, oacc_max_threads, scan_sharing_clauses): Remove oacc reduction handling here. (lower_rec_input_clauses): Don't handle OpenACC reductions here. (oacc_lower_reduction_var_helper): Delete. (lower_oacc_reductions): New. (lower_reduction_clauses): Don't handle OpenACC reductions here. (lower_oacc_head_tail): Call lower_oacc_reductions. (oacc_gimple_assign, oacc_init_reduction_array, oacc_initialize_reduction_data, oacc_finalize_reduction_data, oacc_process_reduction_data): Delete. (lower_omp_target): Remove old OpenACC reduction handling. Insert dummy OpenACC gang reduction for reductions at outer level. (oacc_loop_xform_head_tail): Transform IFN_GOACC_REDUCTION. (default_goacc_reduction): New. (execute_oacc_device_lower): Handle IFN_GOACC_REDUCTION. From-SVN: r229767
2015-10-30Makefile.in (OBJS): Add multiple_target.o.Evgeny Stupachenko1-0/+13
2015-10-30 Evgeny Stupachenko <evstupac@gmail.com> gcc/ * Makefile.in (OBJS): Add multiple_target.o. * attrib.c (make_attribute): Moved from config/i386/i386.c * config/i386/i386.c (make_attribute): Deleted. * multiple_target.c (create_dispatcher_calls): New. (get_attr_len): Ditto. (get_attr_str): Ditto. (separate_attrs): Ditto. (is_valid_asm_symbol): Ditto. (create_new_asm_name): Ditto. (create_target_clone): Ditto. (expand_target_clones): Ditto. (ipa_target_clone): Ditto. (ipa_dispatcher_calls): Ditto. * passes.def (pass_target_clone): Two new ipa passes. * tree-pass.h (make_pass_target_clone): Ditto. * doc/extend.texi (target_clones): New attribute description. gcc/c-family/ * c-common.c (handle_target_clones_attribute): New. (c_common_attribute_table): Add handle_target_clones_attribute. (handle_always_inline_attribute): Add check on target_clones attribute. (handle_target_attribute): Ditto. gcc/testsuite/ * gcc.dg/mvc1.c: New test for multiple targets cloning. * gcc.dg/mvc2.c: Ditto. * gcc.dg/mvc3.c: Ditto. * gcc.dg/mvc4.c: Ditto. * gcc.dg/mvc5.c: Ditto. * gcc.dg/mvc6.c: Ditto. * gcc.dg/mvc7.c: Ditto. * g++.dg/ext/mvc1.C: Ditto. * g++.dg/ext/mvc2.C: Ditto. * g++.dg/ext/mvc3.C: Ditto. * g++.dg/ext/mvc4.C: Ditto. From-SVN: r229595
2015-10-30Re: [Docs] Reword the documentation for -fdump-rtl-James Greenhalgh1-10/+12
gcc/ * doc/invoke.texi (fdump-rtl-@var{pass}): Clarify relationship between pass numbering and execution order. From-SVN: r229584
2015-10-30libgcc changes for AMD znver1.Venkataramanan Kumar1-0/+3
2015-10-30 Venkataramanan Kumar <venkataramanan.kumar@amd.com> * config/i386/i386.c (get_builtin_code_for_version): Set priority for PROCESSOR_ZNVER1. (enum processor_model): Add M_AMDFAM17H_znver1. (struct arch_names_table): Likewise. * doc/extend.texi: ADD znver1. 2015-10-30 Venkataramanan Kumar <venkataramanan.kumar@amd.com> * config/i386/cpuinfo.c (enum processor_types): Add AMDFAM17H. (processor_subtypes): Add znver1. (get_amd_cpu): Detect znver1. From-SVN: r229575
2015-10-29rs6000.c (rs6000_init_libfuncs): Split libfunc setup into 3 functions...Michael Meissner2-6/+39
[gcc] 2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_init_libfuncs): Split libfunc setup into 3 functions: init_float128_ibm, init_float128_ieee, and rs6000_init_libfuncs. If -mfloat128, add IFmode functions for all of the traditional names that TFmode uses for handling IEEE extended double. If -mfloat128, add KFmode functions for all of the emulation functions. If -mabi=ieeelongdouble and -mfloat128, make TFmode use the same emulation functions as KFmode. (init_float128_ibm): Likewise. (init_float128_ieee): Likewise. (rs6000_generate_compare): For IEEE 128-bit floating point comparisons, call the unordered comparison function instead of the ordered comparison function. (rs6000_expand_float128_convert): Deal with operands that are memory operands. Restructure the code to use a switch statement on the mode. Add support for TFmode defaulting to either IBM extended double or IEEE 128-bit floating point. If the underlying types are the same, use a move instead of a conversion function. (TARGET_C_MODE_FOR_SUFFIX): Define 'q' and 'Q' as the suffix to use for IEEE 128-bit floating point constants with -mfloat128. (rs6000_c_mode_for_suffix): Likewise. (TARGET_INVALID_BINARY_OP): Do not allow inter-mixing of IEEE 128-bit floating point with IBM extended double floating point. (rs6000_invalid_binary_op): Likewise. (rs6000_gen_le_vsx_permute): On little endian systems generate a ROTATE insn instead of VEC_SELECT for IEEE 128-bit floating point types that can go in vector registers. (chain_contains_only_swaps): Properly swap IEEE 128-bit floating point types that can go in vector registers on little endian PowerPC systems. (mark_swaps_for_removal): Likewise. (rs6000_analyze_swaps): Likewise. (rs6000_mangle_type): Use U10__float128 for IEEE 128-bit floating point. * config/rs6000/rs6000.md (FLOAT128_SFDFTF): Delete iterator, rework IEEE 128-bit floating point insns to deal with TFmode being either IBM extended double or IEEE 128-bit floating point. (IFKF): Likewise. (IBM128): Update iterator to add condition that the mode is IBM extended double. (IEEE128): New iterator for IEEE 128-bit floating point. (TFIFKF): Rename TFIFKF iterator to FLOAT128. (FLOAT128): Likewise. (signbit<mode>2): FLOAT128_IBM_P condition test moved into IBM128 iterator. (neg<mode>2): Replace TFIFKF iterator with FLOAT128. Add support for TFmode being IEEE 128-bit floating point. Use IEEE128 iterator instead of hard coding TFmode or KFmode. (negtf2_internal): Likewise. (neg<mode>2_internal): Likewise. (abs<mode>2): Likewise. (abstf2_internal): Likewise. (abs<mode>2_internal): Likewise. (ieee_128bit_neg<mode>2): Likewise. (ieee_128bit_neg<mode>2_internal): Likewise. (ieee_128bit_abs<mode>2): Likewise. (ieee_128bit_abs<mode>2_internal): Likewise. (ieee_128bit_nabs<mode>2): Likewise. (ieee_128bit_nabs<mode>2_internal): Likewise. (extendiftf2): Add explicit conversions between 128-bit floating point types. Drop the old conversions that had become unwieldy. (extend<FLOAT128_SFDFTF:mode><IFKF:mode>2): Likewise. (extendifkf2): Likewise. (trunc<IFKF:mode><FLOAT128_SFDFTF:mode>2): Likewise. (extendtfkf2): Likewise. (fix_trunc<IFKF:mode><SDI:mode>2): Likewise. (trunciftf2): Likewise. (fixuns_trunc<IFKF:mode><SDI:mode>2): Likewise. (truncifkf2): Likewise. (float<SDI:mode><IFKF:mode>2): Likewise. (trunckftf2): Likewise. (floatuns<SDI:mode><IFKF:mode>2): Likewise. (trunctfif2): Likewise. (FP iterator): Allow TFmode to be IEEE 128-bit floating point. (extenddftf2): Rework 128-bit floating point conversions to properly handle -mabi=ieeelongdouble. Merge IFmode, TFmode, and KFmode expanders into one function. (extenddf<mode>2): Likewise. (extenddftf2_fprs): Likewise. (extenddf<mode>2_fprs): Likewise. (extenddftf2_vsx): Likewise. (extenddf<mode>2_vsx): Likewise. (extendsftf2): Likewise. (extendsf<mode>2): Likewise. (trunctfdf2): Likewise. (trunc<mode>df2): Likewise. (trunctfdf2_internal1): Likewise. (trunc<mode>df2_internal1): Likewise. (trunctfdf2_internal2): Likewise. (trunc<mode>df2_internal2): Likewise. (trunctfsf2): Likewise. (trunc<mode>sf2): Likewise. (trunctfsf2_fprs): Likewise. (trunc<mode>sf2_fprs): Likewise. (floatsit2f): Likewise. (floatsi<mode>2): Likewise. (fix_trunc_helper): Likewise. (fix_trunc_helper<mode>): Likewise. (fix_trunctfsi2): Likewise. (fix_trunc<mode>si2): Likewise. (fix_trunctfsi2_fprs): Likewise. (fix_trunc<mode>si2_fprs): Likewise. (fix_trunctfsi2_internal): Likewise. (fix_trunc<mode>si2_internal): Likewise. (fix_trunctfdi2): Likewise. (fix_trunc<mode>di2): Likewise. (fixuns_trunctf<mode>2): Likewise. (fixuns_trunc<IEEE128:mode><SDI:mode>2): Likewise. (floatditf2): Likewise. (floatdi<mode>2): Likewise. (floatuns<mode>tf2): Likewise. (floatuns<SDI:mode><IEEE128:mode>): Likewise. (cmptf_internal1): Use a mode iterator to add support for both types (IFmode, TFmode) that support IBM extended double. (cmp<mode>_internal1): Likewise. (cmptf_internal2): Likewise. (cmp<mode>_internal2): Likewise. * doc/extend.texi (Floating Types): Document __ibm128 and __float128 on PowerPC. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mfloat128 and -mno-float128. [gcc/testsuite] 2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/float128-call.c: New test for -mfloat128 on PowerPC. * gcc.target/powerpc/float128-mix.c: Likewise. From-SVN: r229547
2015-10-28common.opt (fchecking): New flag controlling flag_checking.Richard Biener1-1/+7
2015-10-28 Richard Biener <rguenther@suse.de> * common.opt (fchecking): New flag controlling flag_checking. * passes.c (verify_curr_properties): Drop DEBUG_FUNCTION. * timevar.c (timer::print): Adjust output. * doc/invoke.texi (fchecking): Document. From-SVN: r229480
2015-10-27internal-fn.def (IFN_GOACC_DIM_SIZE, [...]): New.Nathan Sidwell1-5/+7
* internal-fn.def (IFN_GOACC_DIM_SIZE, IFN_GOACC_DIM_POS, IFN_GOACC_LOOP): New. * internal-fn.h (enum ifn_unique_kind): Add IFN_UNIQUE_OACC_FORK, IFN_UNIQUE_OACC_JOIN, IFN_UNIQUE_OACC_HEAD_MARK, IFN_UNIQUE_OACC_TAIL_MARK. (enum ifn_goacc_loop_kind): New. * internal-fn.c (expand_UNIQUE): Add IFN_UNIQUE_OACC_FORK, IFN_UNIQUE_OACC_JOIN cases. (expand_GOACC_DIM_SIZE, expand_GOACC_DIM_POS): New. (expand_GOACC_LOOP): New. * target-insns.def (oacc_dim_pos, oacc_dim_size): New. * omp-low.c: Include gimple-pretty-print.h. (struct oacc_loop): New. (enum oacc_loop_flags): New. (oacc_thread_numbers): New. (oacc_xform_loop): New. (new_oacc_loop_raw, new_oacc_loop_outer, new_oacc_loop, new_oacc_loop_routine, finish_oacc_loop, free_oacc_loop): New, (dump_oacc_loop_part, dump_oacc_loop, debug_oacc_loop): New, (oacc_loop_discover_walk, oacc_loop_sibling_nrevers, oacc_loop_discovery): New. (oacc_loop_xform_head_tail, oacc_loop_xform_loop, oacc_loop_process): New. (oacc_loop_fixed_partitions, oacc_loop_partition): New. (execute_oacc_device_lower): Discover & process loops. Process internal fns. * target.def (goacc.fork_join): Change sense of hook, clarify documentation. * doc/tm.texi: Regenerated. From-SVN: r229466
2015-10-27target-insns.def (oacc_fork, oacc_join): Define.Nathan Sidwell2-1/+11
* target-insns.def (oacc_fork, oacc_join): Define. * target.def (goacc.validate_dims): Adjust doc to avoid warning. (goacc.fork_join): New GOACC hook. * targhooks.h (default_goacc_fork_join): Declare. * omp-low.c (default_goacc_forkjoin): New. * doc/tm.texi.in (TARGET_GOACC_FORK_JOIN): Add. * doc/tm.texi: Regenerate. From-SVN: r229465
2015-10-27re PR rtl-optimization/67609 (Generates wrong code for SSE2 _mm_load_pd)Richard Henderson2-4/+26
PR rtl-opt/67609 * config/i386/i386.c (ix86_cannot_change_mode_class): Disallow narrowing subregs on SSE and MMX registers. * doc/tm.texi.in (CANNOT_CHANGE_MODE_CLASS): Clarify when subregs that appear to be sub-words of multi-register pseudos must be rejected. * doc/tm.texi: Regenerate. testsuite/ * gcc.target/i386/pr67609-2.c: New test. From-SVN: r229458
2015-10-27config.gcc: Handle --enable-fdpic.Daniel Jacobowitz2-0/+7
gcc/ChangeLog * config.gcc: Handle --enable-fdpic. * config/sh/constraints.md (Ccl): New constraint. * config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. * config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and __SH_FDPIC__. * config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls to library functions. * config/sh/sh-protos.h (function_symbol_result): New struct. (function_symbol): Return function_symbol_result. (sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New declarations. * config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer): Implement target hook. (TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p): Likewise. (sh_option_override): Force -fPIC if FDPIC is in effect. (sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC cases. (prepare_move_operands): Use FDPIC initial GOT register for TLS-related GOT access; inhibit cross-section address offset constants for FDPIC. (sh_assemble_integer): New function. (sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC PC-relative call sites. (expand_ashiftrt): Adapt invocation of function_symbol. (sh_expand_prologue): Inhibit PC-relative GOT address load for FDPIC. (nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC. (legitimize_pic_address): Resolve function symbols to function descriptors for FDPIC. Do not use GOT-relative addressing for local data that may be read-only on FDPIC. (sh_emit_storesi, sh_emit_storehi): New functions. (sh_trampoline_init): Generate FDPIC trampolines. (sh_function_ok_for_sibcall): Add TARGET_FDPIC check. (sh_expand_sym_label2reg): Don't assume sibcalls are local. (sh_output_mi_thunk): Generate FDPIC call. (function_symbol): Return function_symbol_result. For SFUNC_STATIC on FDPIC, generate call site labels to use PC-relative addressing rather than GOT-relative addressing. (sh_conditional_register_usage): Make PIC register fixed and call used when FDPIC is in effect. (sh_legitimate_constant_p): Impose FDPIC constant constraints. (sh_cannot_force_const_mem_p, sh_load_function_descriptor, sh_get_fdpic_reg_initial_val): New functions. * config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. (FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS, PIC_OFFSET_TABLE_REG_CALL_CLOBBERED, SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros. (DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and FDPIC_SELF_SPECS. (TRAMPOLINE_SIZE): Select trampoline size for FDPIC. (ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for FDPIC. (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case. * config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New constants. (calli_fdpic, call_valuei_fdpic, sibcalli_fdpic, sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic, sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic, sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC, symGOTOFFFUNCDESC2reg): New patterns. (udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3, *divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3, ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call, calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel, sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel, sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load, symGOTOFF2reg, block_move_real, block_lump_real, block_move_real_i4, block_lump_real_i4): Add support for FDPIC calls. (mulsi3, ic_invalidate_line, initialize_trampoline, call_pop, call_value_pop): Adjust for new function_symbol signature. * config/sh/sh.opt (-mfdpic): New option. * doc/install.texi (Options specification): Document --enable-fdpic. * doc/invoke.texi (SH Options): Document -mfdpic. include/ChangeLog: * longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH. libitm/ChangeLog: * config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling GTM_begin_transaction for compatibility with FDPIC. Co-Authored-By: Andrew Stubbs <ams@codesourcery.com> Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com> Co-Authored-By: Rich Felker <dalias@libc.org> From-SVN: r229438
2015-10-26target.def (TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P): New hook.Simon Dardis2-0/+12
gcc/ * target.def (TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P): New hook. * doc/tm.texi.in (TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P): Document. * doc/tm.texi: Regenerated. * reorg.c (dbr_schedule): Use new hook. * config/mips/mips.c (mips_no_speculation_in_delay_slots_p): New. testsuite/ * gcc.target/mips/ds-schedule-1.c: New. * gcc.target/mips/ds-schedule-2.c: New. From-SVN: r229383
2015-10-23* doc/install.texi (*-ibm-aix*): Additional information for AIX 7.1.David Edelsohn1-1/+11
From-SVN: r229263
2015-10-23Support for vectorizing conditional expressionsAlan Hayward1-0/+3
2015-10-23 Alan Hayward <alan.hayward@arm.com> gcc/ PR tree-optimization/65947 * tree-vect-loop.c (vect_is_simple_reduction_1): Find condition reductions. (vect_model_reduction_cost): Add condition reduction costs. (get_initial_def_for_reduction): Add condition reduction initial var. (vect_create_epilog_for_reduction): Add condition reduction epilog. (vectorizable_reduction): Condition reduction support. * tree-vect-stmts.c (vectorizable_condition): Add vect reduction arg * doc/sourcebuild.texi (Vector-specific attributes): Document vect_max_reduc gcc/testsuite PR tree-optimization/65947 * lib/target-supports.exp (check_effective_target_vect_max_reduc): Add. * gcc.dg/vect/pr65947-1.c: New test. * gcc.dg/vect/pr65947-2.c: New test. * gcc.dg/vect/pr65947-3.c: New test. * gcc.dg/vect/pr65947-4.c: New test. * gcc.dg/vect/pr65947-5.c: New test. * gcc.dg/vect/pr65947-6.c: New test. * gcc.dg/vect/pr65947-7.c: New test. * gcc.dg/vect/pr65947-8.c: New test. * gcc.dg/vect/pr65947-9.c: New test. * gcc.dg/vect/pr65947-10.c: New test. * gcc.dg/vect/pr65947-11.c: New test. From-SVN: r229245
2015-10-23Fix typo.Nick Clifton1-1/+1
From-SVN: r229213
2015-10-22Proposed doc update for Explicit Reg Vars 3/3David Wohlferd1-49/+60
* doc/extend.exp (Global Register Variables): Rewrite. From-SVN: r229188
2015-10-22msp430.opt: Add -msilicon-errata and -msilicon-errata-warn.Nick Clifton1-0/+11
* config/msp430/msp430.opt: Add -msilicon-errata and -msilicon-errata-warn. * config/msp430/msp430.h (ASM_SPEC): Pass new options on to assembler. * doc/invoke.texi: Document new options. From-SVN: r229177
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