rs6000.opt (-mpower9-fusion): Add new switches for ISA 3.0 (power9).

2015-11-09  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.opt (-mpower9-fusion): Add new switches for
	ISA 3.0 (power9).
	(-mpower9-vector): Likewise.
	(-mpower9-dform): Likewise.
	(-mpower9-minmax): Likewise.
	(-mtoc-fusion): Likewise.
	(-mmodulo): Likewise.
	(-mfloat128-hardware): Likewise.

	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add option
	mask for ISA 3.0 (power9).
	(POWERPC_MASKS): Add new ISA 3.0 switches.
	(power9 cpu): Add power9 cpu.

	* config/rs6000/rs6000.h (ASM_CPU_POWER9_SPEC): Add support for
	power9.
	(ASM_CPU_SPEC): Likewise.
	(EXTRA_SPECS): Likewise.

	* config/rs6000/rs6000-opts.h (enum processor_type): Add
	PROCESSOR_POWER9.

	* config/rs6000/rs6000.c (power9_cost): Initial cost setup for
	power9.
	(rs6000_debug_reg_global): Add support for power9 fusion.
	(rs6000_setup_reg_addr_masks): Cache mode size.
	(rs6000_option_override_internal): Until real power9 tuning is
	added, use -mtune=power8 for -mcpu=power9.
	(rs6000_setup_reg_addr_masks): Do not allow pre-increment,
	pre-decrement, or pre-modify on SFmode/DFmode if we allow the use
	of Altivec registers.
	(rs6000_option_override_internal): Add support for ISA 3.0
	switches.
	(rs6000_loop_align): Add support for power9 cpu.
	(rs6000_file_start): Likewise.
	(rs6000_adjust_cost): Likewise.
	(rs6000_issue_rate): Likewise.
	(insn_must_be_first_in_group): Likewise.
	(insn_must_be_last_in_group): Likewise.
	(force_new_group): Likewise.
	(rs6000_register_move_cost): Likewise.
	(rs6000_opt_masks): Likewise.

	* config/rs6000/rs6000.md (cpu attribute): Add power9.
	* config/rs6000/rs6000-tables.opt: Regenerate.

	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
	_ARCH_PWR9 if power9 support is available.

	* config/rs6000/aix61.h (ASM_CPU_SPEC): Add power9.
	* config/rs6000/aix53.h (ASM_CPU_SPEC): Likewise.

	* configure.ac: Determine if the assembler supports the ISA 3.0
	instructions.
	* config.in (HAVE_AS_POWER9): Likewise.
	* configure: Regenerate.

	* doc/invoke.texi (RS/6000 and PowerPC Options): Document ISA 3.0
	switches.

From-SVN: r230031

1 files changed, 42 insertions, 6 deletions

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dc9a4e7..2198db0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -949,8 +949,9 @@ See RS/6000 and PowerPC Options.
 -mquad-memory-atomic -mno-quad-memory-atomic @gol
 -mcompat-align-parm -mno-compat-align-parm @gol
 -mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
--mupper-regs -mno-upper-regs @gol
--mfloat128 -mno-float128}
+-mupper-regs -mno-upper-regs -mmodulo -mno-modulo @gol
+-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
+-mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector}
 
 @emph{RX Options}
 @gccoptlist{-m64bit-doubles  -m32bit-doubles  -fpu  -nofpu@gol
@@ -19311,8 +19312,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
 @samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
 @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
 @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
-@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{powerpc},
-@samp{powerpc64}, @samp{powerpc64le}, and @samp{rs64}.
+@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
+@samp{power9}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+and @samp{rs64}.
 
 @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
 @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
@@ -19332,7 +19334,8 @@ following options:
 -mpowerpc-gpopt  -mpowerpc-gfxopt  -msingle-float -mdouble-float @gol
 -msimple-fpu -mstring  -mmulhw  -mdlmzb  -mmfpgpr -mvsx @gol
 -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
--mquad-memory -mquad-memory-atomic}
+-mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
+-mpower9-fusion -mpower9-vector}
 
 The particular options set for any particular CPU varies between
 compiler versions, depending on what setting seems to produce optimal
@@ -19569,12 +19572,45 @@ If the @option{-mno-upper-regs} option is used, it turns off both
 @opindex mfloat128
 @opindex mno-float128
 Enable/disable the @var{__float128} keyword for IEEE 128-bit floating point
-and use software emulation for IEEE 128-bit floating point.
+and use either software emulation for IEEE 128-bit floating point or
+hardware instructions.
 
 The VSX instruction set (@option{-mvsx}, @option{-mcpu=power7}, or
 @option{-mcpu=power8}) must be enabled to use the @option{-mfloat128}
 option.
 
+@item -mfloat128-hardware
+@itemx -mno-float128-hardware
+@opindex mfloat128-hardware
+@opindex mno-float128-hardware
+Enable/disable using ISA 3.0 hardware instructions to support the
+@var{__float128} data type.
+
+@item -mmodulo
+@itemx -mno-modulo
+@opindex mmodulo
+@opindex mno-module
+Generate code that uses (does not use) the ISA 3.0 integer modulo
+instructions.  The @option{-mmodulo} option is enabled by default
+with the @option{-mcpu=power9} option.
+
+@item -mpower9-fusion
+@itemx -mno-power9-fusion
+@opindex mpower9-fusion
+@opindex mno-power9-fusion
+Generate code that keeps (does not keeps) some operations adjacent so
+that the instructions can be fused together on power9 and later
+processors.
+
+@item -mpower9-vector
+@itemx -mno-power9-vector
+@opindex mpower9-vector
+@opindex mno-power9-vector
+Generate code that uses (does not use) the vector and scalar
+instructions that were added in version 2.07 of the PowerPC ISA.  Also
+enable the use of built-in functions that allow more direct access to
+the vector instructions.
+
 @item -mfloat-gprs=@var{yes/single/double/no}
 @itemx -mfloat-gprs
 @opindex mfloat-gprs