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2013-04-26Makefile.in (toplev.o): Depend on diagnostic-color.h.Jakub Jelinek1-3/+4
* Makefile.in (toplev.o): Depend on diagnostic-color.h. * diagnostic-color.c (should_colorize): Remove _WIN32 version. (colorize_init): Add argument to _WIN32 version. * toplev.c: Include diagnostic-color.h. (process_options): Default to -fdiagnostics-color=auto if GCC_COLORS env var is in the environment. * common.opt (fdiagnostics-color=): Add Var and Init. * doc/invoke.texi (-fdiagnostics-color=): Document that if GCC_COLORS env var is in the environment, the default is auto rather than never. * lib/prune.exp: Add -fdiagnostics-color=never to TEST_ALWAYS_FLAGS. * lib/c-compat.exp (compat-use-alt-compiler, compat_setup_dfp): Handle -fdiagnostics-color=never option similarly to -fno-diagnostics-show-caret option. From-SVN: r198332
2013-04-25arm.c (neon_builtin_type_mode): Add T_V4HF.Kyrylo Tkachov1-0/+12
2013-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Julian Brown <julian@codesourcery.com> * config/arm/arm.c (neon_builtin_type_mode): Add T_V4HF. (TB_DREG): Add T_V4HF. (v4hf_UP): New macro. (neon_itype): Add NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW. (arm_init_neon_builtins): Handle NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW. Handle initialisation of V4HF. Adjust initialisation of reinterpret built-ins. (arm_expand_neon_builtin): Handle NEON_FLOAT_WIDEN, NEON_FLOAT_NARROW. (arm_vector_mode_supported_p): Handle V4HF. (arm_mangle_map): Handle V4HFmode. * config/arm/arm.h (VALID_NEON_DREG_MODE): Add V4HF. * config/arm/arm_neon_builtins.def: Add entries for vcvtv4hfv4sf, vcvtv4sfv4hf. * config/arm/neon.md (neon_vcvtv4sfv4hf): New pattern. (neon_vcvtv4hfv4sf): Likewise. * config/arm/neon-gen.ml: Handle half-precision floating point features. * config/arm/neon-testgen.ml: Handle Requires_FP_bit feature. * config/arm/arm_neon.h: Regenerate. * config/arm/neon.ml (type elts): Add F16. (type vectype): Add T_float16x4, T_floatHF. (type vecmode): Add V4HF. (type features): Add Requires_FP_bit feature. (elt_width): Handle F16. (elt_class): Likewise. (elt_of_class_width): Likewise. (mode_of_elt): Refactor. (type_for_elt): Handle F16, fix error messages. (vectype_size): Handle T_float16x4. (vcvt_sh): New function. (ops): Add entries for vcvt_f16_f32, vcvt_f32_f16. (string_of_vectype): Handle T_floatHF, T_float16, T_float16x4. (string_of_mode): Handle V4HF. * doc/arm-neon-intrinsics.texi: Regenerate. 2013-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * lib/target-supports.exp (check_effective_target_arm_neon_fp16_ok_nocache): New procedure. (check_effective_target_arm_neon_fp16_ok): Likewise. (add_options_for_arm_neon_fp16): Likewise. * gcc.target/arm/neon/vcvtf16_f32.c: New test. Generated. * gcc.target/arm/neon/vcvtf32_f16.c: Likewise. Co-Authored-By: Julian Brown <julian@codesourcery.com> From-SVN: r198298
2013-04-24* invoke.texi: Update expected date for C++1y.Jason Merrill1-1/+1
From-SVN: r198260
2013-04-24cpp.texi: Remove __GXX_EXPERIMENTAL_CXX1Y__.Paolo Carlini1-7/+0
2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * doc/cpp.texi: Remove __GXX_EXPERIMENTAL_CXX1Y__. /c-family 2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * c-cppbuiltin.c (c_cpp_builtins): Do not define __GXX_EXPERIMENTAL_CXX1Y__. /testsuite 2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/cpp1y/cxx1y_macro.C: Remove. From-SVN: r198258
2013-04-24cpp.texi: Document __GXX_EXPERIMENTAL_CXX1Y__.Paolo Carlini1-0/+7
2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * doc/cpp.texi: Document __GXX_EXPERIMENTAL_CXX1Y__. /c-family 2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * c-cppbuiltin.c (c_cpp_builtins): Define __GXX_EXPERIMENTAL_CXX1Y__. /testsuite 2013-04-24 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/cpp1y/cxx1y_macro.C: New. From-SVN: r198249
2013-04-23Add -flto-report-wpaAndi Kleen1-1/+5
-flto-report is useful, but it prints for every LTRANS pass and is very noisy and the main problem is often in WPA only. Add a new -flto-report-wpa option that is only printed for WPA. gcc/: 2013-04-22 Andi Kleen <ak@linux.intel.com> * common.opt (-flto-report-wpa): Add. * doc/invoke.texi (-flto-report-wpa): Add. * lto/lto.c (do_whole_program_analysis): Check for lto-report-wpa. (lto_main): dito. From-SVN: r198172
2013-04-22[Mid-end] Add TARGET_GIMPLE_FOLD_BUILTIN target hook.James Greenhalgh2-4/+15
gcc/ * coretypes.h (gimple_stmt_iterator_d): Forward declare. (gimple_stmt_iterator): New typedef. * gimple.h (gimple_stmt_iterator): Rename to... (gimple_stmt_iterator_d): ... This. * doc/tm.texi.in (TARGET_FOLD_BUILTIN): Detail restriction that trees be valid for GIMPLE and GENERIC. (TARGET_GIMPLE_FOLD_BUILTIN): New. * gimple-fold.c (gimple_fold_call): Call target hook gimple_fold_builtin. * hooks.c (hook_bool_gsiptr_false): New. * hooks.h (hook_bool_gsiptr_false): New. * target.def (fold_stmt): New. * doc/tm.texi: Regenerate. From-SVN: r198142
2013-04-17re PR web/45688 (Typo in __attribute__((version-id)) docs)Manuel López-Ibáñez1-1/+1
2013-04-17 Manuel López-Ibáñez <manu@gcc.gnu.org> PR 45688 * doc/extend.texi: Fix typo. From-SVN: r198028
2013-04-16invoke.texi (i386 Option): Reword -mstack-protector-guard description.Uros Bizjak1-3/+3
* doc/invoke.texi (i386 Option): Reword -mstack-protector-guard description. From-SVN: r198002
2013-04-15Use -z ignore instead of --as-needed on SolarisRainer Orth2-2/+4
* configure.ac (gcc_cv_ld_as_needed): Set gcc_cv_ld_as_needed_option, gcc_cv_no_as_needed_option. Use -z ignore, -z record on *-*-solaris2*. (HAVE_LD_AS_NEEDED): Update comment. (LD_AS_NEEDED_OPTION, LD_NO_AS_NEEDED_OPTION): Define. * configure: Regenerate. * config.in: Regenerate. * gcc.c (init_gcc_specs) [USE_LD_AS_NEEDED]: Use LD_AS_NEEDED_OPTION, LD_NO_AS_NEEDED_OPTION. * config/sol2.h [HAVE_LD_AS_NEEDED] (USE_LD_AS_NEEDED): Define. * doc/tm.texi.in (USE_LD_AS_NEEDED): Allow for --as-needed equivalents. Fix markup. * doc/tm.texi: Regenerate. From-SVN: r197964
2013-04-15i386.opt: New option mstack-protector-guard=.Andrew Hsieh1-1/+9
* config/i386/i386.opt: New option mstack-protector-guard=. * config/i386/i386-opts.h: Add enum stack_protector_guard. * config/i386/i386.h: Define TARGET_SSP_GLOBAL_GUARD and TARGET_SSP_TLS_GUARD. * config/i386/i386.c (ix86_option_override_internal): Set ix86_stack_protector_guard. * config/i386/i386.md (stack_protect_set): Enable for TARGET_SSP_TLS_GUARD only. (stack_protect_set_<mode>): Ditto. (stack_protect_test): Ditto. (stack_protect_test_<mode>): Ditto. * doc/invoke.texi (i386 Option): Document. From-SVN: r197963
2013-04-12tm.texi.in (LOOP_ALIGN): Remove loop note references.Steven Bosscher2-4/+4
* doc/tm.texi.in (LOOP_ALIGN): Remove loop note references. * doc/tm.texi: Regenerated. From-SVN: r197937
2013-04-12opts.c: Include diagnostic-color.h.Jakub Jelinek1-0/+71
* opts.c: Include diagnostic-color.h. (common_handle_option): Handle OPT_fdiagnostics_color_. * Makefile.in (OBJS-libcommon): Add diagnostic-color.o. (diagnostic.o, opts.o, pretty-print.o): Depend on diagnostic-color.h. (diagnostic-color.o): New. * common.opt (fdiagnostics-color, fdiagnostics-color=): New options. (diagnostic_color_rule): New enum. * dwarf2out.c (gen_producer_string): Don't print -fdiagnostics-color*. * langhooks.c (lhd_print_error_function): Add %r "locus" and %R around the location string. * diagnostic.def: Add 3rd argument to DEFINE_DIAGNOSTIC_KIND macros, either NULL, or color kind. * diagnostic-color.c: New file. * diagnostic-color.h: New file. * diagnostic-core.h (DEFINE_DIAGNOSTIC_KIND): Adjust macro for 3 arguments. * doc/invoke.texi (-fdiagnostics-color): Document. * pretty-print.h (pp_show_color): Define. (struct pretty_print_info): Add show_color field. * diagnostic.c: Include diagnostic-color.h. (diagnostic_build_prefix): Adjust for 3 argument DEFINE_DIAGNOSTIC_KIND macros. Colorize error:, warning: etc. strings and also the location string. (diagnostic_show_locus): Colorize the caret line. * pretty-print.c: Include diagnostic-color.h. (pp_base_format): Handle %r and %R format specifiers. Colorize strings inside of %< %> quotes or quoted through q format modifier. c-family/ * c-format.c (gcc_diag_char_table, gcc_tdiag_char_table, gcc_cdiag_char_table, gcc_cxxdiag_char_table): Add %r and %R format specifiers. cp/ * error.c (cp_print_error_function, print_instantiation_partial_context_line, maybe_print_constexpr_context): Colorize locus strings. From-SVN: r197841
2013-04-10Improve cstore code generation on 64-bit sparc.David S. Miller2-0/+6
One major suboptimal area of the sparc back end is cstore generation on 64-bit. Due to the way arguments and return values of functions must be promoted, the ideal mode for cstore's result would be DImode. But this hasn't been done because of a fundamental limitation of the cstore patterns. They require a fixed mode be used for the boolean result value. I've decided to work around this by building a target hook which specifies the type to use for conditional store results, and then I use a special predicate for operans 0 in the cstore expanders so that they still match even when we use DImode. The default version of the target hook just does what it does now, so no other target should be impacted by this at all. Regstrapped on 32-bit sparc-linux-gnu and I've run the testsuite with "-m64" to validate the 64-bit side. gcc/ * target.def (cstore_mode): New hook. * target.h: Include insn-codes.h * targhooks.c: Likewise. (default_cstore_mode): New function. * targhooks.h: Declare it. * doc/tm.texi.in: New hook slot for TARGET_CSTORE_MODE. * doc/tm.texi: Rebuild. * expmed.c (emit_cstore): Obtain cstore boolean result mode using target hook, rather than inspecting the insn_data. * config/sparc/sparc.c (sparc_cstore_mode): New function. (TARGET_CSTORE_MODE): Redefine. (emit_scc_insn): When TARGET_ARCH64, emit new 64-bit boolean result patterns. * config/sparc/predicates.md (cstore_result_operand): New special predicate. * config/sparc/sparc.md (cstoresi4, cstoredi4, cstore<F:mode>4): Use it for operand 0. (*seqsi_special): Rewrite using 'P' mode iterator on operand 0. (*snesi_special): Likewise. (*snesi_zero): Likewise. (*seqsi_zero): Likewise. (*sltu_insn): Likewise. (*sgeu_insn): Likewise. (*seqdi_special): Make operand 0 and comparison operation be of DImode. (*snedi_special): Likewise. (*snedi_special_vis3): Likewise. (*neg_snesi_zero): Rename to *neg_snesisi_zero. (*neg_snesi_sign_extend): Rename to *neg_snesidi_zero. (*snesi_zero_extend): Delete, covered by 'P' mode iterator. (*neg_seqsi_zero): Rename to *neg_seqsisi_zero. (*neg_seqsi_sign_extend): Rename to *neg_seqsidi_zero. (*seqsi_zero_extend): Delete, covered by 'P' mode iterator. (*sltu_extend_sp64): Likewise. (*neg_sltu_insn): Rename to *neg_sltusi_insn. (*neg_sltu_extend_sp64): Rename to *neg_sltudi_insn. (*sgeu_extend_sp64): Delete, covered by 'P' mode iterator. (*neg_sgeu_insn): Rename to *neg_sgeusi_insn. (*neg_sgeu_extend_sp64): Rename to *neg_sgeudi_insn. gcc/testsuite/ * gcc.target/sparc/setcc-4.c: New test. * gcc.target/sparc/setcc-5.c: New test. From-SVN: r197679
2013-04-08rtl.texi (sequence): Rewrite documentation to match the current use of ↵Steven Bosscher1-33/+19
SEQUENCE rtl objects. * doc/rtl.texi (sequence): Rewrite documentation to match the current use of SEQUENCE rtl objects. * rtl.def (SEQUENCE): Likewise. * doc/rtl.texi (NOTE_INSN_EH_REGION_BEG, NOTE_INSN_EH_REGION_END): Update documentation. (NOTE_INSN_LOOP_BEG, NOTE_INSN_LOOP_END, NOTE_INSN_LOOP_CONT, NOTE_INSN_LOOP_VTOP): Remove documentation for non-existing notes. * reg-notes.def (REG_EH_CONTEXT): Remove unused note. From-SVN: r197611
2013-04-05Document cortex-a53 in ARM options.Ramana Radhakrishnan1-2/+2
2013-04-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * doc/invoke.texi (ARM Options): Document cortex-a53 support. From-SVN: r197513
2013-04-05standards.texi (Standards): The Go frontend supports the Go 1 language standard.Ian Lance Taylor1-7/+2
* doc/standards.texi (Standards): The Go frontend supports the Go 1 language standard. From-SVN: r197507
2013-03-30md.texi (Standard Names): Update documentation for JUMP_TABLE_DATA changes.Steven Bosscher4-8/+22
* doc/md.texi (Standard Names) <casesi>: Update documentation for JUMP_TABLE_DATA changes. * doc/tm.texi.in (Dispatch Tables) <ASM_OUTPUT_CASE_LABEL>: Likewise. * doc/rtl.texi (Flags) <INSN_DELETED_P, SCHED_GROUP_P>: Likewise. (Insns) <jump_table_data>: New entry. * doc/tm.texi: Regenerate. From-SVN: r197267
2013-03-29re PR lto/56777 (bad grammar in fwhole-program documentation)Paolo Carlini1-1/+1
2013-03-29 Paolo Carlini <paolo.carlini@oracle.com> PR lto/56777 * doc/invoke.texi ([-fwhole-program]): Fix typo. From-SVN: r197237
2013-03-28genmodes.c (emit_max_int): New function.Kenneth Zadeck1-0/+14
2013-03-28 Kenneth Zadeck <zadeck@naturalbridge.com> * genmodes.c (emit_max_int): New function. (emit_insn_modes_h): Added call to emit_max_function. * doc/rtl.texi (MAX_BITSIZE_MODE_ANY_INT, MAX_BITSIZE_MODE_ANY_MODE): Added doc. * machmode.def: Fixed comment. From-SVN: r197200
2013-03-27invoke.texi (AVR Options): Tweak link for AVR-LibC user manual.Gerald Pfeifer2-3/+3
* doc/invoke.texi (AVR Options): Tweak link for AVR-LibC user manual. * doc/extend.texi (Named Address Spaces): Ditto. (Variable Attributes): Ditto. From-SVN: r197180
2013-03-27target.def (TARGET_HAS_IFUNC_P): New target hook.Alexander Ivchenko2-0/+8
* gcc/target.def (TARGET_HAS_IFUNC_P): New target hook. * gcc/doc/tm.texi.in (TARGET_HAS_IFUNC_P): New. * gcc/doc/tm.texi: Regenerate. * gcc/targhooks.h (default_has_ifunc_p): New. * gcc/targhooks.c (default_has_ifunc_p): Ditto. * gcc/config/linux-protos.h: New file. * gcc/config/linux-android.h (TARGET_HAS_IFUNC_P): Using version of this hook for linux which disables support of indirect functions in android. * gcc/config/linux-android.c: New file. * gcc/config/t-linux-android.c: Ditto. * gcc/config.gcc: Added new object file linux-android.o. * gcc/config/i386/i386.c (ix86_get_function_versions_dispatcher): Using TARGET_HAS_IFUNC hook instead of HAVE_GNU_INDIRECT_FUNCTION. * gcc/varasm.c (do_assemble_alias): Likewise. * configure.ac: Define HAVE_GNU_INDIRECT_FUNCTION as zero if the target doesn't support indirect functions. * configure: Regenerate. From-SVN: r197156
2013-03-27arm-cores.def: Added core cortex-r7.Terry Guo1-1/+1
2013-03-27 Terry Guo <terry.guo@arm.com> * config/arm/arm-cores.def: Added core cortex-r7. * config/arm/arm-tune.md: Regenerated. * config/arm/arm-tables.opt: Regenerated. * doc/invoke.texi: Added entry for core cortex-r7. From-SVN: r197153
2013-03-26* doc/invoke.texi (SPARC options): Remove -mlittle-endian.Eric Botcazou1-6/+0
From-SVN: r197120
2013-03-25mmips-cpus.def (74kc, [...]): Add PTF_AVOID_IMADD.Steve Ellcey1-1/+10
2013-03-25 Steve Ellcey <sellcey@mips.com> * config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1, 74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD. * config/mips/mips.c (mips_option_override): Set IMADD default. * config/mips/mips.h (PTF_AVOID_IMADD): New. (ISA_HAS_MADD_MSUB): Remove MIPS16 check. (GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check. * config/mips/mips.md (mimadd): New flag for integer madd/msub. * doc/invoke.texi (-mimadd/-mno-imadd): New. From-SVN: r197072
2013-03-21[ARM] Turning off 64bits ops in NeonChristophe Lyon1-1/+7
2013-03-21 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-protos.h (tune_params): Add prefer_neon_for_64bits field. * config/arm/arm.c (prefer_neon_for_64bits): New variable. (arm_slowmul_tune): Default prefer_neon_for_64bits to false. (arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune): Ditto. (arm_9e_tune, arm_v6t2_tune, arm_cortex_tune): Ditto. (arm_cortex_a15_tune, arm_cortex_a5_tune): Ditto. (arm_cortex_a9_tune, arm_v6m_tune, arm_fa726te_tune): Ditto. (arm_option_override): Handle -mneon-for-64bits new option. * config/arm/arm.h (TARGET_PREFER_NEON_64BITS): New macro. (prefer_neon_for_64bits): Declare new variable. * config/arm/arm.md (arch): Rename neon_onlya8 and neon_nota8 to avoid_neon_for_64bits and neon_for_64bits. Remove onlya8 and nota8. (arch_enabled): Handle new arch types. Remove support for onlya8 and nota8. (one_cmpldi2): Use new arch names. * config/arm/arm.opt (mneon-for-64bits): Add option. * config/arm/neon.md (adddi3_neon, subdi3_neon, iordi3_neon) (anddi3_neon, xordi3_neon, ashldi3_neon, <shift>di3_neon): Use neon_for_64bits instead of nota8 and avoid_neon_for_64bits instead of onlya8. * doc/invoke.texi (-mneon-for-64bits): Document. gcc/testsuite: * gcc.target/arm/neon-for-64bits-1.c: New tests. * gcc.target/arm/neon-for-64bits-2.c: Likewise. From-SVN: r196876
2013-03-20predicates.md (indexed_address, [...]): New predicates.Michael Meissner1-0/+15
[gcc] 2013-03-20 Pat Haugen <pthaugen@us.ibm.com> * config/rs6000/predicates.md (indexed_address, update_address_mem update_indexed_address_mem): New predicates. * config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type" attribute for load/store instructions. * config/rs6000/dfp.md (movsd_store): Likewise. (movsd_load): Likewise. * config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise. (unnamed HI->DI extend define_insn): Likewise. (unnamed SI->DI extend define_insn): Likewise. (unnamed QI->SI extend define_insn): Likewise. (unnamed QI->HI extend define_insn): Likewise. (unnamed HI->SI extend define_insn): Likewise. (unnamed HI->SI extend define_insn): Likewise. (extendsfdf2_fpr): Likewise. (movsi_internal1): Likewise. (movsi_internal1_single): Likewise. (movhi_internal): Likewise. (movqi_internal): Likewise. (movcc_internal1): Correct mnemonic for stw insn. Set correct "type" attribute for load/store instructions. (mov<mode>_hardfloat): Set correct "type" attribute for load/store instructions. (mov<mode>_softfloat): Likewise. (mov<mode>_hardfloat32): Likewise. (mov<mode>_hardfloat64): Likewise. (mov<mode>_softfloat64): Likewise. (movdi_internal32): Likewise. (movdi_internal64): Likewise. (probe_stack_<mode>): Likewise. 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary floating point, and decimal floating point to reload iterator. * config/rs6000/constraints.md (wl constraint): New constraints to return FLOAT_REGS if certain options are used to reduce the number of separate patterns that exist in the file. (wx constraint): Likewise. (wz constraint): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): If -mdebug=reg, print wg, wl, wx, and wz constraints. (rs6000_init_hard_regno_mode_ok): Initialize new constraints. Initialize the reload functions for 64-bit binary/decimal floating point types. (reg_offset_addressing_ok_p): If we are on a power7 or later, use LFIWZX and STFIWX to load/store 32-bit decimal types, and don't create the buffer on the stack to overcome not having a 32-bit load and store. (rs6000_emit_move): Likewise. (rs6000_secondary_memory_needed_rtx): Likewise. (rs6000_alloc_sdmode_stack_slot): Likewise. (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f via xxlxor, just like DFmode 0.0. * config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro, define as 1 if we are running on a power7 or newer. (enum r6000_reg_class_enum): Add new constraints. * config/rs6000/dfp.md (movsd): Delete, combine with binary floating point moves in rs6000.md. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. Use xxlxor to create 0.0f. (movsd splitter): Likewise. (movsd_hardfloat): Likewise. (movsd_softfloat): Likewise. * config/rs6000/rs6000.md (FMOVE32): New iterators to combine binary and decimal floating point moves. (fmove_ok): New attributes to combine binary and decimal floating point moves, and to combine power6x (mfpgpr) moves along normal floating moves. (real_value_to_target): Likewise. (f32_lr): Likewise. (f32_lm): Likewise. (f32_li): Likewise. (f32_sr): Likewise. (f32_sm): Likewise. (f32_si): Likewise. (movsf): Combine binary and decimal floating point moves. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. (mov<mode> for SFmode/SDmode); Likewise. (SFmode/SDmode splitters): Likewise. (movsf_hardfloat): Likewise. (mov<mode>_hardfloat for SFmode/SDmode): Likewise. (movsf_softfloat): Likewise. (mov<mode>_softfloat for SFmode/SDmode): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl, wx and wz constraints. * config/rs6000/constraints.md (wg constraint): New constraint to return FLOAT_REGS if -mmfpgpr (power6x) was used. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg constraint. * config/rs6000/rs6000.c (rs6000_debug_reg_global): If -mdebug=reg, print wg, wl, wx, and wz constraints. (rs6000_init_hard_regno_mode_ok): Initialize new constraints. Initialize the reload functions for 64-bit binary/decimal floating point types. (reg_offset_addressing_ok_p): If we are on a power7 or later, use LFIWZX and STFIWX to load/store 32-bit decimal types, and don't create the buffer on the stack to overcome not having a 32-bit load and store. (rs6000_emit_move): Likewise. (rs6000_secondary_memory_needed_rtx): Likewise. (rs6000_alloc_sdmode_stack_slot): Likewise. (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f via xxlxor, just like DFmode 0.0. * config/rs6000/dfp.md (movdd): Delete, combine with binary floating point moves in rs6000.md. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). Use LFIWZX and STFIWX for loading SDmode on power7. (movdd splitters): Likewise. (movdd_hardfloat32): Likewise. (movdd_softfloat32): Likewise. (movdd_hardfloat64_mfpgpr): Likewise. (movdd_hardfloat64): Likewise. (movdd_softfloat64): Likewise. * config/rs6000/rs6000.md (FMOVE64): New iterators to combine 64-bit binary and decimal floating point moves. (FMOVE64X): Likewise. (movdf): Combine 64-bit binary and decimal floating point moves. Combine power6x (mfpgpr) moves with other moves by using conditional constraits (wg). (mov<mode> for DFmode/DDmode): Likewise. (DFmode/DDmode splitters): Likewise. (movdf_hardfloat32): Likewise. (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise. (movdf_softfloat32): Likewise. (movdf_hardfloat64_mfpgpr): Likewise. (movdf_hardfloat64): Likewise. (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise. (movdf_softfloat64): Likewise. (mov<mode>_softfloat64 for DFmode/DDmode): Likewise. (reload_<mode>_load): Move to later in the file so they aren't in the middle of the floating point move insns. (reload_<mode>_store): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg constraint. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg constraint if -mdebug=reg. (rs6000_initi_hard_regno_mode_ok): Enable wg constraint if -mfpgpr. Enable using dd reload support if needed. * config/rs6000/dfp.md (movtd): Delete, combine with 128-bit binary and decimal floating point moves in rs6000.md. (movtd_internal): Likewise. * config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and decimal floating point moves. (movtf): Likewise. (movtf_internal): Likewise. (mov<mode>_internal, TDmode/TFmode): Likewise. (movtf_softfloat): Likewise. (mov<mode>_softfloat, TDmode/TFmode): Likewise. * config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with movdi_internal64, using wg constraint for move direct operations. (movdi_internal64): Likewise. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print MODES_TIEABLE_P for selected modes. Print the numerical value of the various virtual registers. Use GPR/FPR first/last values, instead of hard coding the register numbers. Print which modes have reload functions registered. (rs6000_option_override_internal): If -mdebug=reg, trace the options settings before/after setting cpu, target and subtarget settings. (rs6000_secondary_reload_trace): Improve the RTL dump for -mdebug=addr and for secondary reload failures in rs6000_secondary_reload_inner. (rs6000_secondary_reload_fail): Likewise. (rs6000_secondary_reload_inner): Likewise. * config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience macros for first/last GPR and FPR registers. (LAST_GPR_REGNO): Likewise. (FIRST_FPR_REGNO): Likewise. (LAST_FPR_REGNO): Likewise. * config/rs6000/vector.md (mul<mode>3): Use the combined macro VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P. (vcond<mode><mode>): Likewise. (vcondu<mode><mode>): Likewise. (vector_gtu<mode>): Likewise. (vector_gte<mode>): Likewise. (xor<mode>3): Don't allow logical operations on TImode in 32-bit to prevent the compiler from converting DImode operations to TImode. (ior<mode>3): Likewise. (and<mode>3): Likewise. (one_cmpl<mode>2): Likewise. (nor<mode>3): Likewise. (andc<mode>3): Likewise. * config/rs6000/constraints.md (wt constraint): New constraint that returns VSX_REGS if TImode is allowed in VSX registers. * config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy constant under VSX. * config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is similar to TImode, but it is restricted to being in the GPRs. * config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow TImode to occupy a single VSX register. * config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to -mvsx-timode for power7/power8. (power7 cpu): Likewise. (power8 cpu): Likewise. * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make sure that TFmode/TDmode take up two registers if they are ever allowed in the upper VSX registers. (rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX registers. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_debug_reg_global): Add debugging for PTImode and wt constraint. Print if LRA is turned on. (rs6000_option_override_internal): Give an error if -mvsx-timode and VSX is not enabled. (invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If -mvsx-timode, restrict TImode to reg+reg addressing, and PTImode to reg+offset addressing. Use PTImode when checking offset addresses for validity. (reg_offset_addressing_ok_p): Likewise. (rs6000_legitimate_offset_address_p): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_legitimize_reload_address): Likewise. (rs6000_legitimate_address_p): Likewise. (rs6000_eliminate_indexed_memrefs): Likewise. (rs6000_emit_move): Likewise. (rs6000_secondary_reload): Likewise. (rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit reloads to fpr registers to continue to use reg+offset addressing, but 64-bit reloads to altivec registers need reg+reg addressing. Drop test for PRE_MODIFY, since VSX loads/stores no longer support it. Treat LO_SUM like a PLUS operation. (rs6000_secondary_reload_class): If type is 64-bit, prefer to use FLOAT_REGS instead of VSX_RGS to allow use of reg+offset addressing. (rs6000_cannot_change_mode_class): Do not allow TImode in VSX registers to share a register with a smaller sized type, since VSX puts scalars in the upper 64-bits. (print_operand): Add support for PTImode. (rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX registers, but don't have arithmetic support. (rs6000_memory_move_cost): Add test for VSX. (rs6000_opt_masks): Add -mvsx-timode. * config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves for TImode. (VSs): Likewise. (VSr): Use wt constraint for TImode. (VSv): Drop TImode support. (vsx_movti): Delete, replace with versions for 32-bit and 64-bit. (vsx_movti_64bit): Likewise. (vsx_movti_32bit): Likewise. (vec_store_<mode>): Use VSX iterator instead of vector iterator. (vsx_and<mode>3): Delete use of '?' constraint on inputs, just put one '?' on the appropriate output constraint. Do not allow TImode logical operations on 32-bit systems. (vsx_ior<mode>3): Likewise. (vsx_xor<mode>3): Likewise. (vsx_one_cmpl<mode>2): Likewise. (vsx_nor<mode>3): Likewise. (vsx_andc<mode>3): Likewise. (vsx_concat_<mode>): Likewise. (vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes. * config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from OPTION_MASK_VSX_TIMODE. (enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. (STACK_SAVEAREA_MODE): Use PTImode instead of TImode. * config/rs6000/rs6000.md (INT mode attribute): Add PTImode. (TI2 iterator): New iterator for TImode, PTImode. (wd mode attribute): Add values for vector types. (movti_string): Replace TI move operations with operations for TImode and PTImode. Add support for TImode being allowed in VSX registers. (mov<mode>_string, TImode/PTImode): Likewise. (movti_ppc64): Likewise. (mov<mode>_ppc64, TImode/PTImode): Likewise. (TI mode splitters): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt constraint. [gcc/testsuite] 2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/mmfpgpr.c: New test. * gcc.target/powerpc/sd-vsx.c: Likewise. * gcc.target/powerpc/sd-pwr6.c: Likewise. * gcc.target/powerpc/vsx-float0.c: Likewise. From-SVN: r196831
2013-03-20extend.texi: (micromips, nomicromips, nocompression): Document new function ↵Catherine Moore3-7/+67
attributes. gcc/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Tom de Vries <tom@codesourcery.com> Nathan Sidwell <nathan@codesourcery.com> Iain Sandoe <iain@codesourcery.com> Nathan Froyd <froydnj@codesourcery.com> Chao-ying Fu <fu@mips.com> * doc/extend.texi: (micromips, nomicromips, nocompression): Document new function attributes. * doc/invoke.texi (minterlink-compressed, mmicromips, m14k, m14ke, m14kec): Document new options. (minterlink-mips16): Update documentation. * doc/md.texi (ZC, ZD): Document new constraints. * configure.ac (gcc_cv_as_micromips): Check if linker supports the .set micromips directive. * configure: Regenerate. * config.in: Regenerate. * config/mips/mips-tables.opt: Regenerate. * config/mips/micromips.md: New file. * constraints.md (ZC, ZD): New constraints. * config/mips/predicates.md (movep_src_register): New predicate. (movep_src_operand): New predicate. (non_volatile_mem_operand): New predicate. * config/mips/mips.md (multimem): New type. (length): Differentiate between 17-bit and 18-bit branch offsets. (MOVEP1, MOVEP2): New mode iterator. (mov_<load>l): Use ZC constraint. (mov_<load>r): Likewise. (mov_<store>l): Likewise. (mov_<store>r): Likewise. (*branch_equality<mode>_inverted): Add microMIPS support. (*branch_equality<mode>): Likewise. (*jump_absolute): Likewise. (indirect_jump_<mode>): Likewise. (tablejump_<mode>): Likewise. (<optab>_internal): Likewise. (sibcall_internal): Likewise. (sibcall_value_internal): Likewise. (prefetch): Use constraint ZD. * config/mips/mips.opt (minterlink-compressed): New option. (minterlink-mips16): Now an alias for minterlink-compressed. (mmicromips): New option. * config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint. (compare_and_swap_12): Likewise. (sync_add<mode>): Likewise. (sync_<optab>_12): Likewise. (sync_old_<optab>_12): Likewise. (sync_new_<optab>_12): Likewise. (sync_nand_12): Likewise. (sync_old_nand_12): Likewise. (sync_new_nand_12): Likewise. (sync_sub<mode>): Likewise. (sync_old_add<mode>): Likewise. (sync_old_sub<mode>): Likewise. (sync_new_add<mode>): Likewise. (sync_new_sub<mode>): Likewise. (sync_<optab><mode>): Likewise. (sync_old_<optab><mode>): Likewise. (sync_new_<optab><mode>): Likewise. (sync_nand<mode>): Likewise. (sync_old_nand<mode>): Likewise. (sync_new_nand<mode>): Likewise. (sync_lock_test_and_set<mode>): Likewise. (test_and_set_12): Likewise. (atomic_compare_and_swap<mode>): Likewise. (atomic_exchange<mode>_llsc): Likewise. (atomic_fetch_add<mode>_llsc): Likewise. * config/mips/mips-cpus.def (m14kc, m14k): New processors. * config/mips/mips-protos.h (umips_output_save_restore): New prototype. (umips_save_restore_pattern_p): Likewise. (umips_load_store_pair_p): Likewise. (umips_output_load_store_pair): Likewise. (umips_movep_target_p): Likewise. (umips_12bit_offset_address_p): Likewise. * config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. Update all uses. (mips_attribute_table): Add micromips, nomicromips and nocompression. (mips_mips16_decl_p): Delete. (mips_nomips16_decl_p): Delete. (mips_get_compress_on_flags): New function. (mips_get_compress_off_flags): New function. (mips_get_compress_mode): New function. (mips_get_compress_on_name): New function. (mips_get_compress_off_name): New function. (mips_insert_attributes): Support multiple compression types. (mips_merge_decl_attributes): Likewise. (umips_12bit_offset_address_p): New function. (mips_start_function_definition): Emit .set micromips directive. (mips_call_may_need_jalx_p): New function. (mips_function_ok_for_sibcall): Add microMIPS support. (mips_print_operand_punctuation): Support short delay slots and compact jumps. (umips_swm_mask, umips_swm_encoding): New. (umips_build_save_restore): New function. (mips_for_each_saved_gpr_and_fpr): Add microMIPS support. (was_mips16_p): Remove. (old_compression_mode): New. (mips_set_compression_mode): New function. (mips_set_current_function): Add microMIPS support. (mips_option_override): Likewise. (umips_save_restore_pattern_p): New function. (umips_output_save_restore): New function. (umips_load_store_pair_p_1): New function. (umips_load_store_pair_p): New function. (umips_output_load_store_pair_1): New function. (umips_output_load_store_pair): New function. (umips_movep_target_p) New function. (mips_prepare_pch_save): Add microMIPS support. * config/mips/mips.h (TARGET_COMPRESSION): New. (TARGET_CPU_CPP_BUILTINS): Update macro to use new compression flags and to support microMIPS. (MIPS_ISA_LEVEL_SPEC): Add m14k processors. (MIPS_ARCH_FLOAT_SPEC): Likewise. (ISA_HAS_LWXS): Include TARGET_MICROMIPS. (ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS. (ASM_SPEC): Support mmicromips and mno-micromips. (M16STORE_REG_P): New macro. (MIPS_CALL): Support TARGET_MICROMIPS. (MICROMIPS_J): New macro. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. (UMIPS_12BIT_OFFSET_P): New macro. * config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS. (MULTILIB_DIRNAMES): Likewise. libgcc/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Chao-ying Fu <fu@mips.com> * config/mips/mips16.S: Don't build for microMIPS. * config/mips/linux-unwind.h: Handle microMIPS frame. * config/mips/crtn.S (fini, init): New labels. gcc/testsuite/ 2013-03-20 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * gcc.target/mips/mips.exp: Add microMIPS support. * gcc.target/mips/umips-movep-2.c: New test. * gcc.target/mips/umips-lwp-2.c: New test. * gcc.target/mips/umips-swp-5.c: New test. * gcc.target/mips/umips-constraints-1.c: New test. * gcc.target/mips/umips-lwp-3.c: New test. * gcc.target/mips/umips-swp-6.c: New test. * gcc.target/mips/umips-constraints-2.c: New test. * gcc.target/mips/umips-save-restore-1.c: New test. * gcc.target/mips/umips-lwp-4.c: New test. * gcc.target/mips/umips-swp-7.c: New test. * gcc.target/mips/umips-save-restore-2.c: New test. * gcc.target/mips/umips-lwp-swp-volatile.c: New test. * gcc.target/mips/umips-lwp-5.c: New test. * gcc.target/mips/umips-save-restore-3.c: New test. * gcc.target/mips/umips-lwp-6.c: New test. * gcc.target/mips/umips-swp-1.c: New test. * gcc.target/mips/umips-lwp-7.c: New test. * gcc.target/mips/umips-swp-2.c: New test. * gcc.target/mips/umips-lwp-8.c: New test. * gcc.target/mips/umips-swp-3.c: New test. * gcc.target/mips/umips-movep-1.c: New test. * gcc.target/mips/umips-lwp-1.c: New test. * gcc.target/mips/umips-swp-4.c: New test. Co-Authored-By: Chao-ying Fu <fu@mips.com> Co-Authored-By: Iain Sandoe <iain@codesourcery.com> Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Maciej W. Rozycki <macro@codesourcery.com> Co-Authored-By: Nathan Froyd <froydnj@codesourcery.com> Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> Co-Authored-By: Richard Sandiford <rdsandiford@googlemail.com> Co-Authored-By: Tom de Vries <tom@codesourcery.com> From-SVN: r196828
2013-03-15Document HLE / RTM intrinsicsAndi Kleen1-0/+115
The TSX HLE/RTM intrinsics were missing documentation. Add this to the manual. gcc/: 2013-03-14 Andi Kleen <ak@linux.intel.com> PR target/56619 * doc/extend.texi: Document __ATOMIC_HLE_ACQUIRE, __ATOMIC_HLE_RELEASE. Document __builtin_ia32 TSX intrincs. Document _x* TSX intrinsics. From-SVN: r196671
2013-03-14re PR tree-optimization/53265 (Warn when undefined behavior implies smaller ↵Jakub Jelinek1-1/+8
iteration count) PR tree-optimization/53265 * common.opt (Waggressive-loop-optimizations): New option. * tree-ssa-loop-niter.c: Include tree-pass.h. (do_warn_aggressive_loop_optimizations): New function. (record_estimate): Call it. Don't add !is_exit bounds to loop->bounds if number_of_latch_executions returned constant. (estimate_numbers_of_iterations_loop): Call number_of_latch_executions early. If number_of_latch_executions returned constant, set nb_iterations_upper_bound back to it. * cfgloop.h (struct loop): Add warned_aggressive_loop_optimizations field. * Makefile.in (tree-ssa-loop-niter.o): Depend on $(TREE_PASS_H). * doc/invoke.texi (-Wno-aggressive-loop-optimizations): Document. * gcc.dg/pr53265.c: New test. * gcc.dg/torture/pr49518.c: Add -Wno-aggressive-loop-optimizations to dg-options. * g++.dg/opt/longbranch2.C (EBCOTLut): Double sizes of a2 and a3 arrays. * gcc.dg/tree-ssa/cunroll-10.c (main): Rename to foo. Add argument n, use it as high bound instead of 4. * unwind-dw2.c (execute_cfa_program): Avoid -Waggressive-array-optimizations warnings for DW_CFA_GNU_window_save on targets with DWARF_FRAME_REGISTERS < 32. * testsuite/libmudflap.c/fail37-frag.c: Add optimization barrier. From-SVN: r196650
2013-03-12* doc/invoke.texi (-Waddr-space-convert): Move into the table earlier.Jakub Jelinek1-5/+5
From-SVN: r196614
2013-03-12re PR target/56263 ([avr] Provide strict address-space checking)Georg-Johann Lay1-1/+6
PR target/56263 * config/avr/avr.c (TARGET_CONVERT_TO_TYPE): Define to... (avr_convert_to_type): ...this new static function. * config/avr/avr.opt (-Waddr-space-convert): New C option. * doc/invoke.texi (AVR Options): Document it. From-SVN: r196611
2013-03-07invoke.texi (fwhole-program): Discourage use in combination with -flto.Richard Biener1-9/+5
2013-03-07 Richard Biener <rguenther@suse.de> * doc/invoke.texi (fwhole-program): Discourage use in combination with -flto. From-SVN: r196518
2013-03-06re PR target/56529 ([SH] Calls to __sdivsi3_i4i and __udivsi3_i4i are ↵Oleg Endo1-2/+32
generated on SH2) PR target/56529 * config/sh/sh.c (sh_option_override): Check for TARGET_DYNSHIFT instead of TARGET_SH2 for call-table case. Do not set sh_div_strategy to SH_DIV_CALL_TABLE for TARGET_SH2. * config.gcc (sh_multilibs): Add m2 and m2a to sh*-*-linux* multilib list. * doc/invoke.texi (SH options): Document mdiv= call-div1, call-fp, call-table options. PR target/56529 * config/sh/lib1funcs.S (udivsi3_i4i, sdivsi3_i4i): Add __SH2A__ to inclusion list. From-SVN: r196484
2013-03-05invoke.texi (MicroBlaze): Add -mbig-endian, -mlittle-endian, -mxl-reorder.David Holsgrove1-1/+13
* doc/invoke.texi (MicroBlaze): Add -mbig-endian, -mlittle-endian, -mxl-reorder. From-SVN: r196470
2013-03-03target.def (TARGET_OPTION_VALID_ATTRIBUTE_P): Update comments; the attribute ↵Sandra Loosemore2-36/+36
is now called "target" instead of "option". 2013-03-03 Sandra Loosemore <sandra@codesourcery.com> gcc/ * target.def (TARGET_OPTION_VALID_ATTRIBUTE_P): Update comments; the attribute is now called "target" instead of "option". (TARGET_OPTION_PRAGMA_PARSE): Likewise, for the pragma. * doc/tm.texi.in (Target Attributes): Likewise document the correct attribute/pragma name for TARGET_OPTION_VALID_P and TARGET_OPTION_PRAGMA_PARSE. Also copy-edit and correct markup. * doc/tm.texi: Regenerated. From-SVN: r196418
2013-03-01extended.texi (C Extensions): Change order in @menu to match @node.Tobias Burnus5-173/+173
gcc/ 2013-03-01 Tobias Burnus <burnus@net-b.de> * doc/extended.texi (C Extensions): Change order in @menu to match @node. (Other MIPS Built-in Functions): Move last MIPS entry before "picoChip Built-in Functions". (SH Built-in Functions): Move after RX Built-in Functions. * doc/gcc.texi (Introduction): Change order in @menu to match @node. * doc/md.texi (Constraints): Ditto. * gty.texi (Type Information): Ditto. (User-provided marking routines for template types): Make subsection. * doc/invoke.texi (AArch64 Options): Move before "Adapteva Epiphany Options". libiberty/ 2013-03-01 Andreas Schwab <schwab@linux-m68k.org> * obstacks.texi (Obstacks): Trim @node to only contain the node name. * libiberty.texi (Obstacks): Lower section. From-SVN: r196388
2013-02-28re PR sanitizer/56454 (need to rename attribute no_address_safety_analysis ↵Konstantin Serebryany1-4/+9
to no_sanitize_address) PR sanitizer/56454 * asan.c (gate_asan): Lookup no_sanitize_address instead of no_address_safety_analysis attribute. * doc/extend.texi (no_address_safety_attribute): Rename to no_sanitize_address attribute, mention no_address_safety_analysis attribute as deprecated alias. * c-common.c (handle_no_sanitize_address_attribute): New function. (c_common_attribute_table): Add no_sanitize_address attribute. (handle_no_address_safety_analysis_attribute): Add no_sanitize_address attribute, not no_address_safety_analysis attribute. * g++.dg/asan/default-options-1.C (__asan_default_options): Use no_sanitize_address attribute rather than no_address_safety_analysis. * g++.dg/asan/sanitizer_test_utils.h (ATTRIBUTE_NO_ADDRESS_SAFETY_ANALYSIS): Likewise. * c-c++-common/asan/attrib-1.c: Test no_sanitize_address attribute in addition to no_address_safety_analysis. Co-Authored-By: Jakub Jelinek <jakub@redhat.com> From-SVN: r196361
2013-02-28re PR c++/55813 (Poorly named/documented option Wctor-dtor-privacy)Paolo Carlini1-1/+3
2013-02-28 Paolo Carlini <paolo.carlini@oracle.com> PR c++/55813 * doc/invoke.texi ([-Wctor-dtor-privacy]): Complete. From-SVN: r196334
2013-02-28* avr/avr-mcus.def (ata5272, ata5505, attiny1634, ata6285)Georg-Johann Lay1-9/+9
(ata6286, atmega8a, atmega48pa, ata5790, ata5790n, ata5795) (atmega164pa, atmega165pa, atmega168pa, atmega16hva, atmega16hvb) (atmega16hvbrevb, atmega16m1, atmega16u4, atmega26hvg, atmega32a) (atmega32a, atmega3250pa, atmega3290pa, atmega32c1, atmega32m1) (atmega32u4, atmega32u6, atmega64a, atmega6490a, atmega6490p) (atmega64c1, atmega64m1, atmega64rfa2, atmega64rfr2, atmega32hvb) (atmega32hvbrevb, atmega16hva2, atmega48hvf, at90pwm161) (atmega128a, atmega1284, atmxt112sl, atmxt224, atmxt224e) (atmxt336s, atxmega16a4u, atxmega16c4, atxmega32a4u, atxmega32c4) (atxmega32e5, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3) (atxmega64c3, atxmega64d4, atxmega128a3u, atxmega128b1) (atxmega128b3, atxmega128c3, atxmega128d4, atmxt540s, atmxt540sreva) (atxmega192a3u, atxmega192c3, atxmega256a3u, atxmega256c3) (atxmega384c3, atxmega384d3, atxmega128a4u): New AVR_MCU. (avrxmega6): Increase max flash segments from 5 to 6. * config/avr/t-multilib: Regenerate. * config/avr/avr-tables.opt: Regenerate. * doc/avr-mmcu.texi: Regenerate. From-SVN: r196331
2013-02-25invoke.texi: Document r4700.Matt Turner1-1/+1
gcc/ 2013-02-25 Matt Turner <mattst88@gmail.com> * doc/invoke.texi: Document r4700. From-SVN: r196270
2013-02-252012-02-25 Catherine Moore <clm@codesourcery.com>Catherine Moore3-67/+7
Revert microMIPS patch. From-SVN: r196259
2013-02-25invoke.texi (-fsanitize=): Move from optimization to debugging options.Tobias Burnus1-12/+12
2013-02-25 Tobias Burnus <burnus@net-b.de> * doc/invoke.texi (-fsanitize=): Move from optimization to debugging options. From-SVN: r196254
2013-02-24mips16.S: Don't build for microMIPS.Catherine Moore3-7/+67
libgcc/ 2013-02-24 Catherine Moore <clm@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Chao-ying Fu <fu@mips.com> * config/mips/mips16.S: Don't build for microMIPS. * config/mips/linux-unwind.h: Handle microMIPS frame. * config/mips/crtn.S (fini, init): New labels. gcc/ 2013-02-24 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Tom de Vries <tom@codesourcery.com> Nathan Sidwell <nathan@codesourcery.com> Iain Sandoe <iain@codesourcery.com> Nathan Froyd <froydnj@codesourcery.com> Chao-ying Fu <fu@mips.com> * doc/extend.texi: (micromips, nomicromips, nocompression): Document new function attributes. * doc/invoke.texi (minterlink-compressed, mmicromips, m14k, m14ke, m14kec): Document new options. (minterlink-mips16): Update documentation. * doc/md.texi (ZC, ZD): Document new constraints. * configure.ac (gcc_cv_as_micromips): Check if linker supports the .set micromips directive. * configure: Regenerate. * config.in: Regenerate. * config/mips/mips-tables.opt: Regenerate. * config/mips/micromips.md: New file. * constraints.md (ZC, AD): New constraints. * config/mips/predicates.md (movep_src_register): New predicate. (movep_src_operand): New predicate. (non_volatile_mem_operand): New predicate. * config/mips/mips.md (multimem): New type. (length): Differentiate between 17-bit and 18-bit branch offsets. (MOVEP1, MOVEP2): New mode iterator. (mov_<load>l): Use ZC constraint. (mov_<load>r): Likewise. (mov_<store>l): Likewise. (mov_<store>r): Likewise. (*branch_equality<mode>_inverted): Add microMIPS support. (*branch_equality<mode>): Likewise. (*jump_absolute): Likewise. (indirect_jump_<mode>): Likewise. (tablejump_<mode>): Likewise. (<optab>_internal): Likewise. (sibcall_internal): Likewise. (sibcall_value_internal): Likewise. (prefetch): Use constraint ZD. * config/mips/mips.opt (minterlink-compressed): New option. (minterlink-mips16): Now an alias for minterlink-compressed. (mmicromips): New option. * config/mips/sync.md (sync_compare_and_swap<mode>): Use ZR constraint. (compare_and_swap_12): Likewise. (sync_add<mode>): Likewise. (sync_<optab>_12): Likewise. (sync_old_<optab>_12): Likewise. (sync_new_<optab>_12): Likewise. (sync_nand_12): Likewise. (sync_old_nand_12): Likewise. (sync_new_nand_12): Likewise. (sync_sub<mode>): Likewise. (sync_old_add<mode>): Likewise. (sync_old_sub<mode>): Likewise. (sync_new_add<mode>): Likewise. (sync_new_sub<mode>): Likewise. (sync_<optab><mode>): Likewise. (sync_old_<optab><mode>): Likewise. (sync_new_<optab><mode>): Likewise. (sync_nand<mode>): Likewise. (sync_old_nand<mode>): Likewise. (sync_new_nand<mode>): Likewise. (sync_lock_test_and_set<mode>): Likewise. (test_and_set_12): Likewise. (atomic_compare_and_swap<mode>): Likewise. (atomic_exchange<mode>_llsc): Likewise. (atomic_fetch_add<mode>_llsc): Likewise. * config/mips/mips-cpus.def (m14kc, m14k): New processors. * config/mips/mips-protos.h (umips_output_save_restore): New prototype. (umips_save_restore_pattern_p): Likewise. (umips_load_store_pair_p): Likewise. (umips_output_load_store_pair): Likewise. (umips_movep_target_p): Likewise. (umips_12bit_offset_address_p): Likewise. * config/mips/mips.c (MIPS_MAX_FIRST_STEP): Update for microMIPS. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. Update all uses. (mips_attribute_table): Add micromips, nomicromips and nocompression. (mips_mips16_decl_p): Delete. (mips_nomips16_decl_p): Delete. (mips_get_compress_on_flags): New function. (mips_get_compress_off_flags): New function. (mips_get_compress_mode): New function. (mips_get_compress_on_name): New function. (mips_get_compress_off_name): New function. (mips_insert_attributes): Support multiple compression types. (mips_merge_decl_attributes): Likewise. (umips_12bit_offset_address_p): New function. (mips_start_function_definition): Emit .set micromips directive. (mips_call_may_need_jalx_p): New function. (mips_function_ok_for_sibcall): Add microMIPS support. (mips_print_operand_punctuation): Support short delay slots and compact jumps. (umips_swm_mask, umips_swm_encoding): New. (umips_build_save_restore): New function. (mips_for_each_saved_gpr_and_fpr): Add microMIPS support. (was_mips16_p): Remove. (old_compression_mode): New. (mips_set_compression_mode): New function. (mips_set_current_function): Add microMIPS support. (mips_option_override): Likewise. (umips_save_restore_pattern_p): New function. (umips_output_save_restore): New function. (umips_load_store_pair_p_1): New function. (umips_load_store_pair_p): New function. (umips_output_load_store_pair_1): New function. (umips_output_load_store_pair): New function. (umips_movep_target_p) New function. (mips_prepare_pch_save): Add microMIPS support. * config/mips/mips.h (TARGET_COMPRESSION): New. (TARGET_CPU_CPP_BUILTINS): Update macro to use new compression flags and to support microMIPS. (MIPS_ISA_LEVEL_SPEC): Add m14k processors. (MIPS_ARCH_FLOAT_SPEC): Likewise. (ISA_HAS_LWXS): Include TARGET_MICROMIPS. (ISA_HAS_LOAD_DELAY): Exclude TARGET_MICROMIPS. (ASM_SPEC): Support mmicromips and mno-micromips. (M16STORE_REG_P): New macro. (MIPS_CALL): Support TARGET_MICROMIPS. (MICROMIPS_J): New macro. (mips_base_mips16): Rename this... (mips_base_compression_flags): ...to this. (UMIPS_12BIT_OFFSET_P): New macro. * config/mips/t-sde: (MULTILIB_OPTIONS): Add microMIPS. (MULTILIB_DIRNAMES): Likewise. gcc/testsuite/ 2013-02-24 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * gcc.target/mips/mips.exp: Add microMIPS support. * gcc.target/mips/umips-movep-2.c: New test. * gcc.target/mips/umips-lwp-2.c: New test. * gcc.target/mips/umips-swp-5.c: New test. * gcc.target/mips/umips-constraints-1.c: New test. * gcc.target/mips/umips-lwp-3.c: New test. * gcc.target/mips/umips-swp-6.c: New test. * gcc.target/mips/umips-constraints-2.c: New test. * gcc.target/mips/umips-save-restore-1.c: New test. * gcc.target/mips/umips-lwp-4.c: New test. * gcc.target/mips/umips-swp-7.c: New test. * gcc.target/mips/umips-save-restore-2.c: New test. * gcc.target/mips/umips-lwp-swp-volatile.c: New test. * gcc.target/mips/umips-lwp-5.c: New test. * gcc.target/mips/umips-save-restore-3.c: New test. * gcc.target/mips/umips-lwp-6.c: New test. * gcc.target/mips/umips-swp-1.c: New test. * gcc.target/mips/umips-lwp-7.c: New test. * gcc.target/mips/umips-swp-2.c: New test. * gcc.target/mips/umips-lwp-8.c: New test. * gcc.target/mips/umips-swp-3.c: New test. * gcc.target/mips/umips-movep-1.c: New test. * gcc.target/mips/umips-lwp-1.c: New test. * gcc.target/mips/umips-swp-4.c: New test. Co-Authored-By: Chao-ying Fu <fu@mips.com> Co-Authored-By: Iain Sandoe <iain@codesourcery.com> Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Maciej W. Rozycki <macro@codesourcery.com> Co-Authored-By: Nathan Froyd <froydnj@codesourcery.com> Co-Authored-By: Nathan Sidwell <nathan@codesourcery.com> Co-Authored-By: Richard Sandiford <rdsandiford@googlemail.com> Co-Authored-By: Tom de Vries <tom@codesourcery.com> From-SVN: r196246
2013-02-21rtl.texi (vec_concat, [...]): Mention that scalars are valid operands.Hans-Peter Nilsson1-8/+9
* doc/rtl.texi (vec_concat, vec_duplicate): Mention that scalars are valid operands. From-SVN: r196208
2013-02-21invoke.texi (MIPS Options): Update documentation of the floating-point ↵Maciej W. Rozycki1-4/+6
multiply-accumulate instruction... * doc/invoke.texi (MIPS Options): Update documentation of the floating-point multiply-accumulate instruction restrictions. From-SVN: r196204
2013-02-21re PR bootstrap/56258 (Please upgrade doc/*.texi to the latest texinfo ↵Jakub Jelinek1-1/+1
package(s)) PR bootstrap/56258 * doc/invoke.texi (-fdump-rtl-pro_and_epilogue): Use @item instead of @itemx. * gnat-style.texi (@title): Remove @hfill. * projects.texi: Avoid line wrapping inside of @pxref or @xref. * doc/cp-tools.texinfo (Virtual Machine Options): Use just one @gccoptlist instead of 3 separate ones. From-SVN: r196196
2013-02-12extend.texi: Document Function Multiversioning and "default" parameter ↵Sriraman Tallam1-0/+64
string to target... * doc/extend.texi: Document Function Multiversioning and "default" parameter string to target attribute. * g++.dg/ext/mv12.C: New test. * g++.dg/ext/mv12.h: New file. * g++.dg/ext/mv12-aux.C: New file. * g++.dg/ext/mv13.C: New test. * config/i386/i386.c (get_builtin_code_for_version): Return 0 if target attribute parameter is "default". (ix86_compare_version_priority): Remove checks for target attribute. (ix86_mangle_function_version_assembler_name): Change error to sorry. Remove check for target attribute equal to NULL. Add assert. (ix86_generate_version_dispatcher_body): Change error to sorry. From-SVN: r195967
2013-02-05install.texi: Refer to ISL, not PPL.Richard Biener1-3/+3
2013-02-05 Richard Biener <rguenther@suse.de> * doc/install.texi: Refer to ISL, not PPL. From-SVN: r195752
2013-01-31lib1funcs.S: Add support for e3v5 architecture variant.Nick Clifton1-25/+145
* config/v850/lib1funcs.S: Add support for e3v5 architecture variant. * config/v850/constraints.md (Q): Define as a memory constraint. * config/v850/predicates.md (label_ref_operand): New predicate. (e3v5_shift_operand): New predicate. (ior_operator): New predicate. * config/v850/t-v850: Add e3v5 multilib. * config/v850/v850-protos.h (v850_adjust_insn_length): Prototype. (v850_gen_movdi): Prototype. * config/v850/v850.c: Add support for e3v5 architecture. Rename all uses of TARGET_V850E || TARGET_V850E2_ALL to TARGET_V850E_UP. (construct_save_jarl): Add e3v5 long JARL support. (v850_adjust_insn_length): New function. Adjust length of call insns when using e3v5 instructions. (v850_gen_movdi): New function: Generate instructions to move a DImode value. * config/v850/v850.h (TARGET_CPU_v850e3v5): Define. (CPP_SPEC): Define __v850e3v5__ as appropriate. (TARGET_USE_FPU): Enable for e3v5. (CONST_OK_FOR_W): New macro. (ADJUST_INSN_LENGTH): Define. * config/v850/v850.md (UNSPEC_LOOP): Define. (attr cpu): Add v850e3v5. Rename all uses of TARGET_V850E2 to TARGET_V850E2V3_UP. (movdi): New pattern. (movdi_internal): New pattern. (cbranchsf4): Conditionalize on TARGET_USE_FPU. (cbranchdf4): Conditionalize on TARGET_USE_FPU. (cstoresf4): Likewise. (cstoredf4): Likewise. (insv): New pattern. (rotlso3_a): New pattern. (rotlsi3_b): New pattern (rotlsi3_v850e3v5): New pattern. (doloop_begin): New pattern. (fix_loop_counter): New pattern. (doloop_end): New pattern. (branch_normal): Add e3v5 long branch support. (branch_invert): Likewise. (branch_z_normal): Likewise. (branch_z_invert): Likewise. (branch_nz_normal): Likewise. (branch_nz_invert): Likewise. (call_internal_short): Add e3v5 register-indirect JARL support. (call_internal_long): Likewise. (call_value_internal_short): Likewise. (call_value_internal_long): Likewise. * config/v850/v850.opt (mv850e3v5, mv850e2v4): New options. (mloop): New option. * config.gcc: Add support for configuring v840e3v5 target. * doc/invoke.texi: Document new v850 specific command line options. From-SVN: r195623
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