Age | Commit message (Collapse) | Author | Files | Lines |
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2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* target.def (hard_regno_mode_ok): New hook.
* doc/tm.texi (HARD_REGNO_MODE_OK): Replace with...
(TARGET_HARD_REGNO_MODE_OK): ...this.
* doc/tm.texi.in: Regenerate.
* hooks.h (hook_bool_uint_mode_true): Declare.
* hooks.c (hook_bool_uint_mode_true): New function.
* doc/md.texi: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* genpreds.c (write_insn_preds_c): Add an include of target.h.
* alias.c (init_alias_target): Use targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* caller-save.c: Include target.h.
(reg_save_code): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* combine.c (can_combine_p): Likewise.
(combinable_i3pat): Likewise.
(can_change_dest_mode): Likewise.
* expr.c (init_expr_target): Likewise.
(convert_move): Likewise.
(convert_modes): Likewise.
* ira.c (setup_prohibited_class_mode_regs): Likewise.
(setup_prohibited_mode_move_regs): Likewise.
* ira.h (target_ira): Likewise.
* lra-assigns.c (find_hard_regno_for_1): Likewise.
* lra-constraints.c (process_alt_operands): Likewise.
(split_reg): Likewise.
* recog.c (peep2_find_free_register): Likewise.
* ree.c (combine_reaching_defs): Likewise.
* regcprop.c (maybe_mode_change): Likewise.
* reginfo.c (init_reg_sets_1): Likewise.
(choose_hard_reg_mode): Likewise.
(simplifiable_subregs): Likewise.
* regrename.c (check_new_reg_p): Likewise.
* reload.c (find_valid_class): Likewise.
(find_valid_class_1): Likewise.
(reload_inner_reg_of_subreg): Likewise.
(push_reload): Likewise.
(combine_reloads): Likewise.
(find_dummy_reload): Likewise.
(find_reloads): Likewise.
* reload1.c (find_reg): Likewise.
(set_reload_reg): Likewise.
(allocate_reload_reg): Likewise.
(choose_reload_regs): Likewise.
(reload_adjust_reg_for_temp): Likewise.
* rtlanal.c (subreg_size_offset_from_lsb): Likewise.
(simplify_subreg_regno): Likewise.
* sel-sched.c (init_regs_for_mode): Likewise.
* varasm.c (make_decl_rtl): Likewise.
* config/aarch64/aarch64.h (HARD_REGNO_MODE_OK): Delete.
(MODES_TIEABLE_P): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/aarch64/aarch64-protos.h (aarch64_hard_regno_mode_ok): Delete.
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/alpha/alpha.h (HARD_REGNO_MODE_OK): Delete.
* config/alpha/alpha.c (alpha_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/arc/arc.h (arc_hard_regno_mode_ok): Delete.
(arc_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/arc/arc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(arc_hard_regno_mode_ok): Rename old array to...
(arc_hard_regno_mode_ok_modes): ...this.
(arc_conditional_register_usage): Update accordingly.
(arc_mode_class): Make static.
(arc_hard_regno_mode_ok): New function.
* config/arm/arm.h (HARD_REGNO_MODE_OK): Delete.
* config/arm/arm-protos.h (arm_hard_regno_mode_ok): Delete.
* config/arm/arm.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(arm_hard_regno_mode_ok): Make static.
* config/arm/arm.md (movdi): Use targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/avr/avr-protos.h (avr_hard_regno_mode_ok): Delete.
* config/avr/avr.h (HARD_REGNO_MODE_OK): Delete.
* config/avr/avr.c (avr_hard_regno_mode_ok): Make static and
return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/bfin/bfin-protos.h (hard_regno_mode_ok): Delete.
* config/bfin/bfin.h (HARD_REGNO_MODE_OK): Delete.
* config/bfin/bfin.c (hard_regno_mode_ok): Rename to...
(bfin_hard_regno_mode_ok): ...this. Make static and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/bfin/predicates.md (valid_reg_operand): Use
targetm.hard_regno_mode_ok instead of HARD_REGNO_MODE_OK.
* config/c6x/c6x.h (HARD_REGNO_MODE_OK): Delete.
* config/c6x/c6x.c (c6x_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/cr16/cr16.h (HARD_REGNO_MODE_OK): Delete.
* config/cr16/cr16-protos.h (cr16_hard_regno_mode_ok): Delete.
* config/cr16/cr16.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(cr16_hard_regno_mode_ok): Make static and return a bool.
* config/cris/cris.h (HARD_REGNO_MODE_OK): Delete.
* config/cris/cris.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(cris_hard_regno_mode_ok): New function.
* config/epiphany/epiphany.h (epiphany_hard_regno_mode_ok): Delete.
(epiphany_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/epiphany/epiphany-protos.h (hard_regno_mode_ok): Delete.
* config/epiphany/epiphany.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(hard_regno_mode_ok): Rename to...
(epiphany_hard_regno_mode_ok): ...this. Make static and return a bool.
* config/fr30/fr30.h (HARD_REGNO_MODE_OK): Delete.
* config/fr30/fr30.md: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/frv/frv.h (HARD_REGNO_MODE_OK): Delete.
* config/frv/frv-protos.h (frv_hard_regno_mode_ok): Delete.
* config/frv/frv.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(frv_hard_regno_mode_ok): Make static and return a bool.
* config/frv/frv.md: Refer to targetm.hard_regno_mode_ok instead of
HARD_REGNO_MODE_OK.
* config/ft32/ft32.h (HARD_REGNO_MODE_OK): Delete.
* config/h8300/h8300.h (HARD_REGNO_MODE_OK): Delete.
* config/h8300/h8300-protos.h (h8300_hard_regno_mode_ok): Delete.
* config/h8300/h8300.c (h8300_hard_regno_mode_ok): Make static
and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/i386/i386.h (HARD_REGNO_MODE_OK): Delete.
* config/i386/i386-protos.h (ix86_hard_regno_mode_ok): Delete.
* config/i386/i386.c (ix86_hard_regno_mode_ok): Make static and
return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/ia64/ia64.h (HARD_REGNO_MODE_OK): Delete.
* config/ia64/ia64.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(ia64_hard_regno_mode_ok): New function.
* config/iq2000/iq2000.h (HARD_REGNO_MODE_OK): Delete.
* config/iq2000/iq2000.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(iq2000_hard_regno_mode_ok): New function.
* config/lm32/lm32.h (HARD_REGNO_MODE_OK): Delete.
* config/lm32/lm32.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(lm32_hard_regno_mode_ok): New function.
* config/m32c/m32c.h (HARD_REGNO_MODE_OK): Delete.
* config/m32c/m32c-protos.h (m32c_hard_regno_ok): Delete.
* config/m32c/m32c.c (class_can_hold_mode): Use m32c_hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
(m32c_hard_regno_ok): Rename to...
(m32c_hard_regno_mode_ok): ...this. Make static and return a bool.
(m32c_cannot_change_mode_class): Update accordingly.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/m32r/m32r.h (m32r_hard_regno_mode_ok): Delete.
(m32r_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/m32r/m32r.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(m32r_hard_regno_mode_ok): Rename to...
(m32r_hard_regno_modes): ...this.
(m32r_mode_class): Make static.
(m32r_hard_regno_mode_ok): New function.
* config/m68k/m68k.h (HARD_REGNO_MODE_OK): Delete.
* config/m68k/m68k-protos.h (m68k_regno_mode_ok): Delete.
* config/m68k/m68k.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(m68k_hard_regno_mode_ok): Make static.
* config/mcore/mcore.h (HARD_REGNO_MODE_OK): Delete.
* config/mcore/mcore.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(mcore_hard_regno_mode_ok): New function.
* config/microblaze/microblaze.h (microblaze_hard_regno_mode_ok)
(HARD_REGNO_MODE_OK): Delete.
* config/microblaze/microblaze.c (microblaze_hard_regno_mode_ok):
Rename to...
(microblaze_hard_regno_mode_ok_p): ...this and make static.
(microblaze_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/mips/mips.h (HARD_REGNO_MODE_OK): Delete.
(mips_hard_regno_mode_ok): Delete.
* config/mips/mips.c (mips_hard_regno_mode_ok): Rename to...
(mips_hard_regno_mode_ok_p): ...this and make static.
(mips_hard_regno_mode_ok_p): Rename to...
(mips_hard_regno_mode_ok_uncached): ...this.
(mips_hard_regno_mode_ok): New function.
(mips_class_max_nregs): Use mips_hard_regno_mode_ok instead
of HARD_REGNO_MODE_OK.
(mips_option_override): Update after above name changes.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/mmix/mmix.h (HARD_REGNO_MODE_OK): Delete.
* config/mn10300/mn10300.h (HARD_REGNO_MODE_OK): Delete.
* config/mn10300/mn10300-protos.h (mn10300_hard_regno_mode_ok): Delete.
* config/mn10300/mn10300.c (mn10300_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/moxie/moxie.h (HARD_REGNO_MODE_OK): Delete.
* config/msp430/msp430.h (HARD_REGNO_MODE_OK): Delete.
* config/msp430/msp430-protos.h (msp430_hard_regno_mode_ok): Delete.
* config/msp430/msp430.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(msp430_hard_regno_mode_ok): Make static and return a bool.
* config/nds32/nds32.h (HARD_REGNO_MODE_OK): Delete.
* config/nds32/nds32-protos.h (nds32_hard_regno_mode_ok): Delete.
* config/nds32/nds32.c (nds32_hard_regno_mode_ok): Make static
and return a bool.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/nios2/nios2.h (HARD_REGNO_MODE_OK): Delete.
* config/nvptx/nvptx.h (HARD_REGNO_MODE_OK): Delete.
* config/pa/pa.h (MODES_TIEABLE_P): Update commentary.
* config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): Rename to...
(PA_HARD_REGNO_MODE_OK): ...this
* config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Rename to...
(PA_HARD_REGNO_MODE_OK): ...this.
* config/pa/pa.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(pa_hard_regno_mode_ok): New function.
* config/pdp11/pdp11.h (HARD_REGNO_MODE_OK): Delete.
* config/pdp11/pdp11.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(pdp11_hard_regno_mode_ok): New function.
* config/powerpcspe/powerpcspe.h (HARD_REGNO_MODE_OK): Delete.
* config/powerpcspe/powerpcspe-protos.h (rs6000_hard_regno_mode_ok_p):
Delete.
* config/powerpcspe/powerpcspe.c (rs6000_hard_regno_mode_ok_p):
Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(rs6000_hard_regno_mode_ok): Rename to...
(rs6000_hard_regno_mode_ok_uncached): ...this.
(rs6000_init_hard_regno_mode_ok): Update accordingly.
(rs6000_hard_regno_mode_ok): New function.
* config/riscv/riscv.h (HARD_REGNO_MODE_OK): Delete.
* config/riscv/riscv-protos.h (riscv_hard_regno_mode_ok_p): Delete.
* config/riscv/riscv.c (riscv_hard_regno_mode_ok_p): Rename to...
(riscv_hard_regno_mode_ok): ...this and make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/rl78/rl78.h (HARD_REGNO_MODE_OK): Delete.
* config/rl78/rl78-protos.h (rl78_hard_regno_mode_ok): Delete.
* config/rl78/rl78.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(rl78_hard_regno_mode_ok): Make static and return bool.
* config/rs6000/rs6000.h (HARD_REGNO_MODE_OK): Delete.
* config/rs6000/rs6000-protos.h (rs6000_hard_regno_mode_ok_p):
Delete.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok_p): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(rs6000_hard_regno_mode_ok): Rename to...
(rs6000_hard_regno_mode_ok_uncached): ...this.
(rs6000_init_hard_regno_mode_ok): Update accordingly.
(rs6000_hard_regno_mode_ok): New function.
* config/rx/rx.h (HARD_REGNO_MODE_OK): Delete.
* config/rx/rx.c (rx_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/s390/s390.h (HARD_REGNO_MODE_OK): Delete.
* config/s390/s390-protos.h (s390_hard_regno_mode_ok): Delete.
* config/s390/s390.c (s390_hard_regno_mode_ok): Make static.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/sh/sh.h (HARD_REGNO_MODE_OK): Delete.
* config/sh/sh-protos.h (sh_hard_regno_mode_ok): Delete.
* config/sh/sh.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(sh_hard_regno_mode_ok): Make static.
* config/sparc/constraints.md: Refer to targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* config/sparc/sparc.h (hard_regno_mode_classes): Delete.
(sparc_mode_class): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/sparc/sparc.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(hard_regno_mode_classes): Make static.
(sparc_mode_class): Likewise.
(sparc_hard_regno_mode_ok): New function.
* config/spu/spu.h (HARD_REGNO_MODE_OK): Delete.
* config/stormy16/stormy16.h (HARD_REGNO_MODE_OK): Delete.
* config/stormy16/stormy16.c (xstormy16_hard_regno_mode_ok): New
function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/tilegx/tilegx.h (HARD_REGNO_MODE_OK): Delete.
* config/tilepro/tilepro.h (HARD_REGNO_MODE_OK): Delete.
* config/v850/v850.h (HARD_REGNO_MODE_OK): Delete.
* config/v850/v850.c (v850_hard_regno_mode_ok): New function.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
* config/vax/vax.h (HARD_REGNO_MODE_OK): Delete.
* config/visium/visium.h (HARD_REGNO_MODE_OK): Delete.
* config/visium/visium.c (TARGET_HARD_REGNO_MODE_OK): Redefine.
(visium_hard_regno_mode_ok): New function.
* config/visium/visium.md: Refer to targetm.hard_regno_mode_ok
instead of HARD_REGNO_MODE_OK.
* config/xtensa/xtensa.h (xtensa_hard_regno_mode_ok): Delete.
(HARD_REGNO_MODE_OK): Delete.
* config/xtensa/xtensa.c (xtensa_hard_regno_mode_ok): Rename to...
(xtensa_hard_regno_mode_ok_p): ...this and make static.
(xtensa_option_override): Update accordingly.
(TARGET_HARD_REGNO_MODE_OK): Redefine.
(xtensa_hard_regno_mode_ok): New function.
* system.h (HARD_REGNO_MODE_OK): Poison.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251646
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* config/s390/s390.md (mem_signal_fence): Remove.
* doc/md.texi (mem_signal_fence): Remove.
* optabs.c (expand_mem_signal_fence): Remove uses of mem_signal_fence.
Update comments.
* target-insns.def (mem_signal_fence): Remove.
From-SVN: r251597
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PR target/80640
* doc/md.texi (mem_thread_fence): Remove mention of mode. Rewrite.
* optabs.c (expand_mem_thread_fence): Emit a compiler barrier when
using targetm.gen_mem_thread_fence.
testsuite/
* gcc.dg/atomic/pr80640.c: New testcase.
From-SVN: r251377
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128b right away, to be more efficient for Ryzen and Intel)
PR target/80846
* optabs.def (vec_extract_optab, vec_init_optab): Change from
a direct optab to conversion optab.
* optabs.c (expand_vector_broadcast): Use convert_optab_handler
with GET_MODE_INNER as last argument instead of optab_handler.
* expmed.c (extract_bit_field_1): Likewise. Use vector from
vector extraction if possible and optab is available.
* expr.c (store_constructor): Use convert_optab_handler instead
of optab_handler. Use vector initialization from smaller
vectors if possible and optab is available.
* tree-vect-stmts.c (vectorizable_load): Likewise.
* doc/md.texi (vec_extract, vec_init): Document that the optabs
now have two modes.
* config/i386/i386.c (ix86_expand_vector_init): Handle expansion
of vec_init from half-sized vectors with the same element mode.
* config/i386/sse.md (ssehalfvecmode): Add V4TI case.
(ssehalfvecmodelower, ssescalarmodelower): New mode attributes.
(reduc_plus_scal_v8df, reduc_plus_scal_v4df, reduc_plus_scal_v2df,
reduc_plus_scal_v16sf, reduc_plus_scal_v8sf, reduc_plus_scal_v4sf,
reduc_<code>_scal_<mode>, reduc_umin_scal_v8hi): Add element mode
after mode in gen_vec_extract* calls.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><ssescalarmodelower>): ... this.
(vec_extract<mode><ssehalfvecmodelower>): New expander.
(rotl<mode>3, rotr<mode>3, <shift_insn><mode>3, ashrv2di3): Add
element mode after mode in gen_vec_init* calls.
(VEC_INIT_HALF_MODE): New mode iterator.
(vec_init<mode>): Renamed to ...
(vec_init<mode><ssescalarmodelower>): ... this.
(vec_init<mode><ssehalfvecmodelower>): New expander.
* config/i386/mmx.md (vec_extractv2sf): Renamed to ...
(vec_extractv2sfsf): ... this.
(vec_initv2sf): Renamed to ...
(vec_initv2sfsf): ... this.
(vec_extractv2si): Renamed to ...
(vec_extractv2sisi): ... this.
(vec_initv2si): Renamed to ...
(vec_initv2sisi): ... this.
(vec_extractv4hi): Renamed to ...
(vec_extractv4hihi): ... this.
(vec_initv4hi): Renamed to ...
(vec_initv4hihi): ... this.
(vec_extractv8qi): Renamed to ...
(vec_extractv8qiqi): ... this.
(vec_initv8qi): Renamed to ...
(vec_initv8qiqi): ... this.
* config/rs6000/vector.md (VEC_base_l): New mode attribute.
(vec_init<mode>): Renamed to ...
(vec_init<mode><VEC_base_l>): ... this.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><VEC_base_l>): ... this.
* config/rs6000/paired.md (vec_initv2sf): Renamed to ...
(vec_initv2sfsf): ... this.
* config/rs6000/altivec.md (splitter, altivec_copysign_v4sf3,
vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
vec_unpacku_lo_v8hi, mulv16qi3, altivec_vreve<mode>2): Add
element mode after mode in gen_vec_init* calls.
* config/aarch64/aarch64-simd.md (vec_init<mode>): Renamed to ...
(vec_init<mode><Vel>): ... this.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><Vel>): ... this.
* config/aarch64/iterators.md (Vel): New mode attribute.
* config/s390/s390.c (s390_expand_vec_strlen, s390_expand_vec_movstr):
Add element mode after mode in gen_vec_extract* calls.
* config/s390/vector.md (non_vec_l): New mode attribute.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><non_vec_l>): ... this.
(vec_init<mode>): Renamed to ...
(vec_init<mode><non_vec_l>): ... this.
* config/s390/s390-builtins.def (s390_vlgvb, s390_vlgvh, s390_vlgvf,
s390_vlgvf_flt, s390_vlgvg, s390_vlgvg_dbl): Add element mode after
vec_extract mode.
* config/arm/iterators.md (V_elem_l): New mode attribute.
* config/arm/neon.md (vec_extract<mode>): Renamed to ...
(vec_extract<mode><V_elem_l>): ... this.
(vec_extractv2di): Renamed to ...
(vec_extractv2didi): ... this.
(vec_init<mode>): Renamed to ...
(vec_init<mode><V_elem_l>): ... this.
(reduc_plus_scal_<mode>, reduc_plus_scal_v2di, reduc_smin_scal_<mode>,
reduc_smax_scal_<mode>, reduc_umin_scal_<mode>,
reduc_umax_scal_<mode>, neon_vget_lane<mode>, neon_vget_laneu<mode>):
Add element mode after gen_vec_extract* calls.
* config/mips/mips-msa.md (vec_init<mode>): Renamed to ...
(vec_init<mode><unitmode>): ... this.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><unitmode>): ... this.
* config/mips/loongson.md (vec_init<mode>): Renamed to ...
(vec_init<mode><unitmode>): ... this.
* config/mips/mips-ps-3d.md (vec_initv2sf): Renamed to ...
(vec_initv2sfsf): ... this.
(vec_extractv2sf): Renamed to ...
(vec_extractv2sfsf): ... this.
(reduc_plus_scal_v2sf, reduc_smin_scal_v2sf, reduc_smax_scal_v2sf):
Add element mode after gen_vec_extract* calls.
* config/mips/mips.md (unitmode): New mode iterator.
* config/spu/spu.c (spu_expand_prologue, spu_allocate_stack,
spu_builtin_extract): Add element mode after gen_vec_extract* calls.
* config/spu/spu.md (inner_l): New mode attribute.
(vec_init<mode>): Renamed to ...
(vec_init<mode><inner_l>): ... this.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><inner_l>): ... this.
* config/sparc/sparc.md (veltmode): New mode iterator.
(vec_init<VMALL:mode>): Renamed to ...
(vec_init<VMALL:mode><VMALL:veltmode>): ... this.
* config/ia64/vect.md (vec_initv2si): Renamed to ...
(vec_initv2sisi): ... this.
(vec_initv2sf): Renamed to ...
(vec_initv2sfsf): ... this.
(vec_extractv2sf): Renamed to ...
(vec_extractv2sfsf): ... this.
* config/powerpcspe/vector.md (VEC_base_l): New mode attribute.
(vec_init<mode>): Renamed to ...
(vec_init<mode><VEC_base_l>): ... this.
(vec_extract<mode>): Renamed to ...
(vec_extract<mode><VEC_base_l>): ... this.
* config/powerpcspe/paired.md (vec_initv2sf): Renamed to ...
(vec_initv2sfsf): ... this.
* config/powerpcspe/altivec.md (splitter, altivec_copysign_v4sf3,
vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
vec_unpacku_lo_v8hi, mulv16qi3): Add element mode after mode in
gen_vec_init* calls.
From-SVN: r250759
|
|
This patch tries to clarify some of the restrictions on define_insn
conditions, and also on the use of "#".
2017-06-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* doc/md.texi: Clarify the restrictions on a define_insn condition.
Say that # requires an associated define_split to exist, and that
the define_split must be suitable for use after register allocation.
From-SVN: r248946
|
|
to match 'config/i386/constraints.md'.
* doc/md.texi (Machine Constraints): Update x86 family
machine constraints section to match 'config/i386/constraints.md'.
From-SVN: r248468
|
|
instructions that inherently set a condition...
* doc/md.texi (Canonicalization of Instructions): Describe the
canonical form of instructions that inherently set a condition
code register.
From-SVN: r248156
|
|
-mcpu=power9)
2017-03-21 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
PR target/80123
* doc/md.texi (Constraints): Document wA constraint.
* config/rs6000/constraints.md (wA): New.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
(rs6000_init_hard_regno_mode_ok): Init wA constraint.
* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.
From-SVN: r246394
|
|
gcc/ChangeLog:
* doc/extend.texi: Use "cannot" instead of "can't."
* doc/hostconfig.texi: Same.
* doc/install.texi: Same.
* doc/invoke.texi: Same.
* doc/loop.texi: Same.
* doc/md.texi: Same.
* doc/objc.texi: Same.
* doc/rtl.texi: Same.
* doc/tm.texi: Same.
* doc/tm.texi.in: Same.
* doc/trouble.texi: Same.
From-SVN: r246334
|
|
gcc/ChangeLog:
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.c: New file.
* gcc/common/config/riscv/riscv-common.c: Likewise.
* config.gcc: Likewise.
* config/riscv/constraints.md: Likewise.
* config/riscv/elf.h: Likewise.
* config/riscv/generic.md: Likewise.
* config/riscv/linux.h: Likewise.
* config/riscv/multilib-generator: Likewise.
* config/riscv/peephole.md: Likewise.
* config/riscv/pic.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.c: Likewise.
* config/riscv/riscv-c.c: Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-modes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/sync.md: Likewise.
* config/riscv/t-elf-multilib: Likewise.
* config/riscv/t-linux: Likewise.
* config/riscv/t-linux-multilib: Likewise.
* config/riscv/t-riscv: Likewise.
* configure.ac: Likewise.
* doc/contrib.texi: Add Kito Cheng, Palmer Dabbelt, and Andrew
Waterman as RISC-V maintainers.
* doc/install.texi: Add RISC-V entries.
* doc/invoke.texi: Add RISC-V options section.
* doc/md.texi: Add RISC-V constraints section.
From-SVN: r245224
|
|
2017-01-10 Sandra Loosemore <sandra@codesourcery.com>
gcc/
* doc/extend.texi: Tweak formatting to fix overfull hbox warnings.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* doc/objc.texi: Likewise.
From-SVN: r244286
|
|
From-SVN: r244023
|
|
From-SVN: r243994
|
|
integers (and eventually 8/16-bit...
[gcc]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wH constraint): Add new
constraints for allowing 32-bit integers (and eventually 8/16-bit
integers) into the vector registers.
(wI constraint): Likewise.
(wJ constraint): Likewise.
(wK constraint): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mvsx-small-integer as a default option for ISA 2.07
(i.e. power8).
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
switch to turn off small integer support in vector registers.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
test for -mupper-regs-di, since it is already done with the
reg_add[mode].scalar_in_vsx_p. Add support for the switch
-mvsx-small-integer.
(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
constraints.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Add consistency checks for
-mvsx-small-integer.
(rs6000_secondary_reload_simple_move): SImode is a simple move if
-mvsx-small-integer.
(rs6000_secondary_reload): Use std::swap.
(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
VSX_REGS for small integers in vector registers, since there is no
D-FORM address mode for such types.
(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
(rs6000_opt_masks): Add -mvsx-small-integer.
* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
support.
(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
extracts can be done on ISA 2.07.
(vsx_extract_<mode>): Add support for small integers in vsx
registers.
(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
(vsx_extract_si): New insn to support extraction of SImode in ISA
2.07 using either xxextractuw or vspltw.
(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
wJ, and wK constraints.
* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
storing SDmode with VSX instructions.
(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
GPR load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add MFVSRWZ and XXEXTRACTUW instructions to support
small integers in vector registers.
(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add VEXTSW2D support for small integers in vector
registers.
(lfiwax): Remove ! constraint. Add VEXTSW2D support for small
integers in vector registers.
(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(lfiwzx): Remove ! constraint. Add XXEXTRACTUW support for small
integers in vector registers.
(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(movsi_internal1): Add support for -mvsx-small-integer. Align
columns so that it is more readable.
(SImode splitter for ISA 3.0 constants): Add splitter for
-128..127 constants that can easily be constructed on ISA 3.0.
* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
constraints.
[gcc/testsuite]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-simode.c: New test.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
From-SVN: r241631
|
|
PR target/78102
* optabs.def (vcondeq_optab, vec_cmpeq_optab): New optabs.
* optabs.c (expand_vec_cond_expr): For comparison codes
EQ_EXPR and NE_EXPR, attempt vcondeq_optab as fallback.
(expand_vec_cmp_expr): For comparison codes
EQ_EXPR and NE_EXPR, attempt vec_cmpeq_optab as fallback.
* optabs-tree.h (expand_vec_cmp_expr_p, expand_vec_cond_expr_p):
Add enum tree_code argument.
* optabs-query.h (get_vec_cmp_eq_icode, get_vcond_eq_icode): New
inline functions.
* optabs-tree.c (expand_vec_cmp_expr_p): Add CODE argument. For
CODE EQ_EXPR or NE_EXPR, attempt to use vec_cmpeq_optab as
fallback.
(expand_vec_cond_expr_p): Add CODE argument. For CODE EQ_EXPR or
NE_EXPR, attempt to use vcondeq_optab as fallback.
* tree-vect-generic.c (expand_vector_comparison,
expand_vector_divmod, expand_vector_condition): Adjust
expand_vec_cmp_expr_p and expand_vec_cond_expr_p callers.
* tree-vect-stmts.c (vectorizable_condition,
vectorizable_comparison): Likewise.
* tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern,
check_bool_pattern, search_type_for_mask_1): Likewise.
* expr.c (do_store_flag): Likewise.
* doc/md.texi (@code{vec_cmpeq@var{m}@var{n}},
@code{vcondeq@var{m}@var{n}}): Document.
* config/i386/sse.md (vec_cmpeqv2div2di, vcondeq<VI8F_128:mode>v2di):
New expanders.
testsuite/
* gcc.target/i386/pr78102.c: New test.
From-SVN: r241525
|
|
Revert a part of the `d' constraint documentation update made with
commit 111868 ("Use define_constraint for MIPS"),
<https://gcc.gnu.org/ml/gcc-patches/2006-03/msg00460.html>,
<https://gcc.gnu.org/ml/gcc-patches/2006-03/msg00541.html>, which
inadvertently made the registers covered to be referred to as "address"
rather than "general-purpose" registers, and then further clarify the
set of registers allowed with MIPS16 code.
* config/mips/constraints.md (d): Fix documentation.
* doc/md.texi (Machine Constraints): Update accordingly.
From-SVN: r240546
|
|
* doc/extend.texi: Use lowercase "boolean".
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* target.def: Likewise.
* doc/tm.texi: Regenerated.
From-SVN: r240091
|
|
certain error messages make mention of undocumented...
gcc/ChangeLog:
2016-07-22 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
comments to explain why certain error messages make mention of
undocumented options.
(rs6000_invalid_builtin): Change error messages to replace mention
of undocumented options with mention of the -mcpu=power9 option
that enables those undocumented options.
* config/rs6000/rs6000.h (MASK_FLOAT128): New macro.
(RS6000_BTM_FLOAT128): Use the new MASK_FLOAT128 macro in the
definition of this macro to correct an existing error.
* config/rs6000/rs6000.opt: Add the Undocumented qualifier to the
mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify
descriptions of built-in functions so that they depend on
-mcpu=power9 instead of on the corresponding undocumented flags.
* doc/invoke.texi (Option Summary): Remove all mention of newly
undocumented flags.
(IBM RS/6000 and PowerPC Options): Likewise.
* doc/md.texi (Constraints for Particuliar Machines): Remove all
mention of newly undocumented flags.
From-SVN: r238648
|
|
libgcc/ChangeLog:
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config.host: Remove support for mep-*.
* config/mep/lib1funcs.S: Remove.
* config/mep/lib2funcs.c: Remove.
* config/mep/t-mep: Remove.
* config/mep/tramp.c: Remove.
gcc/ChangeLog:
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* common/config/mep/mep-common.c: Remove.
* config.gcc: Remove mep-* support.
* config/mep/constraints.md: Remove.
* config/mep/default.h: Remove.
* config/mep/intrinsics.h: Remove.
* config/mep/intrinsics.md: Remove.
* config/mep/ivc2-template.h: Remove.
* config/mep/mep-c5.cpu: Remove.
* config/mep/mep-core.cpu: Remove.
* config/mep/mep-default.cpu: Remove.
* config/mep/mep-ext-cop.cpu: Remove.
* config/mep/mep-intrin.h: Remove.
* config/mep/mep-ivc2.cpu: Remove.
* config/mep/mep-pragma.c: Remove.
* config/mep/mep-protos.h: Remove.
* config/mep/mep.c: Remove.
* config/mep/mep.cpu: Remove.
* config/mep/mep.h: Remove.
* config/mep/mep.md: Remove.
* config/mep/mep.opt: Remove.
* config/mep/predicates.md: Remove.
* config/mep/t-mep: Remove.
* doc/install.texi: Remove mep-* documentation.
* doc/md.texi: Likewise.
gcc/testsuite/ChangeLog:
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* gcc.dg/tree-ssa/forwprop-28.c: Remove mep-* support.
* gcc.dg/tree-ssa/reassoc-32.c: Likewise.
* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-2.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-3.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise.
* gcc.dg/tree-ssa/ssa-thread-11.c: Likewise.
* gcc.dg/tree-ssa/vrp87.c: Likewise.
* lib/target-supports.exp: Likewise.
contrib/ChangeLog:
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* config-list.mk: Stop testing mep-elf.
libstdc++-v3/ChangeLog:
2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* configure.host: Remove mep-* support.
From-SVN: r237666
|
|
XXSPLTIB in vector registers.
[gcc]
2016-06-15 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (VSINT_84): Add DImode to enable loading
DImode constants with XXSPLTIB in vector registers.
(vsx_extract_<mode>, V2DImode/V2DFmode): Combine both
vsx_extract_<mode>_internal{1,2} into a single insn that handles
direct move (both ISA 2.07 and ISA 3.0 versions), and optimizes
extraction of the element at the top of the register as a scalar
value.
(vsx_extract_<mode>_internal1): Likewise.
(vsx_extract_<mode>_internal2): Likewise.
* config/rs6000/constraints.md (wi constraint): Remove a comment
about DImode not being allowed in Altivec registers.
(wB constraint): New constraint for constants that can be
generated in Altivec registers with VSPLTISW/VUPKHSW.
* config/rs6000/predicates.md (xxspltib_constant_split): Update
comments.
(xxspltib_constant_nosplit): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Add
support for -mupper-regs-di to enable DImode to go into Altivec
registers.
(POWERPC_MASKS): Likewise.
(power7 cpu): Likewise.
* config/rs6000/rs6000.opt (-mupper-regs-di): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support
for DImode being allowed in Altivec registers. Update wi/wj
constraints. Set scalar_in_vmx_p flag.
(rs6000_option_override_internal): Add checks for -mupper-regs-di.
(xxspltib_constant_p): Allow CONST_INT's with VOIDmode. Don't
return true if we could use VSPLTISW/VUPKHSW instead of XXSPLTIB.
(rs6000_opt_masks): Add -mupper-regs-di.
* config/rs6000/rs6000.md (lfiwax): Update clobbers that don't use
direct move to use wi and not wj.
(lfiwzx): Likewise.
(floatsi<mode>2_lfiwax_mem): Combine alternatives into a single
alternative.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(fix_trunc<mode>di2_fctidz): Change second alternative to allow
any VSX register, instead of just Altivec registers, to allow
either operand to be an Altivec register or both.
(fixuns_trunc<mode>di2_fctiduz): Likewise.
(movdi_internal32): Add support for -mupper-regs-di. Add support
to load constants via XXSPLTIB or VSPLTISW. Add spacing to allow
the alternatives and attributes to be lined up to be easier to
read.
(movdi_internal64): Likewise.
(64-bit DImode splitters): Change predicates to only split loading
up GPR registers. Add splits for using XXSPLTIB or VSPLTISW to
load constants in ISA 3.0 or ISA 2.07 respectively.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs-di. Update -mupper-regs-df and -mupper-regs-sf to
mention -mcpu=power9 sets these options.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
wB constraint.
[gcc/testsuite]
2016-06-15 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-dimode1.c: New test.
* gcc.target/powerpc/p9-dimode2.c: Likewise.
From-SVN: r237490
|
|
In ISO C99/C11, the ceil, floor, round and trunc functions may or may
not raise the "inexact" exception for noninteger arguments. Under TS
18661-1:2014, the C bindings for IEEE 754-2008, these functions are
prohibited from raising "inexact", in line with the general rule that
"inexact" is only when the mathematical infinite precision result of a
function differs from the result after rounding to the target type.
GCC has no option to select TS 18661 requirements for not raising
"inexact" when expanding built-in versions of these functions inline.
Furthermore, even given such requirements, the conditions on the x86
insn patterns for these functions are unnecessarily restrictive. I'd
like to make the out-of-line glibc versions follow the TS 18661
requirements; in the cases where this slows them down (the cases using
x87 floating point), that makes it more important for inline versions
to be used when the user does not care about "inexact".
This patch fixes these issues. A new option
-fno-fp-int-builtin-inexact is added to request TS 18661 rules for
these functions; the default -ffp-int-builtin-inexact reflects that
such exceptions are allowed by C99 and C11. (The intention is that if
C2x incorporates TS 18661-1, then the default would change in C2x
mode.)
The x86 built-ins for rint (x87, SSE2 and SSE4.1) are made
unconditionally available (no longer depending on
-funsafe-math-optimizations or -fno-trapping-math); "inexact" is
correct for noninteger arguments to rint. For floor, ceil and trunc,
the x87 and SSE2 built-ins are OK if -ffp-int-builtin-inexact or
-fno-trapping-math (they may raise "inexact" for noninteger
arguments); the SSE4.1 built-ins are made to use ROUND_NO_EXC so that
they do not raise "inexact" and so are OK unconditionally.
Now, while there was no semantic reason for depending on
-funsafe-math-optimizations, the insn patterns had such a dependence
because of use of gen_truncxf<mode>2_i387_noop to truncate back to
SFmode or DFmode after using frndint in XFmode. In this case a no-op
truncation is safe because rounding to integer always produces an
exactly representable value (the same reason why IEEE semantics say it
shouldn't produce "inexact") - but of course that insn pattern isn't
safe because it would also match cases where the truncation is not in
fact a no-op. To allow frndint to be used for SFmode and DFmode
without that unsafe pattern, the relevant frndint patterns are
extended to SFmode and DFmode or new SFmode and DFmode patterns added,
so that the frndint operation can be represented in RTL as an
operation acting directly on SFmode or DFmode without the extension
and the problematic truncation.
A generic test of the new option is added, as well as x86-specific
tests, both execution tests including the generic test with different
x86 options and scan-assembler tests verifying that functions that
should be inlined with different options are indeed inlined.
I think other architectures are OK for TS 18661-1 semantics already.
Considering those defining "ceil" patterns: aarch64, arm, rs6000, s390
use instructions that do not raise "inexact"; nvptx does not support
floating-point exceptions. (This does mean the -f option in fact only
affects one architecture, but I think it should still be a -f option;
it's logically architecture-independent and is expected to be affected
by future -std options, so is similar to e.g. -fexcess-precision=,
which also does nothing on most architectures but is implied by -std
options.)
Bootstrapped with no regressions on x86_64-pc-linux-gnu. OK to
commit?
PR target/71276
PR target/71277
gcc:
* common.opt (ffp-int-builtin-inexact): New option.
* doc/invoke.texi (-fno-fp-int-builtin-inexact): Document.
* doc/md.texi (floor@var{m}2, btrunc@var{m}2, round@var{m}2)
(ceil@var{m}2): Document dependence on this option.
* ipa-inline-transform.c (inline_call): Handle
flag_fp_int_builtin_inexact.
* ipa-inline.c (can_inline_edge_p): Likewise.
* config/i386/i386.md (rintxf2): Do not test
flag_unsafe_math_optimizations.
(rint<mode>2_frndint): New define_insn.
(rint<mode>2): Do not test flag_unsafe_math_optimizations for 387
or !flag_trapping_math for SSE. Just use gen_rint<mode>2_frndint
for 387 instead of extending and truncating.
(frndintxf2_<rounding>): Test flag_fp_int_builtin_inexact ||
!flag_trapping_math instead of flag_unsafe_math_optimizations.
Change to frndint<mode>2_<rounding>.
(frndintxf2_<rounding>_i387): Likewise. Change to
frndint<mode>2_<rounding>_i387.
(<rounding_insn>xf2): Likewise.
(<rounding_insn><mode>2): Test flag_fp_int_builtin_inexact ||
!flag_trapping_math instead of flag_unsafe_math_optimizations for
x87. Test TARGET_ROUND || !flag_trapping_math ||
flag_fp_int_builtin_inexact instead of !flag_trapping_math for
SSE. Use ROUND_NO_EXC in constant operand of
gen_sse4_1_round<mode>2. Just use gen_frndint<mode>2_<rounding>
for 387 instead of extending and truncating.
gcc/testsuite:
* gcc.dg/torture/builtin-fp-int-inexact.c,
gcc.target/i386/387-builtin-fp-int-inexact.c,
gcc.target/i386/387-rint-inline-1.c,
gcc.target/i386/387-rint-inline-2.c,
gcc.target/i386/sse2-builtin-fp-int-inexact.c,
gcc.target/i386/sse2-rint-inline-1.c,
gcc.target/i386/sse2-rint-inline-2.c,
gcc.target/i386/sse4_1-builtin-fp-int-inexact.c,
gcc.target/i386/sse4_1-rint-inline.c: New tests.
From-SVN: r237074
|
|
[gcc]
2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70915
* config/rs6000/constraints.md (wE constraint): New constraint
for a vector constant that can be loaded with XXSPLTIB.
(wM constraint): New constraint for a vector constant of a 1's.
(wS constraint): New constraint for a vector constant that can be
loaded with XXSPLTIB and a vector sign extend instruction.
* config/rs6000/predicates.md (xxspltib_constant_split): New
predicates for wE/wS constraints.
(xxspltib_constant_nosplit): Likewise.
(easy_vector_constant): Add support for constants that can be
loaded via XXSPLTIB.
(all_ones_constant): New predicate for vector constant with all
1's set.
(splat_input_operand): Add support for ISA 3.0 word splat
operations.
* config/rs6000/rs6000.c (xxspltib_constant_p): New function to
return if a constant can be loaded with the ISA 3.0 XXSPLTIB
instruction and possibly with a sign extension.
(output_vec_const_move): Add support for XXSPLTIB. If we are
loading up 0/-1 into Altivec registers, prefer using VSPLTISW
instead of XXLXOR/XXLORC.
(rs6000_expand_vector_init): Add support for ISA 3.0 word splat
operations.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_output_move_128bit): Use output_vec_const_move to emit
constants.
* config/rs6000/vsx.md (VSX_M): Add TImode (if -mvsx-timode) and
combine VSX_M and VSX_M2 into one iterator.
(VSX_M2): Likewise.
(VSINT_84): New iterators for loading constants with XXSPLTIB.
(VSINT_842): Likewise.
(UNSPEC_VSX_SIGN_EXTEND): New UNSPEC.
(xxspltib_v16qi): New insns to load up constants with the ISA 3.0
XXSPLTIB instruction.
(xxspltib_<mode>_nosplit): Likewise.
(xxspltib_<mode>_split): New insn to load up constants with
XXSPLTIB and a sign extend instruction.
(vsx_mov<mode>): Replace single move that handled all vector types
with separate 32-bit and 64-bit moves. Combine the movti_<bit>
moves (when -mvsx-timode is in effect) into the main vector
moves. Eliminate separate moves for <VSr> <VSa>, where the
preferred register class (<VSr>) is listed first, and the
secondary register class (<VSa>) is listed second with a '?' to
discourage use. Prefer loading 0/-1 in any VSX register for ISA
3.0, and Altivec registers for ISA 2.06/2.07 (PR target/70915) so
that if the register was involved in a slow operation, the
clear/set operation does not wait for the slow operation to
finish. Adjust the length attributes for 32-bit mode. Use
rs6000_output_move_128bit and drop the use of the string
instructions for 32-bit movti when -mvsx-timode is in effect. Use
spacing so that the alternatives and attributes don't generate
long lines, and put things in columns, so that it is easier to
match up the operands and attributes with the insn alternatives.
(vsx_mov<mode>_64bit): Likewise.
(vsx_mov<mode>_32bit): Likewise.
(vsx_movti_64bit): Fold movti into normal vector moves.
(vsx_movti_32bit): Likewise.
(vsx_splat_<mode>, V4SI/V4SF modes): Add support for ISA 3.0 word
spat instructions.
(vsx_splat_v4si_internal): Likewise.
(vsx_splat_v4sf_internal): Likewise.
(vector fusion peepholes): Use VSX_M instead of VSX_M2.
(vsx_sign_extend_qi_<mode>): New ISA 3.0 instructions to sign
extend vector elements.
(vsx_sign_extend_hi_<mode>): Likewise.
(vsx_sign_extend_si_v2di): Likewise.
* config/rs6000/rs6000-protos.h (xxspltib_constant_p): Add
declaration.
* doc/md.texi (PowerPC constraints): Document the wE, wM, and wS
constraints. Add trailing period to wL documentation.
[gcc/testsuite]
2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-splat-1.c: New tests for ISA 3.0 word
splat operations and the XXSPLTIB instruction.
* gcc.target/powerpc/p9-splat-2.c: Likewise.
* gcc.target/powerpc/p9-splat-3.c: Likewise.
* gcc.target/powerpc/pr47755.c: Allow vspltisw in addition to
xxlxor to clear a register.
From-SVN: r236394
|
|
gcc/
* doc/cpp.texi (__GNUC__): Major version changes are no longer rare.
* doc/invoke.texi (-mnan=2008): Change signalling to signaling.
* doc/md.texi (fmin@var{m}3): Likewise.
From-SVN: r236340
|
|
quad_address_p and call it to share code with...
[gcc]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (quad_memory_operand): Move most of
the code into quad_address_p and call it to share code with
vsx_quad_dform_memory_operand.
(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
d-form support.
* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
bit instead of being a separate word. Split -mpower9-dform into
two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
for the register class supporting 128-bit quad word memory
offsets.
(mode_supports_vsx_dform_quad): Helper function to return if the
register class uses quad word memory offsets.
(rs6000_debug_addr_mask): Add support for quad word memory
offsets.
(rs6000_debug_reg_global): Always print if we are using LRA or
not.
(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
instructions are enabled, set up the appropriate addr_masks for
128-bit types.
(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
-mpower9-dform-scalar, instead of -mpower9-dform.
(rs6000_option_override_internal): Split -mpower9-dform into two
switches, -mpower9-dform-scalar and -mpower9-dform-vector. The
-mpower9-dform switch sets or clears both. If we are not using
the LRA register allocator, do not enable -mpower9-dform-vector by
default. If we are using LRA, enable -mpower9-dform-vector and
-mvsx-timode if it is appropriate. Issue a warning if either
-mpower9-dform-vector or -mvsx-timode are explicitly used without
enabling LRA.
(quad_address_offset_p): New helper function to return if the
offset is legal for quad word memory instructions.
(quad_address_p): New function to determin if GPR or vector
register quad word memory addresses are legal.
(mem_operand_gpr): Validate quad word address offsets.
(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
d-form (register + offset) instructions.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Add more debug statements for
-mdebug=addr.
(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
d-form instructions. Distinguish different cases in debug
output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
instructions. If ISA 3.0 is available, generate lxvx/stxvx instead
of the ISA 2.06 indexed memory instructions.
(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
use them to save/restore the saved vector registers instead of
using Altivec instructions.
(rs6000_emit_epilogue): Likewise.
(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
(rs6000_opt_masks): Split -mpower9-dform into
-mpower9-dform-scalar and -mpower9-dform-vector.
(rs6000_print_options_internal): Print -mno-<switch> if <switch>
was not selected.
* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
ISA 3.0 vector indexed memory instructions, and fold the code into
the normal mov<mode> patterns.
(p9_vecstore_<mode>): Likewise.
(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
instructions.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
* config/rs6000/constraints.md (wO constraint): New constraint for
ISA 3.0 vector d-form support.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
-mpower9-dform-scalar instead of -mpower9-dform. Add note not to
include -mpower9-dform-vector until we switch over to LRA.
(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two.
switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
for -mpower9-dform and -mlra.
* doc/md.texi (wO constraint): Document wO constraint.
[gcc/testsuite]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
support.
* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
warning when using -mvsx-timode.
* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.
From-SVN: r236133
|
|
bts/btr/btc')
PR target/49244
* tree-ssa-ccp.c: Include stor-layout.h and optabs-query.h.
(optimize_atomic_bit_test_and): New function.
(pass_fold_builtins::execute): Use it.
* optabs.def (atomic_bit_test_and_set_optab,
atomic_bit_test_and_complement_optab,
atomic_bit_test_and_reset_optab): New optabs.
* internal-fn.def (ATOMIC_BIT_TEST_AND_SET,
ATOMIC_BIT_TEST_AND_COMPLEMENT, ATOMIC_BIT_TEST_AND_RESET): New ifns.
* builtins.h (expand_ifn_atomic_bit_test_and): New prototype.
* builtins.c (expand_ifn_atomic_bit_test_and): New function.
* internal-fn.c (expand_ATOMIC_BIT_TEST_AND_SET,
expand_ATOMIC_BIT_TEST_AND_COMPLEMENT,
expand_ATOMIC_BIT_TEST_AND_RESET): New functions.
* doc/md.texi (atomic_bit_test_and_set@var{mode},
atomic_bit_test_and_complement@var{mode},
atomic_bit_test_and_reset@var{mode}): Document.
* config/i386/sync.md (atomic_bit_test_and_set<mode>,
atomic_bit_test_and_complement<mode>,
atomic_bit_test_and_reset<mode>): New expanders.
(atomic_bit_test_and_set<mode>_1,
atomic_bit_test_and_complement<mode>_1,
atomic_bit_test_and_reset<mode>_1): New insns.
* gcc.target/i386/pr49244-1.c: New test.
* gcc.target/i386/pr49244-2.c: New test.
From-SVN: r235813
|
|
m68k-linux-gnu)
PR target/69885
* doc/md.texi (ashl@var{m}3): Document that mode of operand 2 must
be specified.
From-SVN: r233613
|
|
* cgraph.c: Spelling fixes - behaviour -> behavior and
neighbour -> neighbor.
* target.def: Likewise.
* sel-sched.c: Likewise.
* config/mips/mips.c: Likewise.
* config/arc/arc.md: Likewise.
* config/arm/cortex-a57.md: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/neon.md: Likewise.
* config/arm/arm-c.c: Likewise.
* config/vms/vms-c.c: Likewise.
* config/s390/s390.c: Likewise.
* config/i386/znver1.md: Likewise.
* config/i386/i386.c: Likewise.
* config/ia64/hpux-unix2003.h: Likewise.
* config/msp430/msp430.md: Likewise.
* config/rx/rx.c: Likewise.
* config/rx/rx.md: Likewise.
* config/aarch64/aarch64-simd.md: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/cris/cris.opt: Likewise.
* config/rs6000/rs6000.c: Likewise.
* target.h: Likewise.
* spellcheck.c: Likewise.
* ira-build.c: Likewise.
* tree-inline.c: Likewise.
* builtins.c: Likewise.
* lra-constraints.c: Likewise.
* explow.c: Likewise.
* hwint.h: Likewise.
* targhooks.c: Likewise.
* tree-vect-data-refs.c: Likewise.
* expr.c: Likewise.
* doc/tm.texi: Likewise.
* doc/extend.texi: Likewise.
* doc/install.texi: Likewise.
* doc/md.texi: Likewise.
* tree-ssa-tail-merge.c: Likewise.
* sched-int.h: Likewise.
* match.pd: Likewise.
* sched-ebb.c: Likewise.
* target.def (omit_struct_return_reg): Likewise.
* gimple-ssa-isolate-paths.c: Likewise.
(find_implicit_erroneous_behaviour): Renamed to...
(find_implicit_erroneous_behavior): ... this.
(find_explicit_erroneous_behaviour): Renamed to...
(find_explicit_erroneous_behavior): ... this.
(gimple_ssa_isolate_erroneous_paths): Adjust caller.
gcc/cp/
* error.c: Spelling fixes - behaviour -> behavior and
neighbour -> neighbor.
* decl.c: Likewise.
* typeck.c (cp_build_binary_op): Fix up behavior spelling in
diagnostics.
* init.c (build_delete): Likewise.
gcc/objc/
* objc-act.c: Spelling fixes - behaviour -> behavior and
neighbour -> neighbor.
* objc-map.h: Likewise.
gcc/go/
* gofrontend/lex.cc: Spelling fixes - behaviour -> behavior and
neighbour -> neighbor.
* gccgo.texi: Likewise.
gcc/ada/
* prj-tree.ads: Spelling fixes - behaviour -> behavior and
neighbour -> neighbor.
* prep.adb: Likewise.
* prj.ads: Likewise.
* prepcomp.adb: Likewise.
* g-socket.ads: Likewise.
* s-imgrea.adb: Likewise.
* a-calend.adb: Likewise.
* exp_disp.adb: Likewise.
* doc/gnat_ugn/gnat_utility_programs.rst: Likewise.
* g-socket.adb: Likewise.
* sem_ch12.adb: Likewise.
* terminals.c: Likewise.
gcc/testsuite/
* objc.dg/gnu-api-2-method.m: Spelling fixes - behaviour -> behavior
and neighbour -> neighbor.
* objc.dg/attributes/method-nonnull-1.m: Likewise.
* objc.dg/gnu-api-2-class-meta.m: Likewise.
* c-c++-common/Wvarargs.c: Likewise.
* c-c++-common/goacc/host_data-5.c: Likewise.
* obj-c++.dg/gnu-api-2-class-meta.mm: Likewise.
* obj-c++.dg/attributes/method-nonnull-1.mm: Likewise.
* obj-c++.dg/gnu-api-2-method.mm: Likewise.
* gcc.target/aarch64/pr60697.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vqshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vqrshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vldX.c: Likewise.
* gcc.target/aarch64/aapcs64/ice_2.c: Likewise.
* gcc.target/aarch64/aapcs64/test_23.c: Likewise.
* gcc.target/aarch64/vrnd_f64_1.c: Likewise.
* g++.dg/warn/Wconversion-real-integer-3.C: Likewise.
* g++.dg/lookup/koenig5.C: Likewise.
* g++.dg/ext/no-asm-2.C: Likewise.
* gfortran.dg/bounds_check_array_ctor_3.f90: Likewise.
* gfortran.dg/bounds_check_array_ctor_7.f90: Likewise.
* gfortran.dg/used_types_16.f90: Likewise.
* gfortran.dg/assumed_rank_bounds_1.f90: Likewise.
* gfortran.dg/bounds_check_array_ctor_1.f90: Likewise.
* gfortran.dg/assumed_rank_bounds_2.f90: Likewise.
* gfortran.dg/bounds_check_array_ctor_4.f90: Likewise.
* gfortran.dg/abstract_type_6.f03: Likewise.
* gfortran.dg/bounds_check_array_ctor_5.f90: Likewise.
* gfortran.dg/used_types_15.f90: Likewise.
* gfortran.dg/bounds_check_array_ctor_8.f90: Likewise.
* gfortran.dg/exit_3.f08: Likewise.
* gfortran.dg/open_status_2.f90: Likewise.
* gfortran.dg/derived_pointer_recursion_2.f90: Likewise.
* gfortran.dg/intrinsic_std_1.f90: Likewise.
* gfortran.dg/associate_1.f03: Likewise.
* gfortran.dg/bounds_check_array_ctor_2.f90: Likewise.
* gfortran.dg/intrinsic_std_6.f90: Likewise.
* gfortran.dg/bounds_check_array_ctor_6.f90: Likewise.
* gcc.dg/builtin-object-size-1.c: Likewise.
* gcc.dg/noreturn-6.c: Likewise.
* gcc.dg/builtin-stringop-chk-1.c: Likewise.
* gcc.dg/globalalias.c: Likewise.
* gcc.dg/builtins-config.h: Likewise.
* gcc.dg/pr30457.c: Likewise.
* gcc.c-torture/compile/volatile-1.c: Likewise.
* gcc.c-torture/execute/20101011-1.c: Likewise.
* c-c++-common/Waddress-1.c: Likewise.
From-SVN: r233358
|
|
2016-01-29 Vladimir Makarov <vmakarov@redhat.com>
PR target/69299
* config/i386/constraints.md (Bm): Describe as special memory
constraint.
* doc/md.texi (DEFINE_SPECIAL_MEMORY_CONSTRAINT): Describe it.
* genoutput.c (main): Process DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* genpreds.c (struct constraint_data): Add is_special_memory.
(have_special_memory_constraints, special_memory_start): New
static vars.
(special_memory_end): Ditto.
(add_constraint): Add new arg is_special_memory. Add code to
process its true value. Update have_special_memory_constraints.
(process_define_constraint): Pass the new arg.
(process_define_register_constraint): Ditto.
(choose_enum_order): Process special memory.
(write_tm_preds_h): Generate enum const CT_SPECIAL_MEMORY and
function insn_extra_special_memory_constraint.
(main): Process DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* gensupport.c (process_rtx): Process
DEFINE_SPECIAL_MEMORY_CONSTRAINT.
* ira-costs.c (record_reg_classes): Process CT_SPECIAL_MEMORY.
* ira-lives.c (single_reg_class): Use
insn_extra_special_memory_constraint.
* ira.c (ira_setup_alts): Process CT_SPECIAL_MEMORY.
* lra-constraints.c (process_alt_operands): Ditto.
(curr_insn_transform): Use insn_extra_special_memory_constraint.
* recog.c (asm_operand_ok, preprocess_constraints): Process
CT_SPECIAL_MEMORY.
* reload.c (find_reloads): Ditto.
* rtl.def (DEFINE_SPECIFAL_MEMORY_CONSTRAINT): New.
* stmt.c (parse_input_constraint): Use
insn_extra_special_memory_constraint.
From-SVN: r232993
|
|
PR target/69459
* config/i386/constraints.md (C): Only accept constant zero operand.
(BC): New constraint.
* config/i386/sse.md (*mov<mode>_internal): Use BC constraint
instead of C constraint.
* doc/md.texi (Machine Constraints): Update description
of C constraint.
testsuite/ChangeLog:
PR target/69459
* gcc.target/i386/pr69459.c: New test.
From-SVN: r232955
|
|
* doc/md.texi (reduc_smin_@var{m}, reduc_smax_@var{m},
reduc_umin_@var{m}, reduc_umax_@var{m}, reduc_splus_@var{m},
reduc_uplus_@var{m}): Remove.
* expr.c (expand_expr_real_2): Remove expansion path for
reduc_[us](min|max|plus) optabs.
* optabs-tree.c (scalar_reduc_to_vector): Remove.
* optabs-tree.h (scalar_reduc_to_vector): Remove.
* optabs.def (reduc_smax_optab, reduc_smin_optab, reduc_splus_optab,
reduc_umax_optab, reduc_umin_optab, reduc_uplus_optab): Remove.
* tree-vect-loop.c (vectorizable_reduction): Remove test for
reduc_[us](min|max|plus) optabs.
From-SVN: r232373
|
|
[gcc]
2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wo constraint): New constraint for
ISA 3.0 (power9).
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support
for wo constraint.
(rs6000_init_hard_regno_mode_ok): Likewise.
* config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for
wo constraint.
* config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm
expanders not to have constraints. Add support for ISA 3.0 xxperm
instruction. Add support for fusing xxlor with xxperm.
(altivec_vperm_<mode>_internal): Likewise.
(altivec_vperm_v8hiv16qi): Likewise.
(altivec_vperm_<mode>v16q): Likewise.
(altivec_vperm_<mode>_uns): Likewise.
(vperm_v8hiv4si): Likewise.
(vperm_v16qiv8hi): Likewise.
* doc/md.texi (RS/6000 constraints): Document wo constraint.
[gcc/testsuite]
2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-permute.c: New test for xxperm code
generation.
From-SVN: r232060
|
|
From-SVN: r232055
|
|
As Bernd requested, this patch adds "This pattern cannot FAIL" to the
documentation of optabs that came to be mapped to interal functions.
For consistency I did the same for optabs that were already being
used for internal functions.
Many of the optabs weren't documented in the first place, so I added
entries for the missing ones. Also, there were some inaccuracies in
the documentation of the rounding optabs. The bitcount optabs said
that operand 0 has mode @var{m} and that operand 1 is under target
control, whereas it should be the other way around.
Tested on x86_64-linux-gnu.
gcc/
* doc/md.texi (vec_load_lanes@var{m}@var{n}): Document that
the pattern cannot FAIL.
(vec_store_lanes@var{m}@var{n}): Likewise.
(maskload@var{m}@var{n}): Likewise.
(maskstore@var{m}@var{n}): Likewise. Fix a cut-&-paste error
in the name of the pattern.
(rsqrt@var{m}2): Document that mode m must be a scalar or vector
floating-point mode and that all operands have that mode.
(fmin@var{m}3, fmax@var{m}3): Likewise. Document that the
pattern cannot FAIL.
(sqrt@var{m}2): Document that mode m must be a scalar or vector
floating-point mode, that all operands have that mode, and that
the patterns cannot FAIL. Remove previous documentation referring
to @code{double} and @code{float}.
(fmod@var{m}3, remainder@var{m}3, cos@var{m}2, sin@var{m}2)
(sincos@var{m}3, log@var{m}2, pow@var{m}3, atan2@var{m}3)
(copysign@var{m}3): Likewise.
(exp@var{m}2): Likewise. Explicitly state the base.
(floor@var{m}2): As for sqrt@var{m}2, but also specify the operands.
(btrunc@var{m}2, rint@var{m}2): Likewise.
(round@var{m}2): Likewise. Fix incorrect description of rounding
effect.
(ceil@var{m}2): As for round@var{m}2.
(nearbyint@var{m}2): As for floor@var{m}2, but also mention that
the instruction must not raise an inexact condition.
(scalb@var{m}3): Document previously-undocumented pattern
(ldexp@var{m}3, tan@var{m}2, asin@var{m}2, acos@var{m}2)
(atan@var{m}2, expm1@var{m}2, exp10@var{m}2, exp2@var{m}2)
(log1p@var{m}2, log10@var{m}2, log2@var{m}2, logb@var{m}2)
(significand@var{m}2): Likewise.
(ffs@var{m}2): Fix the description of the modes, so that operand 1 has
mode m and operand 0 is defined more freely. Document that @var{m}
can be a scalar or vector integer mode and that the pattern is not
allowed to FAIL.
(clz@var{m}2, ctz@var{m}2, popcount@var{m}2, parity@var{m}2): Likewise.
(clrsb@var{m}2): Likewise, except that the description of the
mode was missing in this case.
From-SVN: r231230
|
|
All current uses of builtin_reciprocal convert 1.0/sqrt into rsqrt.
This patch adds an rsqrt optab and associated internal function for
that instead. We can then pick up the vector forms of rsqrt automatically,
fixing an AArch64 regression from my internal_fn patches.
With that change, builtin_reciprocal only needs to handle target-specific
built-in functions. I've restricted the hook to those since, if we need
a reciprocal of another standard function later, I think there should be
a strong preference for adding a new optab and internal function for it,
rather than hiding the code in a backend.
Three targets implement builtin_reciprocal: aarch64, i386 and rs6000.
i386 and rs6000 already used the obvious rsqrt<mode>2 pattern names
for the instructions, so they pick up the new code automatically.
aarch64 needs a slight rename.
mn10300 is unusual in that its native operation is rsqrt, and
sqrt is approximated as 1.0/rsqrt. The port also uses rsqrt<mode>2
for the rsqrt pattern, so after the patch we now pick it up as a native
operation.
Two other ports define rsqrt patterns: sh and v850. AFAICT these
patterns aren't currently used, but I think the patch does what the
authors of the patterns would have expected. There's obviously some
risk of fallout though.
Tested on x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabihf
(as a target without the hooks) and powerpc64-linux-gnu.
gcc/
* internal-fn.def (RSQRT): New function.
* optabs.def (rsqrt_optab): New optab.
* doc/md.texi (rsqrtM2): Document.
* target.def (builtin_reciprocal): Replace gcall argument with
a function decl. Restrict hook to machine functions.
* doc/tm.texi: Regenerate.
* targhooks.h (default_builtin_reciprocal): Update prototype.
* targhooks.c (default_builtin_reciprocal): Likewise.
* tree-ssa-math-opts.c: Include internal-fn.h.
(internal_fn_reciprocal): New function.
(pass_cse_reciprocals::execute): Call it, and build a call to an
internal function on success. Only call targetm.builtin_reciprocal
for machine functions.
* config/aarch64/aarch64-protos.h (aarch64_builtin_rsqrt): Remove
second argument.
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin_rsqrt):
Rename aarch64_rsqrt_<mode>2 to rsqrt<mode>2.
(aarch64_builtin_rsqrt): Remove md_fn argument and only handle
machine functions.
* config/aarch64/aarch64.c (use_rsqrt_p): New function.
(aarch64_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_size check.
Only handle machine functions. Update call to aarch64_builtin_rsqrt.
(aarch64_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
* config/aarch64/aarch64-simd.md (aarch64_rsqrt_<mode>2): Rename to...
(rsqrt<mode>2): ...this.
* config/i386/i386.c (use_rsqrt_p): New function.
(ix86_builtin_reciprocal): Replace gcall argument with a
function decl. Use use_rsqrt_p. Remove optimize_insn_for_size_p
check. Only handle machine functions.
(ix86_optab_supported_p): Handle rsqrt_optab.
* config/rs6000/rs6000.c (TARGET_OPTAB_SUPPORTED_P): Define.
(rs6000_builtin_reciprocal): Replace gcall argument with a
function decl. Remove optimize_insn_for_size_p check.
Only handle machine functions.
(rs6000_optab_supported_p): New function.
From-SVN: r231229
|
|
[gcc]
2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com>
<patch #10>
* config/rs6000/constraints.md (wb constraint): New constraint for
ISA 3.0 d-form scalar addressing.
* config/rs6000/rs6000.c (mode_supports_vmx_dform): Add support
for ISA 3.0 D-form addressing to load SFmode/DFmode scalars into
Altivec registers. Add wb constraint for Altivec registers with
D-form addressing. If we have ISA 3.0 d-form support, undo
secondary reload support for using FPR registers if we want to do
D-form addressing.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wb
constraint.
* config/rs6000/rs6000.md (f32_lr2 mode attribute): Add support
for ISA 3.0 SFmode/DFmode d-form addressing to Altivec registers.
(f32_lm2): Likewise.
(f32_li2): Likewise.
(f32_sr2): Likewise.
(f32_sm2): Likewise.
(f32_si2): Likewise.
(f64_p9): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
* doc/md.texi (RS/6000 constraints): Document wb constraint.
Fixup we constraint documentation.
[gcc/testsuite]
2015-11-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-1.c: New test.
* gcc.target/powerpc/dform-2.c: Likewise.
From-SVN: r230913
|
|
2015-11-25 David Sherwood <david.sherwood@arm.com>
* optabs.def: Add new optabs fmax_optab/fmin_optab.
* internal-fn.def: Add new fmax/fmin internal functions.
* doc/md.texi: Add fmin and fmax patterns.
From-SVN: r230888
|
|
PR target/67089
* optabs.def (uaddv4_optab, usubv4_optab): New.
* internal-fn.c (expand_addsub_overflow): Use uaddv4_optab
and usubv4_optab in the u +- u -> u case.
* doc/md.texi (Standard Names): Document addv{m}4, subv{m}4,
mulv{m}4, uaddv{m}4, usubv{m}4, umulv{m}4.
* config/i386/i386.md (uaddv<SWI>4, usubv<SWI>4): New.
From-SVN: r230767
|
|
* doc/md.texi (Standard Names): Move entry for addptr3 around,
add entries for addv4, subv4, mulv4, umulv4 and negv3, fixes
glitch in entries for cbranch4 and jump.
From-SVN: r230651
|
|
* doc/md.texi ('#' and '*' constraint modifiers): Do not include these
in the user documentation.
(define_peephole2, define_split): Similarly.
From-SVN: r230439
|
|
[gcc]
2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (we constraint): New constraint for
64-bit power9 vector support.
(wL constraint): New constraint for the element in a vector that
can be addressed by the MFVSRLD instruction.
* config/rs6000/rs6000-protos.h (convert_float128_to_int): Add
declaration.
(convert_int_to_float128): Likewise.
(rs6000_generate_compare): Add support for ISA 3.0 (power9)
hardware support for IEEE 128-bit floating point.
(rs6000_expand_float128_convert): Likewise.
(convert_float128_to_int): Likewise.
(convert_int_to_float128): Likewise.
* config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for
ISA 3.0 hardware IEEE 128-bit floating point.
(UNSPEC_IEEE128_MOVE): Likewise.
(UNSPEC_IEEE128_CONVERT): Likewise.
(FMA_F): Add support for IEEE 128-bit floating point hardware
support.
(Ff): Add support for DImode.
(Fv): Likewise.
(any_fix code iterator): New and updated iterators for IEEE
128-bit floating point hardware support.
(any_float code iterator): Likewise.
(s code attribute): Likewise.
(su code attribute): Likewise.
(az code attribute): Likewise.
(uns code attribute): Likewise.
(neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit
floating point hardware support.
(abs<mode>2, FLOAT128 iterator): Likewise.
(add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit
floating point hardware.
(sub<mode>3, IEEE128 iterator): Likewise.
(mul<mode>3, IEEE128 iterator): Likewise.
(div<mode>3, IEEE128 iterator): Likewise.
(copysign<mode>3, IEEE128 iterator): Likewise.
(sqrt<mode>2, IEEE128 iterator): Likewise.
(neg<mode>2, IEEE128 iterator): Likewise.
(abs<mode>2, IEEE128 iterator): Likewise.
(nabs<mode>2, IEEE128 iterator): Likewise.
(fma<mode>4_hw, IEEE128 iterator): Likewise.
(fms<mode>4_hw, IEEE128 iterator): Likewise.
(nfma<mode>4_hw, IEEE128 iterator): Likewise.
(nfms<mode>4_hw, IEEE128 iterator): Likewise.
(extend<SFDF:mode><IEEE128:mode>2_hw): Likewise.
(trunc<mode>df2_hw, IEEE128 iterator): Likewise.
(trunc<mode>sf2_hw, IEEE128 iterator): Likewise.
(fix_fixuns code attribute): Likewise.
(float_floatuns code attribute): Likewise.
(fix<uns>_<mode>si2_hw): Likewise.
(fix<uns>_<mode>di2_hw): Likewise.
(float<uns>_<mode>si2_hw): Likewise.
(float<uns>_<mode>di2_hw): Likewise.
(xscvqp<su>wz_<mode>): Likewise.
(xscvqp<su>dz_<mode>): Likewise.
(xscv<su>dqp_<mode): Likewise.
(ieee128_mfvsrd): Likewise.
(ieee128_mfvsrwz): Likewise.
(ieee128_mtvsrw): Likewise.
(ieee128_mtvsrd): Likewise.
(trunc<mode>df2_odd): Likewise.
(cmp<mode>_h): Likewise.
(128-bit GPR splitters): Don't split a 128-bit move that is a
direct move between GPR and vector registers using ISA 3.0 direct
move instructions.
(<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer
multiply-add instruction.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0
debugging.
(rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we
constraint. Disable the VSX<->GPR direct move helpers if we have
the MFVSRLD and MTVSRDD instructions.
(rs6000_secondary_reload_simple_move): Add support for doing
vector direct moves directly without additional scratch registers
if we have ISA 3.0 instructions.
(rs6000_secondary_reload_direct_move): Update comments.
(rs6000_output_move_128bit): Add support for ISA 3.0 vector
instructions.
* config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0
direct move instructions.
(vsx_movti_64bit): Likewise.
(vsx_extract_<mode>): Likewise.
* config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New
macros for ISA 3.0 direct move instructions.
(TARGET_DIRECT_MOVE_128): Likewise.
(TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add
instruction.
* doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL
constraints. Update wa documentation to say not to use %x<n> on
instructions that only take Altivec registers.
[gcc/testsuite]
2015-11-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit
hardware floating point support.
* gcc.target/powerpc/direct-move-vector.c: New test for 128-bit
vector direct move instructions.
* gcc.target/powerpc/maddld.c: New test.
From-SVN: r230342
|
|
gcc/
* doc/md.texi (vec_cmp@var{m}@var{n}): New item.
(vec_cmpu@var{m}@var{n}): New item.
(vcond@var{m}@var{n}): Specify comparison is signed.
(vcondu@var{m}@var{n}): New item.
(vcond_mask_@var{m}@var{n}): New item.
(maskload@var{m}@var{n}): New item.
(maskstore@var{m}@var{n}): New item.
From-SVN: r230290
|
|
* ifcvt.c (noce_try_inverse_constants): New function.
(noce_process_if_block): Call it.
* optabs.h (emit_conditional_neg_or_complement): Declare prototype.
* optabs.def (negcc_optab, notcc_optab): Declare.
* optabs.c (emit_conditional_neg_or_complement): New function.
* doc/tm.texi (Standard Names): Document negcc, notcc names.
From-SVN: r230089
|
|
* doc/md.texi (multi-alternative constraints): Don't document
alternatives inherently tied to reload for the user documentation.
From-SVN: r229897
|
|
From-SVN: r227333
|
|
2015-08-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_L): Add KFmode and TFmode.
(VEC_M): Likewise.
(VEC_N): Likewise.
(mov<mode>, VEC_M iterator): Add support for IEEE 128-bit floating
point in VSX registers.
* config/rs6000/constraints.md (wb constraint): Document unused
w<x> constraint.
(we constraint): Likewise.
(wo constraint): Likewise.
(wp constraint): New constraint for IEEE 128-bit floating point in
VSX registers.
(wq constraint): Likewise.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
IEEE 128-bit floating point in VSX registers.
(easy_scalar_constant): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add new
constraints (wp, wq) for IEEE 128-bit floating point in VSX
registers.
(rs6000_init_hard_regno_mode_ok): Likewise.
* config/rs6000/vsx.md (VSX_LE_128): Add support for IEEE 128-bit
floating point in VSX registers.
(VSX_L): Likewise.
(VSX_M): Likewise.
(VSX_M2): Likewise.
(VSm): Likewise.
(VSs): Likewise.
(VSr): Likewise.
(VSa): Likewise.
(VSv): Likewise.
(vsx_le_permute_<mode>): Add support to properly swap bytes for
IEEE 128-bit floating point in VSX registers on little endian.
(vsx_le_undo_permute_<mode>): Likewise.
(vsx_le_perm_load_<mode>): Likewise.
(vsx_le_perm_store_<mode>): Likewise.
(splitters for IEEE 128-bit fp moves): Likewise.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wp and
wq constraints.
* config/rs6000/altivec.md (VM): Add support for IEEE 128-bit
floating point in VSX registers.
(VM2): Likewise.
* doc/md.text (Machine Constraints): Document wp and wq
constraints on PowerPC.
From-SVN: r226520
|
|
PR target/66217
* config/rs6000/constraints.md ("S", "T", "t"): Delete. Update
"available letters" comment.
* config/rs6000/predicates.md (mask_operand, mask_operand_wrap,
mask64_operand, mask64_2_operand, any_mask_operand, and64_2_operand,
and_2rld_operand): Delete.
(and_operand): Adjust.
(rotate_mask_operator): New.
* config/rs6000/rs6000-protos.h (build_mask64_2_operands,
includes_lshift_p, includes_rshift_p, includes_rldic_lshift_p,
includes_rldicr_lshift_p, insvdi_rshift_rlwimi_p, extract_MB,
extract_ME): Delete.
(rs6000_is_valid_mask, rs6000_is_valid_and_mask,
rs6000_is_valid_shift_mask, rs6000_is_valid_insert_mask,
rs6000_insn_for_and_mask, rs6000_insn_for_shift_mask,
rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and,
rs6000_emit_2insn_and): New.
* config/rs6000/rs6000.c (num_insns_constant): Adjust.
(build_mask64_2_operands, includes_lshift_p, includes_rshift_p,
includes_rldic_lshift_p, includes_rldicr_lshift_p,
insvdi_rshift_rlwimi_p, extract_MB, extract_ME): Delete.
(rs6000_is_valid_mask, rs6000_is_valid_and_mask,
rs6000_insn_for_and_mask, rs6000_is_valid_shift_mask,
s6000_insn_for_shift_mask, rs6000_is_valid_insert_mask,
rs6000_insn_for_insert_mask, rs6000_is_valid_2insn_and,
rs6000_emit_2insn_and): New.
(print_operand) <'b', 'B', 'm', 'M', 's', 'S', 'W'>: Delete.
(rs6000_rtx_costs) <CONST_INT>: Delete mask_operand and mask64_operand
handling.
<NOT>: Don't fall through to next case.
<AND>: Handle the various rotate-and-mask cases directly.
<IOR>: Always cost as one insn.
* config/rs6000/rs6000.md (splitter for bswap:SI): Adjust.
(and<mode>3): Adjust expander for the new patterns.
(and<mode>3_imm, and<mode>3_imm_dot, and<mode>3_imm_dot2,
and<mode>3_imm_mask_dot, and<mode>3_imm_mask_dot2): Adjust condition.
(*and<mode>3_imm_dot_shifted): New.
(*and<mode>3_mask): Delete, rewrite as ...
(and<mode>3_mask): ... New.
(*and<mode>3_mask_dot, *and<mode>3_mask_dot): Rewrite.
(andsi3_internal0_nomc): Delete.
(*andsi3_internal6): Delete.
(*and<mode>3_2insn): New.
(insv, insvsi_internal, *insvsi_internal1, *insvsi_internal2,
*insvsi_internal3, *insvsi_internal4, *insvsi_internal5,
*insvsi_internal6, insvdi_internal, *insvdi_internal2,
*insvdi_internal3): Delete.
(*rotl<mode>3_mask, *rotl<mode>3_mask_dot, *rotl<mode>3_mask_dot2,
*rotl<mode>3_insert, *rotl<mode>3_insert_2, *rotl<mode>3_insert_3,
*rotl<mode>3_insert_4, two splitters for multi-precision shifts,
*ior<mode>_mask): New.
(extzv, extzvdi_internal, *extzvdi_internal1, *extzvdi_internal2,
*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2,
*ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2,
*lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2):
Delete.
(ashr<mode>3): Delete expander.
(*ashr<mode>3): Rename to ...
(ashr<mode>3): ... This.
(ashrdi3_no_power, *ashrdisi3_noppc64be): Delete.
(*rotldi3_internal4, *rotldi3_internal5 and split,
*rotldi3_internal6 and split, *ashldi3_internal4, ashldi3_internal5
and split, *ashldi3_internal6 and split, *ashldi3_internal7,
ashldi3_internal8 and split, *ashldi3_internal9 and split): Delete.
(*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): Delete.
(splitter for loading a mask): Adjust.
* doc/md.texi (Machine Constraints): Remove q, S, T, t constraints.
From-SVN: r226005
|
|
2015-07-14 Sandra Loosemore <sandra@codesourcery.com>
Cesar Philippidis <cesar@codesourcery.com>
Chung-Lin Tang <cltang@codesourcery.com>
gcc/
* config/nios2/constraints.md (U, v): New constraints.
* config/nios2/predicates.md (rdprs_dcache_operand): New.
(ldstex_memory_operand): New.
* config/nios2/sync.md: New file.
* config/nios2/nios2.md (unspecv): Add new builtin function
UNSPECV codes.
(rdprs, flushd, flushda, wrpie, eni): New patterns.
(top-level): Include sync.md.
* config/nios2/nios2.c (N2_FTYPES): Add function types for
new builtins.
(N2_BUILTINS): Add arch field setting, add new builtins.
(enum nios2_builtin_code,nios2_builtins): Update N2_BUILTIN_DEF
for arch field.
(nios2_expand_ldst_builtin): Rename from nios2_expand_ldstio_builtin.
Also handle ldex/stex/ldsex/stsex builtins.
(nios2_expand_rdprs_builtin): New function.
(nios2_expand_cache_builtin): New function.
(nios2_expand_wrpie_builtin): New function.
(nios2_expand_eni_builtin): New function.
(nios2_expand_builtin): Add arch field handling and new builtin
cases.
* doc/extend.texi (Altera Nios II Built-in Functions): Document
new builtins.
* doc/md.texi (Machine Constraints): Document U and v constraints.
gcc/testsuite/
* gcc.target/nios2/nios2-flushd.c: New.
* gcc.target/nios2/nios2-rdprs.c: New.
* gcc.target/nios2/r2-atomic.c: New.
* gcc.target/nios2/r2-eni.c: New.
* gcc.target/nios2/r2-wrpie.c: New.
Co-Authored-By: Cesar Philippidis <cesar@codesourcery.com>
Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com>
From-SVN: r225800
|
|
2015-07-14 Sandra Loosemore <sandra@codesourcery.com>
Cesar Philippidis <cesar@codesourcery.com>
Chung-Lin Tang <cltang@codesourcery.com>
gcc/
* config/nios2/nios2.h (LABEL_ALIGN): Define.
(REG_ALLOC_ORDER): Define.
(ADJUST_REG_ALLOC_ORDER): Define.
(HONOR_REG_ALLOC_ORDER): Define.
(CDX_REG_P): Define.
(ANDCLEAR_INT): Define.
* config/nios2/nios2-protos.h (nios2_add_insn_asm): Declare.
(nios2_label_align): Declare.
(nios2_cdx_narrow_form_p): Declare.
(nios2_adjust_reg_alloc_order): Declare.
* config/nios2/nios2.c (nios2_rtx_costs): Adjust for BMX zero-extract
operation.
(nios2_large_unspec_reloc_p): New function, split from...
(nios2_legitimate_pic_operand_p): ...here.
(nios2_emit_move_sequence): Add *high/*lo_sum constant expand code.
(nios2_print_operand_punct_valid_p): New.
(nios2_print_operand): Add %., %!, %x, %y, %A. Remove %U.
(split_mem_address): New.
(split_alu_insn): New.
(cdxreg): New.
(cdx_add_immed, cdx_and_immed, cdx_mov_immed, cdx_shift_immed): New.
(enum nios2_add_insn_kind): New.
(nios2_add_insn_names, nios2_add_insn_narrow): New.
(nios2_add_insn_classify): New.
(nios2_add_insn_asm): New.
(nios2_cdx_narrow_form_p): New.
(label_align, min_labelno, max_labelno): New.
(nios2_reorg): New.
(nios2_label_align): New.
(nios2_adjust_reg_alloc_order): New.
(TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define.
(TARGET_MACHINE_DEPENDENT_REORG): Define.
* config/nios2/constraints.md (P): New constraint.
* config/nios2/predicates.md (const_and_operand): New.
(and_operand): New.
(stack_memory_operand): New.
* config/nios2/nios2.md (SP_REGNO): Define stack pointer regno.
(length): Update to use nios2_cdx_narrow_form_p().
(type): Add new insn type values.
(control, alu, st, ld, shift): Update insn reservations with
new insn type values.
(*high, *lo_sum): Define new insn patterns for constant generation.
(movqi_internal, movhi_internal, movsi_internal): Reduce
alternatives, update asm template to handle CDX variants, update
type attributes.
(zero_extendhisi2, zero_extendqi<mode>2): Add CDX variants to asm
template, update type attributes.
(extendhisi2, extendqi<mode>2): Likewise.
(addsi3): Change to use function for asm string.
(subsi3): Add CDX notation to asm template, update type attributes.
(negsi3, one_cmplsi3): Likewise.
(andsi3): New pattern, specialized from logical patterns.
(<code>si3): Remove and case, combine alternatives, update asm
template.
(<shift_op>si3): Add CDX notation, update type attributes.
(rotrsi3): Update type attribute.
(*merge, extzv, insv): New insn patterns.
(return): Change to define_expand.
(simple_return): Add CDX notation, update type attributes.
(indirect_jump): Add CDX notation.
(jump): Update asm cases, update length attribute expression.
(*call, *call_value, *sibcall, *sibcall_value): Add CDX variant.
(nios2_cbranch): Update asm cases and length attribute expression
to handle CDX variants.
(nios2_cmp<code>): Update asm template.
(nop): Add CDX notation, update type attributes.
(trap): Add CDX notation.
(ctrapsi4): Update asm cases and length attribute expression to
handle CDX variant.
* doc/md.texi (Machine Constraints): Document P constraint.
gcc/testsuite/
* gcc.target/nios2/andci.c: New.
* gcc.target/nios2/bmx.c: New.
* gcc.target/nios2/cdx-add.c: New.
* gcc.target/nios2/cdx-branch.c: New.
* gcc.target/nios2/cdx-callret.c: New.
* gcc.target/nios2/cdx-loadstore.c: New.
* gcc.target/nios2/cdx-logical.c: New.
* gcc.target/nios2/cdx-mov.c: New.
* gcc.target/nios2/cdx-shift.c: New.
* gcc.target/nios2/cdx-sub.c: New.
* gcc.target/nios2/nios2-trap-insn.c: Adjust pattern.
Co-Authored-By: Cesar Philippidis <cesar@codesourcery.com>
Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com>
From-SVN: r225796
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2015-07-14 Sandra Loosemore <sandra@codesourcery.com>
Cesar Philippidis <cesar@codesourcery.com>
Chung-Lin Tang <cltang@codesourcery.com>
gcc/
* config/nios2/nios2.h (SMALL_INT12): New macro.
* config/nios2/nios2.c (nios2_valid_addr_offset_p): New function.
(nios2_valid_addr_expr_p): Use it.
(nios2_symbol_ref_in_small_data_p): Disallow GP-relative addressing
with implicit "io" instructions on R2.
* config/nios2/constraints.md (w): New constraint.
* config/nios2/predicates.md (ldstio_memory_operand): New.
* config/nios2/nios2.md (ld<bhw_uns>io, ld<bh>io): Update memory
operand predicate and constraint.
(ld<bh>io_signed, st<bhw>io>): Likewise.
* doc/md.texi (Machine Constraints): Document w constraint.
gcc/testsuite/
* gcc.target/nios2/r2-io-range.c: New.
* gcc.target/nios2/r2-stio-1.c: New.
* gcc.target/nios2/r2-stio-2.c: New.
* gcc.target/nios2/nios2-ldxio.c: New.
* gcc.target/nios2/nios2-stxio.c: Change to assemble test instead
of just compile. Add more tests.
Co-Authored-By: Cesar Philippidis <cesar@codesourcery.com>
Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com>
From-SVN: r225792
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2015-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/66474
* doc/md.texi (Machine Constraints): Document that on the PowerPC
if you use a constraint that targets a VSX register, you must use
%x<n> in the template.
From-SVN: r224332
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