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author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-02-06 21:38:37 +0000 |
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committer | Palmer Dabbelt <palmer@gcc.gnu.org> | 2017-02-06 21:38:37 +0000 |
commit | 09cae7507d9e88f2b05cf3a9404bf181e65ccbac (patch) | |
tree | 4068c1ab645786d53f4bb817e680cf0963f2f03d /gcc/doc/md.texi | |
parent | 44a6da7bac79f288af814cd401a666c81fb8735c (diff) | |
download | gcc-09cae7507d9e88f2b05cf3a9404bf181e65ccbac.zip gcc-09cae7507d9e88f2b05cf3a9404bf181e65ccbac.tar.gz gcc-09cae7507d9e88f2b05cf3a9404bf181e65ccbac.tar.bz2 |
RISC-V Port: gcc
gcc/ChangeLog:
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.c: New file.
* gcc/common/config/riscv/riscv-common.c: Likewise.
* config.gcc: Likewise.
* config/riscv/constraints.md: Likewise.
* config/riscv/elf.h: Likewise.
* config/riscv/generic.md: Likewise.
* config/riscv/linux.h: Likewise.
* config/riscv/multilib-generator: Likewise.
* config/riscv/peephole.md: Likewise.
* config/riscv/pic.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.c: Likewise.
* config/riscv/riscv-c.c: Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-modes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/sync.md: Likewise.
* config/riscv/t-elf-multilib: Likewise.
* config/riscv/t-linux: Likewise.
* config/riscv/t-linux-multilib: Likewise.
* config/riscv/t-riscv: Likewise.
* configure.ac: Likewise.
* doc/contrib.texi: Add Kito Cheng, Palmer Dabbelt, and Andrew
Waterman as RISC-V maintainers.
* doc/install.texi: Add RISC-V entries.
* doc/invoke.texi: Add RISC-V options section.
* doc/md.texi: Add RISC-V constraints section.
From-SVN: r245224
Diffstat (limited to 'gcc/doc/md.texi')
-rw-r--r-- | gcc/doc/md.texi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 11266d7..3f71074 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3362,6 +3362,26 @@ The @code{X} register. @end table +@item RISC-V---@file{config/riscv/constraints.md} +@table @code + +@item f +A floating-point register (if availiable). + +@item I +An I-type 12-bit signed immediate. + +@item J +Integer zero. + +@item K +A 5-bit unsigned immediate for CSR access instructions. + +@item A +An address that is held in a general-purpose register. + +@end table + @item RX---@file{config/rx/constraints.md} @table @code @item Q |