riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-01	md/define_c_enum: support value assignation	YunQiang Su	1	-0/+4
2021-08-05	doc: Document cond_* shift optabs in md.texi	Richard Sandiford	1	-0/+11
2021-07-30	doc: correct documentation of "call" (et al) operand 2.	Hans-Peter Nilsson	1	-2/+6
2021-07-14	Vect: Add support for dot-product where the sign for the multiplicant changes.	Tamar Christina	1	-6/+46
2021-07-13	docs: Add 'S' to Machine Constraints for RISC-V	Kito Cheng	1	-0/+3
2021-07-09	docs: don't split @smallexample in multiple @groups	Sergei Trofimovich	1	-9/+0
2021-07-09	docs: add missing 'see' word	Sergei Trofimovich	1	-1/+1
2021-07-06	Add FMADDSUB and FMSUBADD SLP vectorization patterns and optabs	Richard Biener	1	-0/+14
2021-06-24	Add x86 addsub SLP pattern	Richard Biener	1	-0/+8
2021-05-25	C-SKY: Add fpuv3 instructions and CK860 arch.	Geng Qi	1	-0/+8
2021-05-04	Remove CC0	Segher Boessenkool	1	-13/+5
2021-03-22	[PR99581] Define relaxed memory and use it for aarch64	Vladimir N. Makarov	1	-1/+27
2021-01-14	slp: support complex FMS and complex FMS conjugate	Tamar Christina	1	-0/+45
2021-01-14	slp: support complex FMA and complex FMA conjugate	Tamar Christina	1	-0/+45
2021-01-14	slp: support complex multiply and complex multiply conjugate	Tamar Christina	1	-0/+44
2021-01-04	Update copyright years.	Jakub Jelinek	1	-1/+1
2020-12-13	middle-end: Support complex Addition	Tamar Christina	1	-0/+48
2020-12-05	RTL: Also support HOST_WIDE_INT with int iterators	Maciej W. Rozycki	1	-5/+5
2020-11-19	[2/3] [vect] Add widening add, subtract patterns	Joel Hutton	1	-0/+22
2020-11-10	doc: Fix grammar in description of earlyclobber	Alex Coplan	1	-1/+1
2020-07-08	IFN/optabs: Support vector load/store with length	Kewen Lin	1	-0/+26
2020-02-10	md.texi (Define Subst): Match closing paren in example.	Hans-Peter Nilsson	1	-1/+1
2020-02-03	rs6000: Update constraint documentation	Segher Boessenkool	1	-98/+94
2020-01-09	re PR inline-asm/93202 ([RISCV] ICE when using inline asm 'h' operand modifier)	Jakub Jelinek	1	-1/+1
2020-01-07	Update 'Q' constraint documentation.	Michael Meissner	1	-2/+1
2020-01-06	mips.c (vr4130_align_insns): Fix typo.	Bryan Stenson	1	-1/+1
2020-01-01	Update copyright years.	Jakub Jelinek	1	-1/+1
2019-11-18	Add optabs for accelerating RAW and WAR alias checks	Richard Sandiford	1	-0/+31
2019-11-08	Generalise gather and scatter optabs	Richard Sandiford	1	-17/+17
2019-11-06	doc: Insn splitting by combine	Segher Boessenkool	1	-1/+1
2019-10-01	doc/md.texi: Fix some typos	Segher Boessenkool	1	-3/+3
2019-09-30	[AArch64][SVE] Utilize ASRD instruction for division and remainder	Yuliang Wang	1	-0/+11
2019-09-12	Vectorise multiply high with scaling operations (PR 89386)	Yuliang Wang	1	-0/+27
2019-09-03	Remove Cell Broadband Engine SPU targets	Ulrich Weigand	1	-70/+0
2019-08-13	[AArch64] Add a "y" constraint for V0-V7	Richard Sandiford	1	-0/+6
2019-07-12	Support multiple operand counts for .md @ patterns	Richard Sandiford	1	-0/+9
2019-07-02	optabs.def (movmem_optab): Add movmem back for memmove().	Aaron Sawdey	1	-0/+36
2019-06-27	builtins.c (get_memory_rtx): Fix comment.	Aaron Sawdey	1	-12/+14
2019-06-19	md.texi: Document vec_shl_<mode> pattern.	Jakub Jelinek	1	-0/+8
2019-06-18	[Vectorizer] Support masking fold left reductions	Alejandro Martinez	1	-0/+5
2019-06-12	Initial TI PRU GCC port	Dimitar Dimitrov	1	-0/+19
2019-06-05	rs6000: Remove wp and wq	Segher Boessenkool	1	-9/+2
2019-06-05	rs6000: ww -> wa	Segher Boessenkool	1	-4/+1
2019-06-04	rs6000: wf -> wa	Segher Boessenkool	1	-4/+1
2019-06-04	rs6000: wd -> wa	Segher Boessenkool	1	-4/+1
2019-06-04	rs6000: ws -> wa	Segher Boessenkool	1	-4/+1
2019-06-04	rs6000: wv -> v+p7v	Segher Boessenkool	1	-4/+1
2019-06-04	rs6000: wi->wa, wt->wa	Segher Boessenkool	1	-10/+2
2019-06-04	rs6000: Delete wg	Segher Boessenkool	1	-4/+1
2019-05-31	New .md construct: define_insn_and_rewrite	Richard Sandiford	1	-0/+113