aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Collapse)AuthorFilesLines
2016-01-14Revert 2016-01-13 change.Michael Meissner4-58/+33
From-SVN: r232392
2016-01-14[MIPS] Migrate reduction optabs in mips-ps-3d.mdAlan Lawrence1-12/+22
* config/mips/mips-ps-3d.md (reduc_splus_v2sf): Remove. (reduc_plus_scal_v2sf): New. (reduc_smax_v2sf): Rename to... (reduc_smax_scal_v2sf): ...here, make result SFmode, add vec_extract. (reduc_smin_v2sf): Rename to... (reduc_smin_scal_v2sf): ...here, make result SFmode, add vec_extract. From-SVN: r232371
2016-01-13rs6000-builtin.def (BU_FLOAT128_2): Add support for pack/unpack functions ↵Michael Meissner4-33/+58
for __ibm128. [gcc] 2016-01-13 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): Add support for pack/unpack functions for __ibm128. (PACK_IF): Likewise. (UNPACK_IF): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add support for __ibm128 pack/unpack functions. (rs6000_invalid_builtin): Likewise. (rs6000_init_builtins): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (MASK_FLOAT128): Add short name. (RS6000_BTM_FLOAT128): Add support for __ibm128 pack/unpack functions (RS6000_BTM_COMMON): Likewise. * config/rs6000/rs6000.md (f128_vsx): New mode attribute. (unpack<mode>): Use FMOVE128_FPR iterator instead of FMOVE128, to disallow __builtin_{pack,unpack}_longdouble if long double is IEEE 128-bit floating point. Add support for the double values to be in Altivec registers for TF/IF packing and unpacking, but restrict TD packing sub-fields to be FPR registers. Don't allow overlapped register support for packing. Allow pack inputs to be memory locations. Don't build generator functions for unpack<mode>_dm and unpack<mode>_nodm. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>): Likewise. * config/rs6000/rs6000-builtin.def (__builtin_pack_ibm128): Add built-in functions to pack/unpack explicit __ibm128 values. (__builtin_unpack_ibm128): Likewise. * doc/extend.texi (PowerPC Built-in Functions): Document __builtin_pack_ibm128 and __builtin_unpack_ibm128. [libgcc] 2016-01-13 Michael Meissner <meissner@linux.vnet.ibm.com> Steven Munroe <munroesj@linux.vnet.ibm.com> Tulio Magno Quites Machado Filho <tulioqm@br.ibm.com> * config/rs6000/sfp-exceptions.c: New file to provide exception support for IEEE 128-bit floating point. * config/rs6000/float128-hw.c: New file for ISA 3.0 IEEE 128-bit floating point hardware support. * config/rs6000/floattikf.c: New files for IEEE 128-bit floating point conversions. * config/rs6000/fixunskfti.c: Likewise. * config/rs6000/fixkfti.c: Likewise. * config/rs6000/floatuntikf.c: Likewise. * config/rs6000/extendkftf2-sw.c: Likewise. * config/rs6000/trunctfkf2-sw.c: Likewise. * config/rs6000/float128-ifunc.c: New file to pick either IEEE 128-bit floating point software emulation or use ISA 3.0 hardware support if it is available. * config/rs6000/quad-float128.h: New file to support IEEE 128-bit floating point. * config/rs6000/t-float128: New Makefile fragments to enable building __float128 emulation support. * config/rs6000/t-float128-hw: Likewise. * config/rs6000/float128-sed: New file to convert TF names to KF names for PowerPC IEEE 128-bit floating point support. * config/rs6000/sfp-machine.h (_FP_W_TYPE_SIZE): Use 64-bit types when building on 64-bit systems, or when VSX is enabled. (_FP_W_TYPE): Likewise. (_FP_WS_TYPE): Likewise. (_FP_I_TYPE): Likewise. (TItype): Define on 64-bit systems. (UTItype): Likewise. (TI_BITS): Likewise. (_FP_MUL_MEAT_D): Add support for using 64-bit types. (_FP_MUL_MEAT_Q): Likewise. (_FP_DIV_MEAT_D): Likewise. (_FP_DIV_MEAT_Q): Likewise. (_FP_NANFRAC_D): Likewise. (_FP_NANFRAC_Q): Likewise. (ISA_BIT): Add exception support if we are being compiled on a machine with hardware floating point support to build the IEEE 128-bit emulation functions. (FP_EX_INVALID): Likewise. (FP_EX_OVERFLOW): Likewise. (FP_EX_UNDERFLOW): Likewise. (FP_EX_DIVZERO): Likewise. (FP_EX_INEXACT): Likewise. (FP_EX_ALL): Likewise. (__sfp_handle_exceptions): Likewise. (FP_HANDLE_EXCEPTIONS): Likewise. (FP_RND_NEAREST): Likewise. (FP_RND_ZERO): Likewise. (FP_RND_PINF): Likewise. (FP_RND_MINF): Likewise. (FP_RND_MASK): Likewise. (_FP_DECL_EX): Likewise. (FP_INIT_ROUNDMODE): Likewise. (FP_ROUNDMODE): Likewise. * configure.ac (powerpc*-*-linux*): Check whether the PowerPC compiler can do __float128. * configure: Regenerate. * libgcc/config.host (powerpc*-*-linux*): If compiler can compile VSX code, enable IEEE 128-bit floating point. From-SVN: r232346
2016-01-13re PR target/68964 (Internal compiler error for test case ↵Richard Henderson1-48/+0
gcc.dg/tm/20100610.c since r231674) PR 68964 gcc/ PR tree-opt/68964 * target.def (builtin_tm_load, builtin_tm_store): Remove. * config/i386/i386.c (ix86_builtin_tm_load): Remove. (ix86_builtin_tm_store): Remove. (TARGET_VECTORIZE_BUILTIN_TM_LOAD): Remove. (TARGET_VECTORIZE_BUILTIN_TM_STORE): Remove. * doc/tm.texi.in (TARGET_VECTORIZE_BUILTIN_TM_LOAD): Remove. (TARGET_VECTORIZE_BUILTIN_TM_STORE): Remove. * doc/tm.texi: Rebuild. * gtm-builtins.def (BUILT_IN_TM_MEMCPY_RNWT): New. (BUILT_IN_TM_MEMCPY_RTWN): New. * trans-mem.c (tm_log_emit_stmt): Rearrange code for better fallback from vector to integer helpers. (build_tm_load): Handle vector types directly, instead of via target hook. (build_tm_store): Likewise. (expand_assign_tm): Prepare for register types not handled by the above. Copy them to memory and use memcpy. * tree.c (tm_define_builtin): New. (find_tm_vector_type): New. (build_tm_vector_builtins): New. (build_common_builtin_nodes): Call it. libitm/ * Makefile.am (libitm_la_SOURCES) [ARCH_AARCH64]: Add vect128.cc (libitm_la_SOURCES) [ARCH_ARM]: Add neon.cc (libitm_la_SOURCES) [ARCH_PPC]: Add vect128.cc (libitm_la_SOURCES) [ARCH_S390]: Add vect128.cc * configure.ac (ARCH_AARCH64): New conditional. (ARCH_PPC, ARCH_S390): Likewise. * Makefile.in, configure: Rebuild. * libitm.h (_ITM_TYPE_M128): Always define. * vect64.cc: Split ... * vect128.cc: ... out of... * config/x86/x86_sse.cc: ... here. * config/arm/neon.cc: New file. From-SVN: r232330
2016-01-13i386.h (TARGET_FLT_EVAL_METHOD): Return -1 for TARGET_SSE_MATH without ↵Uros Bizjak1-2/+5
TARGET_SSE2. * config/i386/i386.h (TARGET_FLT_EVAL_METHOD): Return -1 for TARGET_SSE_MATH without TARGET_SSE2. Rewrite. From-SVN: r232328
2016-01-13arm-arches.def: Remove spurious whitespace in "armv8.1-a" and ↵Yvan Roux1-2/+2
"armv8.1-a+crc" entries. 2016-01-13 Yvan Roux <yvan.roux@linaro.org> * config/arm/arm-arches.def: Remove spurious whitespace in "armv8.1-a" and "armv8.1-a+crc" entries. From-SVN: r232325
2016-01-13AVX512: Restrict default masks for prefetch gather/scatterAlexander Fomin2-119/+6
instructions. gcc/ PR target/69228 * config/i386/sse.md (define_expand "avx512pf_gatherpf<mode>sf"): Change first operand predicate from register_or_constm1_operand to register_operand. (define_expand "avx512pf_gatherpf<mode>df"): Likewise. (define_expand "avx512pf_scatterpf<mode>sf"): Likewise. (define_expand "avx512pf_scatterpf<mode>df"): Likewise. (define_insn "*avx512pf_gatherpf<mode>sf"): Remove. (define_insn "*avx512pf_gatherpf<mode>df"): Likewise. (define_insn "*avx512pf_scatterpf<mode>sf"): Likewise. (define_insn "*avx512pf_scatterpf<mode>df"): Likewise. * config/i386/i386.c (ix86_expand_builtin): Remove first operand comparison with constm1_rtx from vec_prefetch_gen part. gcc/testsuite PR target/69228 * gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Adjust. * gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Likewise. * gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Likewise. From-SVN: r232324
2016-01-13S/390: PR69247: Fix bswap hi splitter.Andreas Krebbel1-4/+2
gcc/ChangeLog: 2016-01-13 Andreas Krebbel <krebbel@linux.vnet.ibm.com> PR target/69247 * config/s390/s390.md (bswaphi splitter): Use simplify_gen_subreg. gcc/testsuite/ChangeLog: 2016-01-13 Jakub Jelinek <jakub@redhat.com> PR target/69247 * gcc.dg/pr69247.c: New test. From-SVN: r232318
2016-01-12re PR target/69180 ([ARM] #pragma GCC target should not warn about redefined ↵Christian Bruel1-2/+13
macros) PR target/69180 * config/arm/arm-c.c (arm_pragma_target_parse): Set NODE_CONDITIONAL for __ARM_NEON_FP, __ARM_FP, _ARM_FEATURE_LDREX. From-SVN: r232276
2016-01-12re PR target/69198 (FAIL: gcc.target/i386/avx512vl-vmovaps-1.c ↵Jakub Jelinek1-4/+4
scan-assembler-times vmovaps[ \\t]+[^{\n]*%xmm[0-9]+[^\n]*\\){%k[1-7]}(?:\n|[ \\t]+#) 1) PR target/69198 * config/i386/i386.c (ix86_expand_special_args_builtin): Ensure aligned_mem is properly set for AVX512-VL floating point masked stores. From-SVN: r232268
2016-01-12Define STDINT_LONG32 and add predefined integer types for IAMCUH.J. Lu1-0/+16
Define STDINT_LONG32 to 0, add SIZE_TYPE, PTRDIFF_TYPE and WCHAR_TYPE for IAMCU to make integer types compatible with i386 Linux. PR target/68456 PR target/69226 * config/i386/iamcu.h (SIZE_TYPE): New macro. (PTRDIFF_TYPE): Likewise. (WCHAR_TYPE): Likewise. (WCHAR_TYPE_SIZE): Likewise. (STDINT_LONG32): Likewise. From-SVN: r232266
2016-01-12[PATCH 5/6] [DJGPP] Update DJGPP configuration related filesAndris Pavenis5-70/+137
* config/i386/djgpp.h (PREFERRED_DEBUGGING_TYPE): Define to DWARF2 (TARGET_ASM_OUTPUT_IDENT): Define to default_asm_output_ident_directive (MD_EXEC_PREFIX): Remove. (MD_STARTFILE_PREFIX) Removee. (FILE_NAME_ABSOLUTE_P): Remove. (CPP_SPEC): Do not read macros from sys/version.h. (LINK_COMMAND_SPEC): Remove. (LOCAL_INCLUDE_DIR): Remove. (TARGET_ASM_NAMED_SECTION): Define to i386_djgpp_asm_named_section (TARGET_OS_CPP_BUILTINS): Add DJGPP (non ISO only), __DJGPP, __DJGPP__, unix. (POST_LINK_SPEC): Define to invoke stubify after linker (LIBSTDCXX): Remove define (DBX_REGISTER_NUMBER): Define to svr4_dbx_register_map. (DEFAULT_PCC_STRUCT_RETURN): Define to 1. (SUBTARGET_OVERRIDE_OPTIONS): Remove warning about -mbnu2210. (SUBTARGET_OVERRIDE_OPTIONS): Ignore -fPIC and generate message. (SUBTARGET_OVERRIDE_OPTIONS): Default to DWARF2 debugging info. (IX86_MAYBE_NO_LIBGCC_TFMODE): Remove. (i386_djgpp_asm_named_section): Add propotype of new procedure * config/i386/xm-djgpp.h (NATIVE_SYSTEM_HEADER_DIR): Define. (MD_EXEC_PREFIX): Define (moved from config/i386/djgpp.h). (STANDARD_STARTFILE_PREFIX_1): Define (moved from MD_STARTFILE_PREFIX in config/i386/djgpp.h). (STANDARD_STARTFILE_PREFIX_2): Define identical to STANDARD_STARTFILE_PREFIX_1. (LOCAL_INCLUDE_DIR): Define (moved from config/i386/djgpp.h). (GCC_DRIVER_HOST_INITIALIZATION): Fix reporting fatal installation errors. (MAX_OFILE_ALIGNMENT): Define to 128. (HAVE_FTW_H): Undefine as DJGPP do not have nftw, but have ftw.h. * config/i386/djgpp.c: New file. Add implementation of i386_djgpp_asm_named_section. * config/i386/djgpp.opt: Remove obsolete option -mbnu210. * config/i386/t-djgpp: New file. Add djgpp.o to EXTRA_OBJS. Add rule for building djgpp.o. From-SVN: r232258
2016-01-12rs6000.c (v2df_reduction_p): New function.Bill Schmidt1-0/+52
[gcc] 2016-01-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.c (v2df_reduction_p): New function. (rtx_is_swappable_p): Reductions are swappable. (insn_is_swappable_p): V2DF reductions are swappable. [gcc/testsuite] 2016-01-11 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/swaps-p8-23.c: New test. * gcc.target/powerpc/swaps-p8-24.c: Likewise. From-SVN: r232257
2016-01-12pa.c (pa_emit_move_sequence): Handle floating point reloads for other ↵John David Anglin1-43/+70
unsupported memory operands. * config/pa/pa.c (pa_emit_move_sequence): Handle floating point reloads for other unsupported memory operands. From-SVN: r232253
2016-01-12re PR target/69194 (internal compiler error: in extract_insn, at recog.c:2286)Kugan Vivekanandarajah1-1/+2
gcc/ChangeLog: 2016-01-12 Kugan Vivekanandarajah <kuganv@linaro.org> Jim Wilson <jim.wilson@linaro.org> PR target/69194 * config/arm/arm-builtins.c (arm_expand_neon_args): Call copy_to_mode_reg instead of force_reg. gcc/testsuite/ChangeLog: 2016-01-12 Kugan Vivekanandarajah <kuganv@linaro.org> Jim Wilson <jim.wilson@linaro.org> PR target/69194 * gcc.target/arm/pr69194.c: New test. Co-Authored-By: Jim Wilson <jim.wilson@linaro.org> From-SVN: r232251
2016-01-11Set FLT_EVAL_METHOD to 2 only if 387 FPU is usedH.J. Lu1-1/+1
When 387 FPU isn't used, there is no excess precision. We should set FLT_EVAL_METHOD to 2 only if 387 FPU is used. gcc/ PR target/69225 * config/i386/i386.h (TARGET_FLT_EVAL_METHOD): Set to 2 only if TARGET_80387 is true. gcc/testsuite PR target/69225 * gcc.target/i386/pr69225-1.c: New test. * gcc.target/i386/pr69225-2.c: Likewise. * gcc.target/i386/pr69225-3.c: Likewise. * gcc.target/i386/pr69225-4.c: Likewise. * gcc.target/i386/pr69225-5.c: Likewise. * gcc.target/i386/pr69225-6.c: Likewise. From-SVN: r232249
2016-01-11[AArch64] PR rtl-optimization/68796: Add patterns for QImode and HImode ↵Kyrylo Tkachov3-0/+19
comparison with zero PR rtl-optimization/68796 * config/aarch64/aarch64.md (*and<mode>_compare0): New pattern. * config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle HImode and QImode comparisons against zero with CC_NZmode. * config/aarch64/iterators.md (short_mask): New mode_attr. * gcc.target/aarch64/tst_5.c: New test. * gcc.target/aarch64/tst_6.c: Likewise. From-SVN: r232228
2016-01-11Remove snprintf from <avx512>_(load|store)<mode>_maskH.J. Lu1-36/+16
This patch removes snprintf from <avx512>_(load|store)<mode>_mask patterns. * config/i386/sse.md (<avx512>_load<mode>_mask): Remove snprintf. (<avx512>_store<mode>_mask): Likewise. From-SVN: r232225
2016-01-11re PR rtl-optimization/68920 (Undesirable if-conversion for a rarely taken ↵Yuri Rumyantsev3-0/+14
branch) gcc/ 2016-01-11 Yuri Rumyantsev <ysrumyan@gmail.com> PR rtl-optimization/68920 * config/i386/i386.c (ix86_option_override_internal): Restrict number of conditional moves for RTL if-conversion to 1 for TARGET_ONE_IF_CONV_INSN. * config/i386/i386.h (TARGET_ONE_IF_CONV_INSN): New macros. * config/i386/x86-tune.def (X86_TUNE_ONE_IF_CONV_INSN): New macros. * params.def (PARAM_MAX_RTL_IF_CONVERSION_INSNS) : Introduce new parameter to restirct number of conditional moves for RTL if-conversion. * doc/invoke.texi (max-rtl-if-conversion-insns): Document it. * ifcvt.c (bb_ok_for_noce_convert_multiple_sets): Limit number of conditionl moves. gcc/testsuite/ 2016-01-11 Yuri Rumyantsev <ysrumyan@gmail.com> PR rtl-optimization/68920 * gcc.dg/ifcvt-4.c: Add "--param max-rtl-if-conversion-insns=3" option for ix86 targets. * gcc.dg/ifcvt-5.c: New test. From-SVN: r232220
2016-01-11arc.opt (mdiv-rem): Add period to the end.Andrew Burgess1-2/+2
2016-01-11 Andrew Burgess <andrew.burgess@embecosm.com> * config/arc/arc.opt (mdiv-rem): Add period to the end. (mcode-density): Likewise. From-SVN: r232207
2016-01-08vxworks.h (VXWORKS_LIBGCC_SPEC): Don't link shared RTPs with libc_internal.Olivier Hainque1-5/+5
* config/vxworks.h (VXWORKS_LIBGCC_SPEC): Don't link shared RTPs with libc_internal. From-SVN: r232164
2016-01-08[PATCH][RS6000] Migrate reduction optabs in paired.mdAlan Lawrence1-11/+28
* gcc.target/rs6000/paired.md (reduc_smax_v2sf): Rename to... (reduc_smax_scal_v2sf): ...here, make result SFmode, extract element. (reduc_smin_v2sf): Rename to... (reduc_smin_scal_v2sf): ...here, make result SFmode, extract element. (reduc_splus_v2sf): Rename to... (reduc_plus_scal_v2sf): ...here, make result SFmode, extract element. From-SVN: r232158
2016-01-07freebsd.h: Rename SUBTARGET_OVERRIDE_OPTIONS to ↵Andreas Tobler2-4/+10
SUBTARGET_OVERRIDE_INTERNAL_OPTIONS. 2016-01-07 Andreas Tobler <andreast@gcc.gnu.org> * config/arm/freebsd.h: Rename SUBTARGET_OVERRIDE_OPTIONS to SUBTARGET_OVERRIDE_INTERNAL_OPTIONS. Adjust to check unaligned_access on the gcc_options set. * config/arm/arm.c (arm_option_override_internal): Use SUBTARGET_OVERRIDE_INTERNAL_OPTIONS. From-SVN: r232141
2016-01-07re PR target/69140 (stack alignment + O1 breaks with Microsoft ABI)Uros Bizjak1-2/+4
2016-01-07 Uros Bizjak <ubizjak@gmail.com> PR target/69140 * config/i386/i386.c (ix86_frame_pointer_required): Enable frame pointer for TARGET_64BIT_MS_ABI when stack is misaligned. 2016-01-07 Uros Bizjak <ubizjak@gmail.com> Revert 2016-01-06 Uros Bizjak <ubizjak@gmail.com> PR target/69140 * config/i386/i386.c (ix86_expand_prologue): Declare fs.sp_valid depending on frame_pointer_needed before remaining integer and SSE registers are saved. From-SVN: r232140
2016-01-07Add round_nimm_scalar_predicate and use xBmH.J. Lu2-15/+22
Add round_nimm_scalar_predicate for scalar SSE integer to floating point conversions since round_nimm_predicate is for vector operand. round_constraint can't be used on vector SSE patterns since it is mapped to "vm". The "xBm" constraint must be used in this case. gcc/ PR target/69171 * config/i386/sse.md (<sse>_sqrt<mode>2<mask_name><round_name>): Use the "xBm" constraint. (float<sseintvecmodelower><mode>2<mask_name><round_name): Likewise. (sse_cvtsi2ss<round_name>): Use round_nimm_scalar_predicate. (sse_cvtsi2ssq<round_name>): Likewise. (sse_cvtss2si<round_name>): Likewise. (sse_cvtss2siq<round_name>): Likewise. (sse2_cvtsi2sdq<round_name>): Likewise. (sse2_cvtsd2si<round_name>): Likewise. (sse2_cvtsd2siq<round_name>): Likewise. * config/i386/subst.md (round_nimm_scalar_predicate): New predicate. gcc/testsuite/ PR target/69171 * gcc.target/i386/pr69171-1.c: New test. * gcc.target/i386/pr69171-2.c: Likewise. * gcc.target/i386/pr69171-3.c: Likewise. * gcc.target/i386/pr69171-4.c: Likewise. * gcc.target/i386/pr69171-5.c: Likewise. * gcc.target/i386/pr69171-6.c: Likewise. From-SVN: r232126
2016-01-06Reorder function types.Robert Suchanek1-6/+6
* config/mips/mips-ftypes.def: Sort to lexicographical order. From-SVN: r232113
2016-01-06re PR target/69140 (stack alignment + O1 breaks with Microsoft ABI)Uros Bizjak1-0/+2
PR target/69140 * config/i386/i386.c (ix86_expand_prologue): Declare fs.sp_valid depending on frame_pointer_needed before remaining integer and SSE registers are saved. testsuite/ChangeLog: PR target/69140 * gcc.target/i386/pr69140.c: New test From-SVN: r232111
2016-01-06vsx.md (*p9_vecload_<mode>): Replace VSX_M mode iterator with VSX_M2.Bill Schmidt1-11/+11
[gcc] 2015-01-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/vsx.md (*p9_vecload_<mode>): Replace VSX_M mode iterator with VSX_M2. (*p9_vecstore_<mode>): Likewise. (*vsx_le_permute_<mode>): Restrict to !TARGET_P9_VECTOR. (*vsx_le_perm_load_<mode> for VSX_LE_128): Likewise. (*vsx_le_perm_store_<mode> for VSX_LE_128): Likewise. (define_split for VSX_LE128 stores): Likewise. (define_peephole2 for TImode LE swaps): Likewise. (define_split for VSX_LE128 post-reload stores): Likewise. [gcc/testsuite] 2015-01-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/p9-lxvx-stxvx-3.c: New test. From-SVN: r232109
2016-01-05Use vector_operand on SSE with 16b memory operandH.J. Lu4-245/+252
Add vector_operand, which is vector_memory_operand or register_operand, and use it, instead of nonimmediate_operand, in SSE patterns with 16-byte memory operand. gcc/ PR target/68991 * config/i386/i386.c (ix86_expand_vector_logical_operator): Replace nonimmediate_operand with vector_operand. * config/i386/predicates.md (vector_operand): New predicate. (general_vector_operand): Replace nonimmediate_operand with vector_operand. * config/i386/sse.md: Replace nonimmediate_operand with vector_operand and m constraint with Bm constraint on SSE patterns with 16-byte memory operand. * config/i386/subst.md (round_nimm_predicate): Replace nonimmediate_operand with vector_operand. (round_saeonly_nimm_predicate): Likewise. (round_saeonly_nimm_scalar_predicate): New. gcc/testsuite/ PR target/68991 * gcc.target/i386/pr68991.c: New test. From-SVN: r232088
2016-01-05Add vector_memory_operand and "Bm" constraintH.J. Lu3-9/+21
SSE vector arithmetic and logic instructions only accept aligned memory operand. This patch adds vector_memory_operand and "Bm" constraint for aligned SSE memory operand. They are applied to SSE plusminus and any_logic patterns. gcc/ PR target/68991 * config/i386/constraints.md (Bm): New constraint. * config/i386/predicates.md (vector_memory_operand): New predicate. * config/i386/sse.md: Replace xm with xBm in plusminus and any_logic patterns. gcc/testsuite/ PR target/68991 * g++.dg/pr68991-1.C: New test. * g++.dg/pr68991-2.C: Likewise. From-SVN: r232087
2016-01-05[PATCH v2] ia64: don't use dynamic relocations for local symbols PR other/60465Sergei Trofimovich2-0/+35
[PATCH v2] ia64: don't use dynamic relocations for local symbols PR other/60465 * config/ia64/ia64.c (ia64_expand_load_address): Use gprel64 for local symbolic operands. * config/ia64/predicates.md (local_symbolic_operand64): New predicate. PR other/60465 * gcc.target/ia64/pr60465-gprel64.c: New test. * gcc.target/ia64/pr60465-gprel64-c37.c: New test. From-SVN: r232080
2016-01-05re PR target/66655 (miscompilation due to ipa-ra on MinGW)Nick Clifton1-0/+5
PR target/66655 * config/i386/cygming.h (MAKE_DECL_ONE_ONLY): Define to use weak decls if weak support is available. From-SVN: r232071
2016-01-04rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add OPTION_MASK_P9_DFORM.Michael Meissner1-0/+1
2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add OPTION_MASK_P9_DFORM. From-SVN: r232061
2016-01-04constraints.md (wo constraint): New constraint for ISA 3.0 (power9).Michael Meissner4-40/+69
[gcc] 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wo constraint): New constraint for ISA 3.0 (power9). * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support for wo constraint. (rs6000_init_hard_regno_mode_ok): Likewise. * config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for wo constraint. * config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm expanders not to have constraints. Add support for ISA 3.0 xxperm instruction. Add support for fusing xxlor with xxperm. (altivec_vperm_<mode>_internal): Likewise. (altivec_vperm_v8hiv16qi): Likewise. (altivec_vperm_<mode>v16q): Likewise. (altivec_vperm_<mode>_uns): Likewise. (vperm_v8hiv4si): Likewise. (vperm_v16qiv8hi): Likewise. * doc/md.texi (RS/6000 constraints): Document wo constraint. [gcc/testsuite] 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-permute.c: New test for xxperm code generation. From-SVN: r232060
2016-01-04Update copyright years.Jakub Jelinek1338-1354/+1352
From-SVN: r232055
2016-01-04arm.c (aapcs_vfp_allocate_return_reg): Treat all integer modes larger than ↵Eric Botcazou1-1/+4
TImode as TImode if NEON is not enabled. * config/arm/arm.c (aapcs_vfp_allocate_return_reg): Treat all integer modes larger than TImode as TImode if NEON is not enabled. From-SVN: r232051
2016-01-04re PR target/69100 (ICE in final_scan_insn with -msoft-float and ↵Eric Botcazou1-3/+2
__builtin_apply) PR target/69100 * config/sparc/sparc.h (FUNCTION_ARG_REGNO_P): Return true in 64-bit mode for %f0-%f31 only if TARGET_FPU. From-SVN: r232050
2016-01-04re PR target/69072 (ICE in function_arg_record_value on 7th packed structure)Eric Botcazou1-19/+17
PR target/69072 * config/sparc/sparc.c (scan_record_type): Take into account subfields to compute the PACKED_P predicate. (function_arg_record_value): Minor tweaks. From-SVN: r232049
2016-01-01re PR target/68917 (test suite failure for builtin-bitops-1.c)Bernd Edlinger1-4/+7
PR target/68917 * config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of SI values. Explicitly convert SI to DI and vice-versa. From-SVN: r232028
2015-12-30nvptx.c (nvptx_assemble_undefined_decl): Check it's not a constant pool object.Nathan Sidwell1-0/+5
* config/nvptx/nvptx.c (nvptx_assemble_undefined_decl): Check it's not a constant pool object. From-SVN: r232003
2015-12-29rs6000.c (init_float128_ieee): Remove IEEE 128-bit comparison functions in ↵Michael Meissner4-86/+123
cmp_optab and ucmp_optab. 2015-12-29 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (init_float128_ieee): Remove IEEE 128-bit comparison functions in cmp_optab and ucmp_optab. (rs6000_generate_compare): Rewrite IEEE 128-bit floating point software emulation comparisons to only use __eqkf2, __gekf2, __lekf2, and __unordkf2 functions. (rs6000_invalid_binary_op): Add support for -mfloat128-convert. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define __FLOAT128_HARDWARE__ if hardware IEEE 128-bit support is available. * config/rs6000/rs6000.opt (-mfloat128-convert): Add debug switch to allow IBM extended double and IEEE 128-bit floating point to be converted with default conversions. * config/rs6000/rs6000.md (extendkftf2): Add converters between KFmode and TFmode if -mabi=ieeelongdouble. (trunctfkf2): Likewise. (ieee128_mfvsrd): Split 64-bit integer conversions into 32-bit and 64-bit insns. (ieee128_mfvsrd_64bit): Likewise. (ieee128_mfvsrd_32bit): Likewise. (ieee128_mtvsrd): Likewise. (ieee128_mtvsrd_64bit): Likewise. (ieee128_mtvsrd_32bit): Likewise. * doc/extend.texi (Floating Types): Document that complex __float128 does not work currently. * doc/invoke.texi (RS/6000 and PowerPC Options): Document that -mfloat128 is only supported on PowerPC 64-bit Linux systems. From-SVN: r231996
2015-12-28rs6000.c (rs6000_emit_le_vsx_move): Verify that this is never called when ↵Bill Schmidt3-31/+51
lxvx/stxvx are available. [gcc] 2015-12-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Verify that this is never called when lxvx/stxvx are available. (pass_analyze_swaps::gate): Don't perform swap optimization when lxvx/stxvx are available. * config/rs6000/vector.md (mov<mode>): Don't call rs6000_emit_le_vsx_move when lxvx/stxvx are available. * config/rs6000/vsx.md (*p9_vecload_<mode>): New define_insn. (*p9_vecstore_<mode>): Likewise. (*vsx_le_perm_load_<mode>:VSX_LE): Disable when lxvx/stxvx are available. (*vsx_le_perm_load_<mode>:VSX_W): Likewise. (*vsx_le_perm_load_v8hi): Likewise. (*vsx_le_perm_load_v16qi): Likewise. (*vsx_le_perm_store_<mode>:VSX_LE): Likewise. ([related define_splits]): Likewise. (*vsx_le_perm_store_<mode>:VSX_W): Likewise. ([related define_splits]): Likewise. (*vsx_le_perm_store_v8hi): Likewise. ([related define_splits]): Likewise. (*vsx_le_perm_store_v16qi): Likewise. ([related define_splits]): Likewise. (*vsx_lxvd2x2_le_<mode>): Likewise. (*vsx_lxvd2x4_le_<mode>): Likewise. (*vsx_lxvd2x8_le_V8HI): Likewise. (*vsx_lvxd2x16_le_V16QI): Likewise. (*vsx_stxvd2x2_le_<mode>): Likewise. (*vsx_stxvd2x4_le_<mode>): Likewise. (*vsx_stxvd2x8_le_V8HI): Likewise. (*vsx_stxvdx16_le_V16QI): Likewise. ([define_peepholes for vector load fusion]): Likewise. [gcc/testsuite] 2015-12-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.target/powerpc/p9-lxvx-stxvx-1.c: New. * gcc.target/powerpc/p9-lxvx-stxvx-2.c: New. From-SVN: r231974
2015-12-28nvptx.c (nvptx_output_call_insn): Expect hard regs.Nathan Sidwell2-21/+17
* config/nvptx/nvptx.c (nvptx_output_call_insn): Expect hard regs. * config/nvptx/nvptx.md (nvptx_reg_or_mem_operand): Rename to ... (nvptx_nonimmediate_operand): ... here. Update all uses. (call_insn_operand): Use REG_P. (call_operation): Allow hard regs. From-SVN: r231972
2015-12-25freebsd64.h: Delete FREEBSD_DYNAMIC_LINKER32/64 defines.Andreas Tobler1-19/+4
2015-12-25 Andreas Tobler <andreast@gcc.gnu.org> * config/rs6000/freebsd64.h: Delete FREEBSD_DYNAMIC_LINKER32/64 defines. Use FBSD_DYNAMIC_LINKER instead. Rename and simplify LINK_OS_FREEBSD_SPEC_DEF32/64 to LINK_OS_FREEBSD_SPEC_DEF. From-SVN: r231955
2015-12-24Add missing intrinsic file.Kirill Yukhin1-0/+56
From-SVN: r231945
2015-12-24Introduce support for PKU instructions.Kirill Yukhin8-4/+77
gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PKU_SET): New. (OPTION_MASK_ISA_PKU_UNSET): Ditto. (ix86_handle_option): Handle OPT_mpku. * config.gcc: Add pkuintrin.h to i[34567]86-*-* and x86_64-*-* targets. * config/i386/cpuid.h (host_detect_local_cpu): Detect PKU feature. * config/i386/i386-c.c (ix86_target_macros_internal): Handle PKU ISA flag. * config/i386/i386.c (ix86_target_string): Add "-mpku" to ix86_target_opts. (ix86_option_override_internal): Define PTA_PKU, mention new key in skylake-avx512. Handle new ISA bits. (ix86_valid_target_attribute_inner_p): Add "pku". (enum ix86_builtins): Add IX86_BUILTIN_RDPKRU and IX86_BUILTIN_WRPKRU. (builtin_description bdesc_special_args[]): Add new built-ins. * config/i386/i386.h (define TARGET_PKU): New. (define TARGET_PKU_P): Ditto. * config/i386/i386.md (define_c_enum "unspecv"): Add UNSPEC_PKU. (define_expand "rdpkru"): New. (define_insn "*rdpkru"): Ditto. (define_expand "wrpkru"): Ditto. (define_insn "*wrpkru"): Ditto. * config/i386/i386.opt (mpku): Ditto. * config/i386/pkuintrin.h: New file. * config/i386/x86intrin.h: Include pkuintrin.h * doc/extend.texi: Describe new built-ins. * doc/invoke.texi: Describe new switches. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpku. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/rdpku-1.c: New test. * gcc.target/i386/sse-12.c: Add -mpku. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-33.c: Ditto. * gcc.target/i386/wrpku-1.c: New test. From-SVN: r231944
2015-12-23* config/nvptx/nvptx-protos.hNathan Sidwell3-64/+11
(nvptx_maybe_convert_symbolic_operand): Delete prototype. * config/nvptx/nvptx.c (nvptx_maybe_convert_symbolic_operand): Delete. (nvptx_output_mov_insn): Record fnsym here. (nvptx_wpropagate): Don't create UNSPEC_TO_GENERIC unspec. * config/nvptx/nvptx.md (UNSPEC_TO_GENERIC): Delete. (symbolic_operand): Delete predicate. (nvptx_nonimmediate_operand): Delete predicate. (mov<mode>): Hard regs are perfectly ok here. (convaddr_<mode>): Delete. From-SVN: r231930
2015-12-23Fix broken handling of LABEL_REF in genrecog + genpreds.Dominik Vogt1-4/+1
gcc/ChangeLog * config/s390/predicates.md ("larl_operand"): Remove now superfluous const_int and const_double. * genrecog.c (safe_predicate_mode): Return false for VOIDmode LABEL_REFs even if the predicate does not handle const_int, const_double or const_wide_int. * genpreds.c (add_mode_tests): Treat LABEL_REF like CONST_INT. From-SVN: r231927
2015-12-23iterators.md (VMAXMINFNM): New int iterator.David Sherwood4-0/+34
2015-12-23 David Sherwood <david.sherwood@arm.com> gcc/ * config/arm/iterators.md (VMAXMINFNM): New int iterator. (fmaxmin): New int attribute. (fmaxmin_op): Likewise. * config/arm/unspecs.md (UNSPEC_VMAXNM): New unspec. (UNSPEC_VMINNM): Likewise. * config/arm/neon.md (fmaxmin): New pattern. * config/arm/vfp.md (fmaxmin): Likewise. gcc/testsuite * gcc.target/arm/fmaxmin.x: New file used by tests below. * gcc.target/arm/fmaxmin.c: New test. * gcc.target/arm/vect-fmaxmin.c: Likewise. From-SVN: r231924
2015-12-23[PATCH] Allow indirect call via GOT for 64-bit Pmode x32H.J. Lu2-18/+26
From: H.J. Lu <hongjiu.lu@intel.com> Since Pmode is 64-bit with -maddress-mode=long for x32, indirect call via GOT slot doesn't need zero_extend. This patch enables indirect call via GOT for x32 with 64-bit Pmode. gcc/ PR target/66232 * config/i386/constraints.md (Bs): Allow GOT slot for x32 with 64-bit Pmode. (Bw): Likewise. (Bz): Likewise. * config/i386/predicates.md (call_insn_operand): Likewise. (sibcall_insn_operand): Likewise. gcc/testsuite/ PR target/66232 * gcc.target/i386/pr66232-10.c: New test. * gcc.target/i386/pr66232-11.c: Likewise. * gcc.target/i386/pr66232-12.c: Likewise. * gcc.target/i386/pr66232-13.c: Likewise. From-SVN: r231923
generated by cgit v1.1 at 2024-10-03 13:31:50 +0000